10XS3412

10XS3412_09 FREESCALE | Alldatasheet

Document overview

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• PDF pages: 53

Technical content

Features

• Four protected 10 mΩ and 12 mΩ high side switches (at 25°C)
• Operating voltage range of 6.0 V to 20 V with sleep current < 5.0 μA, extended mode from 4.0 V to 28 V
• 8 . 0 MHz 16-bit 3.3 V and 5.0 V SPI control and status reporting with daisy chain capability
• PWM module using external clock or calibratable internal oscillator with programmable outputs delay management
• Smart over-current shutdown, severe short-circuit, over- temperature protections with time limited autoretry, and fail-safe mode in case of MCU damage
• Output OFF or ON open-load detection compliant to bulbs or LEDs and short to battery detection. Analog current feedback with selectable ratio and board temperature feedback.
• Pb-free packaging designated by suffix code DPNA

Figure 1. 10XS3412 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MC10XS3412CPNA - 40°C to 125°C 24 PQFN MC10XS3412DPNA MCU 10XS3412 VDD VDD VPWR VDD VPWR WAKE FS SCLK CS SO RST SI IN0 IN1 IN2 IN3 CSNS FSI GND VDD VPWR HS0 HS1 HS2 HS3 LOADI/O SCLK CS SI I/O SO I/O I/O I/O I/O A/D GND LOAD LOAD LOAD

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Table 1. Device Variations

1. Pin soldering temperature limit is for 10 seconds maximum dur ation. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

1. Freescale’s Package Reflow capability meets Pb-free require ments for JEDEC standard J-STD-020C. For Peak Package Reflow

enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics.

Figure 2. 10XS3412 Simplified Internal Block Diagram

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Figure 3. 10XS3412 Pin Connections Table 2. 10XS3412 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 24.

1 CSNS Output Output Current

recopy and temperature feedback is SPI programmable. are used to directly control HS0 : HS3 high side output pins.

7 FS Output Fault Status

resistor to VDD for fault reporting. 8 WAKE Input Wake This input pin controls the device mode.

9 RST Input Reset This input pin is used to initialize the device configuration and fault registers,

as well as place the device in a low-current Sleep Mode.

10 CS Input Chip Select

12 SI Input Serial Input This pin is a command data input pin connected to the SPI serial data output

of the MCU or to the SO pin of the previous device of a daisy-chain of devices.

of the device. These ground pins must be also shorted in the board. the SI pin of the next device of a daisy-chain of devices. 4, 20 NC N/A No Connect These pins may not be connected. 24 FSI Input Fail-safe Input This input enables the watchdog timeout feature. Table 2. 10XS3412 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 24.

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ELECTRICAL CHARACTERISTICS

Table 3. Maximum Ratings permanent damage to the device.

1. Continuous high side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output

current using package thermal resistance is required.

1. Active clamp energy using single-pulse method (L = 2.0 mH, RL = 0 Ω, VPWR = 14 V, TJ = 150°C initial).
2. ESD testing is performed in accordance with the Human Body Model (HBM) (C ZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (MM)

(CZAP = 200 pF, RZAP = 0 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF).

1. Input / Output pins are: IN[0:3], RSTB, FSI, CSNS, SI, SCLK, CSB, SO, FSB

Analog Integrated Circuit Device Data Freescale Semiconductor 7 10XS3412 Thermal Resistance(7) Junction to Case Junction to Ambient RθJC RθJA <1.0 °C/ W Peak Package Reflow Temperature During Reflow(8), (9) TPPRT Note 9 °C Notes 7. Device mounted on a 2s2p test board per JEDEC JESD51-2. 15 °C/W of R θJA can be reached in a real application case (4 layers board). 8. Pin soldering temperature limit is for 10 seconds maximum dura tion. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 9. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics. Table 3. Maximum Ratings (continued) permanent damage to the device.

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STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics

8.0 MHz SPI Communication(12)

1. In extended mode, the functionality is guaranteed but not the electrical parameters. From 4.0 V to 6.0 V voltage range, the device is only

protected with the thermal shutdown detection.

1. Measured with the outputs open.
2. Typical value guaranteed per design.
3. Output will automatically recover with time limited autoretry to instructed state when V PWR voltage is restored to normal as long as the

supplied by VPWR and assumes that the external VDD supply is within specification.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 10XS3412 STATIC ELECTRICAL CHARACTERISTICS OUTPUTS HS0 TO HS3 HS[0,1] Output Drain-to-Source ON Resistance (IHS = 5.0 A, TA = 25°C) VPWR = 4.5 V VPWR = 6.0 V VPWR = 10 V VPWR = 13 V RDS_01(ON) mΩ HS[0,1] Output Drain-to-Source ON Resistance (IHS = 5.0 A, TA = 150°C) VPWR = 4.5 V VPWR = 6.0 V VPWR = 10 V VPWR = 13 V RDS_01(ON) mΩ HS[0,1] Output Source-to-Drain ON Resistance (IHS = -5.0 A, VPWR = -18 V)(14) TA = 25°C TA = 150°C RSD_01(ON) mΩ HS[2,3] Output Drain-to-Source ON Resistance (IHS = 5.0 A, TA = 25°C) VPWR = 4.5 V VPWR = 6.0 V VPWR = 10 V VPWR = 13 V RDS_23(ON) mΩ HS[2,3] Output Drain-to-Source ON Resistance (IHS = 5.0 A, TA = 150°C) VPWR = 4.5 V VPWR = 6.0 V VPWR = 10 V VPWR = 13 V RDS_23(ON) mΩ HS[2,3] Output Source-to-Drain ON Resistance (IHS = -5.0 AVPWR = -18 V)(14) TA = 25°C TA = 150°C RSD_23(ON) mΩ Maximum Severe Short-Circuit Impedance Detection(15) RSHORT 28 64 100 mΩ Notes 14. Source-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VPWR. 15. Short-circuit impedance calcul ated from HS[0:3] to GND pins. Value guaranteed per design. Table 4. Static Electrical Characteristics (continued)

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STATIC ELECTRICAL CHARACTERISTICS Output Over-current Detection Levels (6.0 V < VHS[0:3] < 20 V)

28 W bit = 0

28 W bit = 1

OCHI1_0 OCHI2_0 OC1_0 OC2_0 OC3_0 OC4_0 OCLO4_0 OCLO3_0 OCLO2_0 OCLO1_0 OCHI1_1 OCHI2_1 OC1_1 OC2_1 OC3_1 OC4_1 OCLO4_1 OCLO3_1 OCLO2_1 OCLO1_1 44.1 37.8 31.5 25.2 18.9 12.6 10.0 6.4 22.0 18.9 15.7 12.6 9.4 6.0 4.5 3.0 94.0 60.0 52.5 45.0 37.5 30.0 22.5 15.0 12.0 8.0 47.0 30.0 26.2 22.5 18.7 15.0 11.2 7.5 6.0 4.0 110 60.9 52.2 43.5 34.8 26.1 17.4 14.0 9.6 30.5 26.1 21.8 17.4 13.1 9.0 7.5 5.0 A Current Sense Ratio (6.0 V < HS[0:3] < 20 V, CSNS < 5.0 V)(16) CSNS_ratio bit = 0 CSNS_ratio bit = 1 CSNS_ratio bit = 0 CSNS_ratio bit = 1 CSR0_0 CSR1_0 CSR0_1 CSR1_1 Current Sense Ratio (CSR0) Accuracy (6.0 V < VHS[0:3] < 20 V) with 28 W bit=0 Output Current 12.5 A 5.0 A 3.0 A 1.5 A CSR0_0_ACC -12 -13 -16 -20 Notes 16. Current sense ratio = I CSNS / IHS[0:3]

Analog Integrated Circuit Device Data Freescale Semiconductor 11 10XS3412 STATIC ELECTRICAL CHARACTERISTICS Current Sense Ratio (CSR0) Accuracy (6.0 V < VHS < 20 V) with 28 W bit=1 Output Current 3.0 A 1.5 A CSR0_1_ACC -16 -20 CSR0 Current Recopy Accuracy with one calibration point (6.0 V < VHS[0:3] <

20 V)(17)

5.0 A CSR0_0_ACC( CAL) -5.0 – 5.0 % Notes 17. Based on statistical analysis. It is not production tested.

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STATIC ELECTRICAL CHARACTERISTICS OUTPUTS HS0 TO HS3 (continued) CSR0 Current Recopy Temperature Drift (6.0 V < VHS[0:3] < 20 V) with 28 W bit=0(18) Output Current 5.0 A Δ(CSR0_0)/ Δ(T) 0.04 %/°C Current Sense Ratio (CSR1) Accuracy (6.0 V < VHS[0:3] < 20 V) with 28 W bit=0 Output Current 12.5 A 75 A CSR1_0_ACC -17 -12 +17 +12 Current Sense Clamp Voltage CSNS Open; IHS[0:3] = 5.0 A with CSR0 ratio VCL(CSNS) VDD+0.25 VDD+1.0 V OFF Open-load Detection Source Current(19) IOLD(OFF) 30 – 100 μA OFF Open-load Fault Detection Voltage Threshold VOLD(THRES) 2.0 3.0 4.0 V ON Open-load Fault Detection Current Threshold IOLD(ON) 100 300 600 mA ON Open-load Fault Detection Current Threshold with LED VHS[0:3] = VPWR - 0.75 V IOLD(ON_LED) 2.5 5.0 10 mA Output Short to VPWR Detection Voltage Threshold Output programmed OFF VOSD(THRES) VPWR-1.2 VPWR-0.8 VPWR-0.4 V Output Negative Clamp Voltage 0.5 A < IHS[0:3] < 5.0 A, Output programmed OFF VCL - 22 – -16 V Output Over-temperature Shutdown for 4.5 V < VPWR < 28 V TSD 155 175 195 °C Notes 18. Based on statistical data: delta(C SR0)/delta(T)={(measured ICSNS at T1 - measured ICSNS at T2) / measured ICSNS at room} / {T1-T2}. No production tested. 19. Output OFF Open-Load Detection Current is the current require d to flow through the load for the purpose of detecting the existence of an open-load condition when the specific output is commanded OFF. Pull-up current is measured for VHS=VOLD(THRES)

Analog Integrated Circuit Device Data Freescale Semiconductor 13 10XS3412 STATIC ELECTRICAL CHARACTERISTICS CONTROL INTERFACE Input Logic High Voltage(20) VIH 2.0 – VDD+0.3 V Input Logic Low Voltage(20) VIL -0.3 – 0.8 V Input Logic Pull-down Current (SCLK, SI)(23) IDWN 5.0 – 20 μA Input Logic Pull-up Current (CS)(24) IUP 5.0 – 20 μA SO, FS Tri-state Capacitance(21) CSO – – 20 pF Input Logic Pull-down Resistor (RST, WAKE and IN[0:3]) RDWN 125 250 500 kΩ Input Capacitance(21) CIN – 4.0 12 pF Wake Input Clamp Voltage(22), ICL(WAKE) < 2.5 mA 10XS3412C 10XS3412D VCL(WAKE) V Wake Input Forward Voltage ICL(WAKE) = -2.5 mA VF(WAKE) - 2.0 – - 0.3 V SO High state Output Voltage IOH = 1.0 mA VSOH VDD-0.4 – – V SO and FS Low state Output Voltage IOL = -1.0 mA VSOL – – 0.4 V SO, CSNS and FS Tri-state Leakage Current CS = VIH and 0 V < VSO < VDD, or FS = 5.5 V, or CSNS=0.0 V ISO(LEAK) - 2.0 0 2.0 μA FSI External Pull-down Resistance(25) Watchdog Disabled Watchdog Enabled RFS – Infinite 1.0 kΩ Notes 20. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:3] and WAKE input signals. The WAKE and RST signals may be supplied by a derived voltage referenced to VPWR. 21. Input capacitance of SI, CS, SCLK, RST, IN[0:3] and WAKE. This parameter is guaranteed by process monitoring but is not production tested. 22. The current must be limited by a series resistance when using voltages > 7.0 V. 23. Pull-down current is with V SI > 1.0 V and VSCLK > 1.0 V. 24. Pull-up current is with V CS < 2.0 V. CS has an active internal pull-up to VDD. 25. In Fail-safe HS[0:3] depends respectively on ON [0:3]. FSI has an active internal pull-up to VREG ~ 3.0 V.

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DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics

1. Rise and Fall Slew Rates measured across a 5.0 Ω resistive load at high side output = 30% to 70% (see Figure 4, page 21).
2. Turn-ON delay time measured fr om rising edge of any signal (IN[0 : 3] and CS) that would turn the output ON to VHS[0 : 3] = VPWR / 2 with

to VHS[0 : 3] =VPWR / 2 with RL = 5.0 Ω resistive load.

Analog Integrated Circuit Device Data Freescale Semiconductor 15 10XS3412 DYNAMIC ELECTRICAL CHARACTERISTICS POWER OUTPUT TIMING HS0 TO HS3 (CONTINUED) Fault Detection Blanking Time(28) 10XS3412C 10XS3412D tFAULT 5.0 5.0 μs Output Shutdown Delay Time(29) 10XS3412C 10XS3412D tDETECT 7.0 7.0 μs CSNS Valid Time(30) t CNSVAL – 70 100 μs Watchdog Timeout(31) t WDTO 217 310 400 ms ON Open-load Fault Cyclic Detection Time with LED - fIN0 / 128 - ms Notes 28. Time necessary to report the fault to FS pin. 29. Time necessary to switch off the output in case of OT or OC or SC or UV fault detection (from negative edge of FS pin to HS voltage = 50% of VPWR 30. Time necessary for CSNS to be within ±5% of the targeted value (from HS voltage = 50% of V PWR to ±5% of the targeted CSNS value). 31. For FSI open, the Watchdog timeout delay measured from the rising edge of RST, to HS[0,2] output state depend on the corresp onding input command. Table 5. Dynamic Electrical Characteristics (continued)

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DYNAMIC ELECTRICAL CHARACTERISTICS Output Over-current Time Step for 28 W bit = 0 OC[1:0]=00 (slow by default) OC[1:0]=01 (fast) OC[1:0]=10 (medium) OC[1:0]=11 (very slow) tOC1_00 tOC2_00 tOC3_00 tOC4_00 tOC5_00 tOC6_00 tOC7_00 tOC1_01 tOC2_01 tOC3_01 tOC4_01 tOC5_01 tOC6_01 tOC7_01 tOC1_10 tOC2_10 tOC3_10 tOC4_10 tOC5_10 tOC6_10 tOC7_10 tOC1_11 tOC2_11 tOC3_11 tOC4_11 tOC5_11 tOC6_11 tOC7_11 4.40 1.62 2.10 2.88 4.58 10.16 73.2 1.10 0.40 0.52 0.72 1.14 2.54 18.2 2.20 0.81 1.05 1.44 2.29 5.08 36.6 8.8 3.2 4.2 5.7 9.1 20.3 146.4 6.30 2.32 3.00 4.12 6.56 14.52 104.6 1.57 0.58 0.75 1.03 1.64 3.63 26.1 3.15 1.16 1.50 2.06 3.28 7.26 52.3 12.6 4.6 6.0 8.2 13.1 29.0 209.2 8.02 3.00 3.90 5.36 8.54 18.88 134.0 2.00 0.75 0.98 1.34 2.13 4.72 34.0 4.01 1.50 1.95 2.68 4.27 9.44 68.0 16.4 21.4 7.8 10.7 17.0 37.7 272.0 ms

Analog Integrated Circuit Device Data Freescale Semiconductor 17 10XS3412 DYNAMIC ELECTRICAL CHARACTERISTICS Output Over-current Time Step for 28 W bit = 1 OC[1:0]=00 (slow by default) OC[1:0]=01 (fast) OC[1:0]=10 (medium) OC[1:0]=11 (very slow) tOC1_00 tOC2_00 tOC3_00 tOC4_00 tOC5_00 tOC6_00 tOC7_00 tOC1_01 tOC2_01 tOC3_01 tOC4_01 tOC5_01 tOC6_01 tOC7_01 tOC1_10 tOC2_10 tOC3_10 tOC4_10 tOC5_10 tOC6_10 tOC7_10 tOC1_11 tOC2_11 tOC3_11 tOC4_11 tOC5_11 tOC6_11 tOC7_11 3.4 1.1 1.4 2.0 3.4 8.5 62.4 0.86 0.28 0.36 0.51 0.78 2.14 20.2 1.7 0.5 0.7 1.0 1.7 4.2 31.2 6.8 2.2 2.9 4.0 6.8 17.0 124.8 4.9 1.6 2.1 2.9 4.9 12.2 89.2 1.24 0.40 0.52 0.74 1.12 3.06 22.2 2.5 0.8 1.0 1.5 2.5 6.1 44.6 9.8 3.2 4.2 5.8 9.8 24.4 178.4 6.4 2.1 2.8 3.8 6.4 15.9 116.0 1.61 0.52 0.68 0.96 1.46 3.98 28.9 3.3 1.0 1.3 2.0 3.3 6.0 58.0 12.8 16.7 5.5 7.6 12.8 31.8 232.0 ms

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DYNAMIC ELECTRICAL CHARACTERISTICS Bulb Cooling Time Step for 28 W bit = 0 CB[1:0]=00 or 11 (medium) CB[1:0]=01 (fast) CB[1:0]=10 (slow) for 28 W bit = 1 CB[1:0]=00 or 11 (medium) CB[1:0]=01 (fast) CB[1:0]=10 (slow) tBC1_00 tBC2_00 tBC3_00 tBC4_00 tBC5_00 tBC6_00 tBC1_01 tBC2_01 tBC3_01 tBC4_01 tBC5_01 tBC6_01 tBC1_10 tBC2_10 tBC3_10 tBC4_10 tBC5_10 tBC6_10 tBC1_00 tBC2_00 tBC3_00 tBC4_00 tBC5_00 tBC6_00 tBC1_01 tBC2_01 tBC3_01 tBC4_01 tBC5_01 tBC6_01 tBC1_10 tBC2_10 tBC3_10 tBC4_10 tBC5_10 tBC6_10 242 126 140 158 181 211 121 105 484 252 280 316 362 422 291 156 178 208 251 314 146 101 126 226 583 312 357 417 501 628 347 181 200 226 259 302 173 100 113 129 151 694 362 400 452 518 604 417 224 255 298 359 449 209 112 127 145 180 324 834 448 510 596 717 898 452 236 260 294 337 393 226 118 130 147 169 197 1904 472 520 588 674 786 542 292 332 388 467 584 272 146 166 189 234 422 1085 582 665 775 933 1170 ms

Analog Integrated Circuit Device Data Freescale Semiconductor 19 10XS3412 DYNAMIC ELECTRICAL CHARACTERISTICS PWM MODULE TIMING Input PWM Clock Range on IN0 fIN0 7.68 – 51.2 kHz Input PWM Clock Low Frequency Detection Range on IN0(32) fIN0(LOW) 1.0 2.0 4.0 kHz Input PWM Clock High Frequency Detection Range on IN0(32) fIN0(HIGH) 100 200 400 kHz Output PWM Frequency Range fPWM – – 1.0 kHz Output PWM Frequency Accuracy using Calibrated Oscillator AFPWM(CAL) -10 – +10 % Default Output PWM Frequency using Internal Oscillator fPWM(0) 84 120 156 Hz CS Calibration Low Minimum Time Detection Range t CSB(MIN) 14 20 26 μs CS Calibration Low Maximum Tine Detection Range t CSB(MAX) 140 200 260 μs Output PWM Duty-Cycle Range for fpwm = 1.0 kHz for High Speed Slew Rate(33) RPWM_1k 6.0 – 94 % Output PWM Duty-Cycle Range for fpwm = 400 Hz(33) RPWM_400 10 98 % Output PWM Duty-Cycle Range for fpwm = 200 Hz (33) RPWM_200 5.0 98 % INPUT TIMING Direct Input Toggle Timeout tIN 175 250 325 ms AUTORETRY TIMING Autoretry Period tAUTO 105 150 195 ms TEMPERATURE ON THE GND FLAG Thermal Prewarning Detection(34) TOTWAR 110 125 140 °C Analog Temperature Feedback at TA = 25°C with RCSNS=2.5 kΩ TFEED 1.15 1.20 1.25 V Analog Temperature Feedback Derating with RCSNS=2.5 kΩ(35) DTFEED -3.5 -3.7 -3.9 mV/°C Notes 32. Clock Fail detector available fo r PWM_en bit is set to logic [1] and CLOCK_sel is set to logic [0]. 33. The PWM ratio is measured at V HS = 50% of VPWR and for the default SR value. It is possible to put the device fully-on (PWM duty-cycle 100%) and fully-off (duty-cycle 0%). For values outside this range, a calibration is needed between the PWM duty-cycle programming and the PWM on the output with RL = 5.0 Ω resistive load. 34. Typical value guaranteed per design. 35. Value guaranteed per statistical analysis.

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DYNAMIC ELECTRICAL CHARACTERISTICS SPI INTERFACE CHARACTERISTICS(36) Maximum Frequency of SPI Operation f SPI – – 8.0 MHz Required Low State Duration for RST(37) t WRST 10 – – μs Rising Edge of CS to Falling Edge of CS (Required Setup Time)(38) t CS – – 1.0 μs Rising Edge of RST to Falling Edge of CS (Required Setup Time)(38) t ENBL – – 5.0 μs Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)(38) t LEAD – – 500 ns Required High State Duration of SCLK (Required Setup Time)(38) t WSCLKh – – 50 ns Required Low State Duration of SCLK (Required Setup Time)(38) t WSCLKl – – 50 ns Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)(38) t LAG – – 60 ns SI to Falling Edge of SCLK (Required Setup Time)(39) t SI (SU) – – 37 ns Falling Edge of SCLK to SI (Required Setup Time)(39) t SI (HOLD) – – 49 ns SO Rise Time CL = 80 pF t RSO – – 13 ns SO Fall Time CL = 80 pF t FSO – – 13 ns SI, CS, SCLK, Incoming Signal Rise Time(39) t RSI – – 13 ns SI, CS, SCLK, Incoming Signal Fall Time(39) t FSI – – 13 ns Time from Rising Edge of SCLK to SO Low-impedance(40) t SO(EN) – – 60 ns Time from Rising Edge of SCLK to SO High-impedance(41) t SO(DIS) – – 60 ns Notes 36. Parameters guaranteed by design. 37. RST low duration measured with outputs enabled and going to OFF or disabled condition. 38. Maximum setup time required for the 10XS3412 is the minimum guaranteed time needed from the microcontroller. 39. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. 40. Time required for output status data to be available for use at SO. 1.0 kΩ on pull-up on CS. 41. Time required for output status data to be terminated at SO. 1.0 kΩ on pull-up on CS.

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Figure 6. Bulb Cooling Management Figure 7. Input Timing Switching Characteristics

0.7 VDD

0.2 VDD

Analog Integrated Circuit Device Data Freescale Semiconductor 23 10XS3412 Figure 8. SCLK Waveform and Valid SO Data Delay Time

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The 10XS3412 is one in a family of devices designed for low-voltage automotive lighting applications. Its four low RDS(ON) MOSFETs (dual 10 mΩ, dual 12 mΩ) can control four separate 55 W / 28 W bulbs and/or Xenon modules. Programming, control and diagnostics are accomplished using a 16-bit SPI interface. Its output with selectable slew- rate improves electromagnetic compatibility (EMC) behavior. Additionally, each output has its own parallel input or SPI control for pulse-width modulation (PWM) control if desired. The 10XS3412 allows the user to program via the SPI the fault current trip levels and duration of acceptable lamp inrush. The device has fail-safe mode to provide fail-safe functionality of the outputs in case of MCU damaged. FUNCTIONAL PIN DESCRIPTION OUTPUT CURRENT MONITORING (CSNS) The Current Sense pin provides a current proportional to the designated HS0 : HS3 output or a voltage proportional to the temperature on the GND flag. That current is fed into a ground-referenced resistor (4.7 kΩ typical) and its voltage is monitored by an MCU's A/D. The output type is selected via the SPI. This pin can be tri-stated through SPI. DIRECT INPUTS (IN0, IN1, IN2, IN3) Each IN input wakes the device. The IN0 : IN3 high side input pins are also used to directly control HS0 : HS3 high side output pins. In case of the outputs are controlled by PWM module, the external PWM clock is applied to IN0 pin. These pins are to be driven with CMOS levels, and they have a passive internal pull-down, R DWN. FAULT STATUS (FS) This pin is an open drain configured output requiring an external pull-up resistor to VDD for fault reporting. If a device fault condition is detected, this pin is active LOW. Specific device diagnostics and faults are reported via the SPI SO pin. WAKE The wake input wakes the device. An internal clamp protects this pin from high damaging voltages with a series resistor (10 kΩ typ). This input has a passive internal pull- down, RDWN. RESET (RST) The reset input wakes the device. This is used to initialize the device configuration and fault registers, as well as place the device in a low-current Sleep Mode. The pin also starts the watchdog timer when transitioning from logic [0] to logic [1]. This pin has a passive internal pull-down, RDWN. CHIP SELECT (CS) The CS pin enables communication with the master microcontroller (MCU). When this pin is in a logic [0] state, the device is capable of transferring information to, and receiving information from, the MCU. The 10XS3412 latches in data from the Input Shift registers to the addressed registers on the rising edge of CS. The device transfers status information from the power output to the Shift register on the falling edge of CS. The SO output driver is enabled when CS is logic [0]. CS should transition from a logic [1] to a logic [0] state only when SCLK is a logic [0]. CS has an active internal pull-up from VDD, IUP. SERIAL CLOCK (SCLK) The SCLK pin clocks the internal shift registers of the 10XS3412 device. The serial input (SI) pin accepts data into the input shift register on the falling edge of the SCLK signal while the serial output (SO) pin shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important the SCLK pin be in a logic low state whenever CS makes any transition. For this reason, it is recommended the SCLK pin be in a logic [0] whenever the device is not accessed (CS logic [1] state). SCLK has an active internal pull-down. When CS is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high-impedance) (see Figure 9, page 27). SCLK input has an active internal pull- down, IDWN. SERIAL INPUT (SI) This is a serial interface (SI) command data input pin. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of serial data is required on the SI pin, starting with D15 (MSB) to D0 (LSB). The internal registers of the 10XS3412 are configured and controlled using a 5-bit addressing scheme described in Table 10, page 35. Register addressing and configuration are described in Table 11, page 36. SI input has an active internal pull-down, IDWN. DIGITAL DRAIN VOLTAGE (VDD) This pin is an external voltage input pin used to supply power to the SPI circuit. In the event VDD is lost (VDD Failure), the device goes to Fail-safe Mode.

Analog Integrated Circuit Device Data Freescale Semiconductor 25 10XS3412 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION GROUND (GND) These pins are the ground for the device. POSITIVE POWER SUPPLY (VPWR) This pin connects to the positive power supply and is the source of operational power for the device. The VPWR contact is the backside surface mount tab of the package. SERIAL OUTPUT (SO) The SO data pin is a tri-stateable output from the shift register. The SO pin remains in a high-impedance state until the CS pin is put into a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, the state of the key inputs, etc. The SO pin changes state on the rising edge of SCLK and reads out on the falling edge of SCLK. SO reporting descriptions are provided in Table 23, page 40. HIGH SIDE OUTPUTS (HS3, HS1, HS0, HS2) Protected 10 mΩ and 12 mΩ high side power outputs to the load. FAIL-SAFE INPUT (FSI) This pin incorporates an active internal pull-up current source from internal supply (VREG). This enables the watchdog timeout feature. When the FSI pin is opened, the watchdog circuit is enabled. After a Watchdog timeout occurs, the output states depends on IN[0:3]. When the FSI pin is connected to GND, the watchdog circuit is disabled. The output states depends on IN[0:3] in case of VDD Failure condition, in case VDD failure detection is activated (VDD_FAIL_en bit sets to logic [1]).

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26 Freescale Semiconductor

FUNCTIONAL INTERNAL BLOCK DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION POWER SUPPLY The 10XS3412B is designed to operate from 4.0 V to 28 V on the VPWR pin. Characteristics are provided from 6.0 V to 20 V for the device. The VPWR pin supplies power to internal regulator, analog, and logic circuit blocks. The VDD supply is used for Serial Peripheral Interface (SPI) communication in order to configure and diagnose the device. This IC architecture provides a low quiescent current Sleep Mode. Applying V PWR and VDD to the device will place the device in the Normal Mode. The device will transit to Fail-safe Mode in case of failures on the SPI or/and on VDD voltage. HIGH SIDE SWITCHES: HS0 – HS3 These pins are the high side outputs controlling automotive lamps located for the front of vehicle, such as 65 W/55 W bulbs and Xenon-HID modules. Those N-channel MOSFETs with 10 mΩ & 12 mΩ RDS(ON) are self-protected and present extended diagnostics in order to detect bulb outage and short-circuit fault condition. The HS output is actively clamped during turn off of inductive loads and inductive battery line. When driving DC motor or Solenoid loads demanding multiple switching, an external recirculation device must be used to maintain the device in its Safe Operating Area. MCU INTERFACE AND OUTPUT CONTROL In Normal Mode, each bulb is controlled directly from the MCU through SPI. A pulse width modulation control module allows improvement of lamp lifetime with bulb power regulation (PWM frequency range from 100 to 400 Hz) and addressing the dimming application (day running light). An analog feedback output provides a current proportional to the load current or the temperature of the board. The SPI is used to configure and to read the diagnostic status (faults) of high side outputs. The reported fault conditions are: open load, short circuit to battery, short circuit to ground (over-current and severe short-circuit), thermal shutdown, and under/over- voltage. Thanks to accurate and configurable over-current detection circuitry and wire-harness optimization, the vehicle is lighter. In Fail-safe Mode, each lamp is controlled with dedicated parallel input pins. The device is configured in default mode. MC10XS3412 - Functional Block Diagram Power Supply MCU Interface and Output Control Self-protected High Side Switches HS0 - HS3 Power Supply MCU Interface and Output Control Parallel Control Inputs Self-protected High Side Switches SPI Interface PWM Controller

compatible with 5.0 or 3.3 V CMOS logic levels. Figure 9. Single 16-Bit Word SPI Communication

1. RSTB is in a logic H state during the above operation.
2. DO, D1, D2, ... , and D15 relate to the most recent ordered entry of program data into the LUX IC
3. RST is a logic [1] state during the above operation.
4. D15:D0 relate to the most recent ordered entry of data into the device.
5. OD15:OD0 relate to the first 16 bits of ordered fault and status data out of the device.

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contained in succeeding paragraphs. Figure 10. IN_ON[x] internal signal

• wake-up = RST or WAKE or IN_ON[0] or IN_ON[1] or IN_ON[2] or IN_ON[3],
• fail = (V DD Failure and VDD_FAIL_en) or (Watchdog timeout and FSI input not shorted to ground),
• fault = OC[0:3] or OT[0:3] or SC[0:3] or UV or (OV and OV_dis).

Figure 11. Operating Modes Table 6. 10XS3412 Operating Modes

• V PWR and VDD are within the normal voltage range,
• wake-up = 0,
• fail = X,
• f a u l t = X . This is the Default Mode of the device after first applying battery voltage (VPWR) prior to any I/O transitions. This is also the state of the device when the WAKE and RST and IN_ON[0:3] are logic [0]. In the Sleep Mode, the output and all unused internal circuitry, such as the internal regulator, are off to minimize draw current. In addition, all SPI-configurable features of the device are as if set to logic [0]. NORMAL MODE The 10XS3412 is in Normal Mode when:
• V PWR and VDD are within the normal voltage range,
• wake-up = 1,
• fail = 0,
• f a u l t = 0 . In this mode, the NM bit is set to lfault_contrologic [1] and the outputs HS[0:3] are under control, as defined by hson signal: hson[x] = ( ( (IN[x] and DIR_dis[x]) or On bit[x] ) and PWM_en ) or (On bit [x] and Duty_cycle[x] and PWM_en). In this mode and also in Fail-safe, the fault condition reset depends on fault_control signal, as defined below: fault_control[x] = ( (IN_ON[x] and DIR_dis[x]) and PWM_en ) or (On bit [x]). Programmable PWM module The outputs HS[0:3] are controlled by the programmable PWM module if PWM_en and On bits are set to logic [1]. The clock frequency from IN0 input pin or from internal clock is the factor 27 (128) of the output PWM frequency (CLOCK_sel bit). The outputs HS[0:3] can be controlled in the range of 5% to 98% with a resolution of 7 bits of duty cycle (Table 7). The state of other IN pin is ignored. The timing includes seven programmable PWM switching delay (number of PWM clock rising edges) to improve overall EMC behavior of the light module (Table 8). The clock frequency from IN0 is permanently monitored in order to report a clock failure in case of the frequency is out a specified frequency range (from fIN0(LOW) to fIN0(HIGH)). In case of clock failure, no PWM feature is provided, the On bit defines the outputs state and the CLOCK_fail bit reports [1]. Calibratable internal clock The internal clock can vary as much as +/-30 percent corresponding to typical fPWM(0) output switching period. Using the existing SPI inputs and the precision timing reference already available to the MCU, the 10XS3412 allows clock period setting within +/-10 percent of accuracy. Calibrating the internal clock is initiated by defined word to CALR register. The calibration pulse is provided by the MCU. The pulse is sent on the CS pin after the SPI word is launched. At the moment, the CS pin transitions from logic [1] to [0] until from logic [0] to [1] determine the period of internal clock with a multiplicative factor of 128. In case of negative CS pulse is outside a predefined time range (from t CSB(MIN) to t CSB(MAX)), the calibration event will be ignored and the internal clock will be unaltered or reset to default value (fPWM(0)) if this was not calibrated before.

Table 7. Output PWM Resolution

0 X OFF

Table 8. Output PWM Switching Delay

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IN0 input, when CLOCK_sel is set to [1].

• V PWR is within the normal voltage range,
• wake-up = 1,
• fail = 1,
• f a u l t = 0 . Watchdog If the FSI input is not grounded, the watchdog timeout detection is active when either the WAKE or IN_ON[0:3] or RST input pin transitions from logic [0] to logic [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting resistance limiting the internal clamp current according to the specification. The watchdog timeout is a multiple of an internal oscillator. As long as the WD bit (D15) of an incoming SPI message is toggled within the minimum watchdog timeout period (WDTO), the device will operate normally. Fail-Safe conditions If an internal watchdog timeout occurs before the WD bit for FSI open (Table 9) or in case of VDD failure condition (VDD< VDD(FAIL))) for VDD_FAIL_en bit is set to logic [1], the device will revert to a Fail-safe Mode until the WD bit is written to logic [1] (see Fail-safe to Normal Mode transition paragraph) and VDD is within the normal voltage range. During the Fail-safe Mode, the outputs will depend on the corresponding input. The SPI register content is reset to their default value (except POR bit) and fault protections are fully operational. The Fail-safe Mode can be detected by monitoring the NM bit is set to [0]. NORMAL & FAIL-SAFE MODE TRANSITIONS Transition Fail-Safe to Normal mode To leave the Fail-safe Mode, VDD must be in nominal voltage and the microcontroller has to send a SPI command with WDIN bit set to logic [1] ; the other bits are not considered. The previous latched faults are reset by the transition into Normal Mode (autoretry included). Moreover, the device can be brought out of the Fail-safe Mode due to watchdog timeout issue by forcing the FSI pin to logic [0]. Transition Normal to Fail-safe Mode To leave the Normal Mode, a fail-safe condition must occurred (fail=1). The previous latched faults are reset by the transition into Fail-safe Mode (autoretry included). FAULT MODE The 10XS3412 is in Fault Mode when:
• V PWR and VDD are within the normal voltage range
• wake-up = 1
• fail = X
• fault=1 This device indicates the faults below as they occur by driving the FS pin to logic [0] for RST input is pulled up:
• Over-temperature fault
• Over-current fault
• Severe short-circuit fault
• Output(s) shorted to VPWR fault in OFF state
• Open load fault in OFF state
• Over-voltage fault (enabled by default)
• Under-voltage fault The FS pin will automatically return to logic [1] when the fault condition is removed, except for over-current, severe short-circuit, over-temperature and under-voltage which will be reset by a new turn-on command (each fault_control signal to be toggled). Fault information is retained in the SPI fault register and is available (and reset) via the SO pin during the first valid SPI communication. The Open load fault in ON state is only reported through SPI register without effect on the corresponding output state (HS[x]) and the FS pin. START-UP SEQUENCE The 10XS3412 enters in Normal Mode after start-up if following sequence is provided:
• VPWR and VDD power supplies must be above their under-voltage thresholds,
• generate wake-up event (wake-up=1) from 0 to 1 on RST. The device switches to Normal Mode with SPI register content is reset (as defined in Table 11 and Table 23). All features of the 10XS3412 will be available after 50μs typical and all SPI registers are set to default values (set to logic [0]). The UV fault is reported in the SPI status registers. And, in case of the PWM module is used (PWM_en bit is set to logic [1]) with an external reference clock:
• apply PWM clock on IN0 input pin after maximum 200 μs (min. 50 μs). If the correct start-up sequence is not provided, the PWM function is not guaranteed.

Table 9. SPI Watchdog Activation

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FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES The SPI fault report (SC[0:3] bits) is removed after a read operation. Over-voltage Fault (Enabled by default) By default, the over-voltage protection is enabled. The 10XS3412 shuts down all outputs and FS will go to logic [0] during an over-voltage fault condition on the VPWR pin (VPWR > VPWR(OV)). The outputs remain in the OFF state until the over-voltage condition is removed (VPWR < VPWR(OV) - VPWR(OVHYS)). When experiencing this fault, the OVF fault bit is set to logic [1] and cleared after either a valid SPI read. The over-voltage protection can be disabled through SPI (OV_dis bit is disabled set to logic [1]). The fault register reflects any over-voltage condition (VPWR > VPWR(OV)). This over-voltage diagnosis, as a warning, is removed after a read operation, if the fault condition disappears. The HS[0:3] outputs are not commanded in RDS(ON) above the OV threshold. In Fail-safe Mode, the over-voltage activation depends on the RST logic state: enable for RST = 1 and disable for RST = 0. The device is still protected with over-temperature protection in case the over-voltage feature is disabled. Under-voltage Fault The output(s) will latch off at some battery voltage below VPWR(UV). As long as the VDD level stays within the normal specified range, the internal logic states within the device will remain (configuration and reporting). In the case where battery voltage drops below the under- voltage threshold (VPWR < VPWR(UV)), the outputs will turn off, FS will go to logic [0], and the fault register UV bit will be set to [1]. Two cases need to be considered when the battery level recovers (VPWR > VPWR(UV)_UP):

• If outputs command are low, FS will go to logic [1] but the UV bit will remain set to 1 until the next read operation (warning report).
• If the output command is ON, FS will remain at logic [0]. To delatch the fault and be able to turn ON again the outputs, the failure condition must disappear and the autoretry circuitry must be active or the corresponding output must be commanded OFF and then ON (toggling fault_control signal of corresponding output) or VSUPPLY(POR) condition if VDD = 0. In extended mode, the output is protected by over- temperature shutdown circuitry. All previous latched faults, occurred when VPWR was within the normal voltage range, are guaranteed if VDD is within the operational voltage range or until VSUPPLY(POR) if VDD = 0. Any new OT fault is detected (VDD failure included) and reported through SPI above VPWR(UV). The output state is not changed as long as the VPWR voltage does not drop any lower than 3.5 V typical. All latched faults (over-temperature, over-current, severe short-circuit, over and under-voltage) are reset if:
• V DD < VDD(FAIL) with VPWR in nominal voltage range,
• VDD and VPWR supplies is below VSUPPLY(POR) voltage value.

Figure 12. Auto-retry State Machine retry[x] = OC[x] or OT[x] or UV. The Figure 12 describes the auto-retry state machine. disabled through SPI (OS_DIS[0:3] bit). output. The OL_OFF[0:3] fault bit is set in the status register. the status register will be cleared after reading the register. through SPI (OLOFF_DIS[0:3] bit).

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FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES Open-load Detection In On State The ON output open-load current thresholds can be chosen by SPI to detect a standard bulbs or LEDs (OLLED[0:3] bit set to logic [1]). In the cases where load current drops below the defined current threshold, OLON bit is set to logic [1], and the output stays ON and FS will not be disturbed. Open-load Detection In On State For Led Open load for LEDs only (OLLED[0:3] set to logic [1]) is detected periodically each t OLLED (fully-on, D[6:0]=7F). To detect OLLED in fully-on state, the output must be ON at least t OLLED. To delatch the diagnosis, the condition should be removed and SPI read operation is needed (OL_ON[0:3] bit). The ON output open-load protection can be disabled through SPI (OLON_DIS[0:3] bit). Analog Current Recopy and Temperature Feedbacks The CSNS pin is an analog output reporting a current proportional to the designed output current or a voltage proportional to the temperature of the GND flag (pin #14). The routing is SPI programmable (TEMP_en, CSNS_en, CSNS_s[1,0] and CSNS_ratio_s bits). In case the current recopy is active, the CSNS output delivers current only during ON time of the output switch without overshoot. The maximum current is 2.0 mA typical. The typical value of external CSNS resistor connected to the ground is 4.7 kΩ. The current recopy is not active in Fail-safe Mode. Temperature Prewarning Detection In Normal Mode, the 10XS3412 provides a temperature prewarning reported via SPI in case of the temperature of the GND flag is higher than TOTWAR. This diagnosis (OTW bit set to [1]) is latched in the SPI DIAGR0 register. To delatch, a read SPI command is needed. ACTIVE CLAMP ON VPWR The device provides an active gate clamp circuit in order to limit the maximum transient VPWR voltage at VPWR(CLAMP). In case of overload on an output the corresponding output is turned off which leads to a high- voltage at VPWR with an inductive VPWR line. When VPWR voltage exceeds VPWR (CLAMP) threshold, the turn-off on the corresponding output is deactivated and all HS[0:3] outputs are switched ON automatically to demagnetize the inductive Battery line. For a long battery line between the battery and the device (> 20 meters), the smart high side switch output may exceed the energy capability in case of a short-circuit. It is recommended to implement a voltage transient suppressor to drain the battery line energy. REVERSE BATTERY ON VPWR The output survives the application of reverse voltage as low as -18 V. Under these conditions, the ON resistance of the output is 2 times higher than typical ohmic value in forward mode. No additional passive components are required except on VDD current path. GROUND DISCONNECT PROTECTION In the event the 10XS3412 ground is disconnected from load ground, the device protects itself and safely turns OFF the output regardless of the state of the output at the time of disconnection (maximum VPWR=16 V). A 10 kΩ resistor needs to be added between the MCU and each digital input pin in order to ensure that the device turns off in case of ground disconnect and to prevent this pin from exceeding maximum ratings. LOSS OF SUPPLY LINES Loss of VDD If the external VDD supply is disconnected (or not within specification: VDD<VDD(FAIL)) with VDD_FAIL_en bit is set to logic [1]), all SPI register content is reset. The outputs can still be driven by the direct inputs IN[0 : 3] if VPWR is within specified voltage range. The 10XS3412 uses the battery input to power the output MOSFET-related current sense circuitry and any other internal logic providing Fail-safe device operation with no VDD supplied. In this state, the over-temperature, over-current, severe short-circuit, short to VPWR and OFF open-load circuitry are fully operational with default values corresponding to all SPI bits are set to logic [0]. No current is conducted from VPWR to VDD. Loss of VPWR If the external VPWR supply is disconnected (or not within specification), the SPI configuration, reporting, and daisy chain features are provided for RST is set to logic [1] under VDD in nominal conditions. The SPI pull-up and pull-down current sources are not operational. This fault condition can be diagnosed with UV fault in the SPI STATR_s registers. The previous device configuration is maintained. No current is conducted from VDD to VPWR. Loss of VPWR and VDD If the external VPWR and VDD supplies are disconnected (or not within specification: (VDD and VPWR) < VSUPPLY(POR)), all SPI register contents are reset with default values corresponding to all SPI bits are set to logic [0] and all latched faults are also reset. EMC PERFORMANCES All following tests are performed on Freescale evaluation board in accordance with the typical application schematic.

transients on the VPWR line (per ISO 7637-2). injection level for immunity tests. with the MSB D15 and ending with the LSB, D0 (Table 10). the outputs and their protection features. latch in a message that is not 16 bits will be ignored. configure the device and to control the state of the outputs. Table 11 summarizes the SI registers. Table 10. SI Message Bit Assignment MSB D15 Watchdog in: toggled to satisfy watchdog requirements. D14 : D13 Register address bits used in some cases for output selection (Table 12). D12 : D10 Register address bits. D9 Not used (set to logic [0]). LSB D8:D0 Used to configure the inputs, outputs, and the device protection features and SO status content.

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addresses (D[14:10]) and their impact on device operation. of the D14 : D13 bits (Table 12). state of the D14 : D13 bits (Table 12). Table 11. Serial Input Address and Configuration Bit Map

4 D13 D1

0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

s = Output selection with the bits A1A0 as defined in Table 12. Table 12. Output Selection

output is only controlled by On bit). PWM_en bit is set to logic [1]). corresponding output fault management through the SPI. based on the state of the D14 : D13 bits (Table 12). default value [0] corresponds to enable this feature. [0] corresponds to enable this feature (Table 14). default value [0] corresponds to enable this feature. detection is set for bulbs (Table 14). value [0] is the low ratio (Table 15). current profile, as described Figure 13. Table 13. Slew Rate Speed Selection Table 14. ON Open-load Selection

1 X disable

Table 15. Current Sense Ratio Selection

0 CRS0 (default)

1 CRS1

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Figure 13. Over-current profile depending on Xenon bit shown Table 16 and Table 17. replaced by OCHI2 during tOC1, as shown Figure 14. Figure 14. Over-current profile with OCHI bit set to ‘1’ current levels in steady state, as defined in Table 18. Table 16. Cooling Curve Selection Table 17. Inrush Curve Selection Table 18. Output Steady State Selection

mode, as described Table 19. to Fail-safe Mode for VDD < VDD(FAIL). feedback on CSNS output pin, as shown in Table 21. clock, as explained in Figure 12. well as message verification. accept new fault status information. STATR write until changed with an updated STATR write.

• The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid SPI communication never occurred.
• The VPWR voltage is below 4.0 V, the status must be ignored by the MCU.

Table 19. Over-current Mode Selection Table 20. PWM Module Selection

0 X PWM module disabled

Table 21. CSNS Reporting Selection Table 22. Output Current Recopy Selection

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• Bit OD15 is the MSB; it reflects the state of the Watchdog bit from the previously clocked-in message.
• Bits OD14:OD10 reflect the state of the bits SOA4 : SOA0 from the previously clocked in message.
• Bit OD9 is set to logic [1] in Normal Mode (NM).
• The contents of bits OD8 : OD0 depend on bits D4 : D0 from the most recent STATR command SOA4 : SOA0 as explained in the paragraphs following Table 23. PREVIOUS ADDRESS SOA4 : SOA0 = A1A0000 (STATR_S) The returned data OD8 reports logic [1] in case of previous Power ON Reset condition (VSUPPLY(POR)). This bit is only reset by a read operation. Bits OD7: OD0 reflect the current state of the Fault register (FLTR) corresponding to the output previously selected with the bits SOA4:SOA3 = A1A0 (Table 23).
• OC_s: over-current fault detection for a selected output,
• SC_s: severe short-circuit f ault detection for a selected output,
• OS_s: output shorted to VPWR fault detection for a selected output,
• OLOFF_s: openload in OFF state fault detection for a selected output,
• OLON_s: openload in ON state fault detection (depending on current level threshold: bulb or LED) for a selected output,
• OV: over-voltage fault detection,
• UV: under-voltage fault detection
• POR: power on reset detection. The FS pin reports all faults. For latched faults, this pin is reset by a new Switch OFF command (toggling fault_control signal). PREVIOUS ADDRESS SOA4 : SOA0 = A1A0001 (PWMR_S) The returned data contains the programmed values in the PWMR register for the output selected with A1A0.

Table 23. Serial Output Bit Map Description

10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0

CONFR0 register for the output selected with A1A0. CONFR1 register for the output selected with A1A0. OCR register for the output selected with A1A0. clock on IN0 pin is out of specified frequency range. of the direct input IN[3:0]. explained in the following Table 24.

• HS output is commanded by corresponding IN input or On bit through SPI. The medium slew rate is used,
• HS output is fully protected by the Xenon over-current profile by default, the severe short-circuit protection, the under-voltage and the over-temperature protection. The auto-retry feature is enabled,
• Open-load in ON and OFF state and HS shorted to VPWR detections are available,
• No current recopy and no analog temperature feedback active,
• Over-voltage protection is enabled,
• SO reporting fault status from HS0,
• VDD failure detection is disabled.

Table 24. Watchdog Activation Report

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The following figure shows a typical automotive lighting application (only one vehicle corner) using an external PWM clock from the main MCU. A redundancy circuitry has been implemented to substitute light control (from MCU to watchdog) in case of a Fail-safe condition. It is recommended to locate a 22 nF decoupling capacitor to the module connector. 10XS3412 VDD VDD VPWR GND MCU Voltage regulator VPWR HS2 HS0 HS1 HS3 VPWRVDD WAKE FS IN0 IN2 IN3 SCLK CS SI SO FSI RST IN1 100nF I/O I/O SCLK CS SI SO 10k 10k 10k 10k 10k 4.7k 10k LOAD 0 LOAD 1 CSNSA/D VDD VDD VPWRVDD 22nF 22nF LOAD 2 22nF LOAD 3 22nF 22nF 10k Watchdog direct light commands (pedal, comodo,...) VPWR ignition switch 100nF 10µF100nF10µF100nF 100nF 10k10k 10k 10k

Analog Integrated Circuit Device Data Freescale Semiconductor 43 10XS3412 PACKAGING SOLDERING INFORMATION PACKAGING SOLDERING INFORMATION The 10XS3412 is packaged in a surface mount power package intended to be soldered directly on the printed circuit board. The CPNA code was qualified in accordance with JEDEC standards J-STD-020C Sn-Pb reflow profile. The maximum peak temperature during the soldering process should not exceed 245 for 10 seconds maximum duration. The DPNA code was qualified in accordance with JEDEC standards J-STD-020C Pb-free reflow profile. The maximum peak temperature during the soldering process should not exceed 260 for 40 seconds maximum duration. The AN2469 provides guidelines for Printed Circuit Board design and assembly.

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For the most current package revision, visit www.freescale.com and perform a keyword search using the 98ARL10596D listed below. PNA SUFFIX 24-PIN PQFN NONLEADED PACKAGE 98ARL10596D ISSUE D

Analog Integrated Circuit Device Data Freescale Semiconductor 45 10XS3412 PACKAGING PACKAGE DIMENSIONS PNA SUFFIX 24-PIN PQFN NONLEADED PACKAGE 98ARL10596D ISSUE D

46 Freescale Semiconductor

Figure 15. Package Mechanical Outline

Analog Integrated Circuit Device Data Freescale Semiconductor 47 10XS3412 PACKAGING PACKAGE DIMENSIONS Package Mechanical Outline PNA SUFFIX 24-PIN PQFN NONLEADED PACKAGE 98ARL10596D ISSUE D

48 Freescale Semiconductor

temperatures, TJ1 and TJ2, and a thermal resistance matrix with RθJAmn. reference temperature while only heat source 1 is heating with P1. to RθJ21 and RθJ22, respectively. Figure 16. Detail of Copper Traces Under Device with Table 25. Thermal Performance Comparison

1. Per JEDEC JESD51-2 at natural convection, still air
2. 2s2p thermal test board per JEDEC JESD51-7and
3. Per JEDEC JESD51-8, with the board temperature on the

center trace near the power outputs.

1. Single layer thermal test board per JEDEC JESD51-3 and
2. Thermal resistance between the die junction and the

exposed pad, “infinite” heat sink attached to exposed pad.

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where the junction temperature is sensed. Figure 20. Steady State Thermal Resistance in Dependance on Heat Streading Area; Table 26. Thermal Resistance Performance

Analog Integrated Circuit Device Data

52 Freescale Semiconductor

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 7.0 10/2008 • Initial release 8.0 10/2008 • Revised wording of VPWR Supply Voltage Range in Maximum Rating Table on page 5.

• Changed Maximum rating for Output Source-to-Drain ON Resistance in Static Electrical Characteristics Table on page 8. 9.0 7/2009 • Added MC10XS3412DPNA part number. The “D” ve rsion has different soldering limits. 10.0 10/2009 • Corrected minor formatting
• Separated definitions for the 10XS3412C and 10XS 3412D in the Static and Dynamic Tables and created a Device Variation Table on page 2.

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