10TPC68M

TPS70445PWPR TI | Alldatasheet

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NC□=□No□internal□connection GND/HEATSINK GND/HEATSINK NC NC PG2 PG1 VSENSE1/FB1 PWP□PACKAGE (TOP□VIEW) 1.8 V VIN1 VIN2 EN1 EN2 VOUT1 VSENSE1 PG1 MR RESET PG2 VSENSE2 VOUT2 TPS70451□PWP 5□V 3.3□V I/O PG2 Core 0.22 /c109F RESET 22 /c109F 47 /c109F 0.22 /c109F MR PG1 EN1 250□k/c87 >2□V <0.7□V 250□k/c87 >2□V <0.7□V >2□V <0.7□V EN2 250□k/c87 TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 www.ti.com SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 DUAL-OUTPUT,LOW DROPOUTVOLTAGEREGULATORS WITHINTEGRATEDSVSFORSPLITVOLTAGESYSTEMS Check forSamples: TPS70445 ,TPS70448 ,TPS70451 ,TPS70458 ,TPS70402 1FEATURES DESCRIPTION 23• Dual Output VoltagesforSplit-Supply The TPS704xx family of devices consists of Applications dual-output,low-dropoutvoltage regulatorswith integratedSVS (RESET, POR, or power on reset)• IndependentEnable Functions(See Part and power good (PG) functions.These devicesareNumber TPS703xx forSequenced Outputs) capableofsupplying1 A and 2 A by regulator1 and• Output CurrentRange of1 A on Regulator1 regulator2 respectively.Quiescentcurrentistypicallyand 2 A on Regulator2 185 mA at fullload.Differentiatedfeatures,such as

FastTransientResponse accuracy,fasttransientresponse,SVS supervisory
Open DrainPower-On Reset with120-ms Delay
Open DrainPower Good forRegulator1 and Regulator2
Ultralow185mA (typ)QuiescentCurrent
2mA InputCurrentDuring Standby
Low Noise:78mVRMS WithoutBypass Capacitor
Quick Output CapacitorDischargeFeature
One Manual Reset Input
2% Accuracy Over Load and Temperature
UndervoltageLockout (UVLO) Feature
24-PinPowerPAD ™ TSSOP Package
Thermal Shutdown Protection Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2PowerPAD isa trademarkofTexas Instruments. 3Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2000–2010,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 www.ti.com The TPS704xx familyofvoltageregulatorsoffersverylow dropoutvoltageand dualoutputs.These deviceshave extremelylow noiseoutputperformancewithoutusingany added filterbypass capacitorsand are designedto have a fasttransientresponseand be stablewith47-mF lowESR capacitors. Regulator1 can supportup to 1 A, and regulator2 can supportup to 2 A. Separatevoltageinputsallowthe designertoconfigurethesourcepower. Because thePMOS devicebehaves as a low-valueresistor,thedropoutvoltageisverylow (typically160 mV on regulator1) and isdirectlyproportionalto the outputcurrent.Additionally,sincethe PMOS pass elementisa voltage-drivendevice,thequiescentcurrentisverylow and independentofoutputloading(maximum of250 mA overthefullrangeofoutputcurrentand fullrangeoftemperature).ThisLDO familyalsofeaturesa sleepmode; applyinga highsignaltoEN1 orEN2 (enable)shutsdown regulator1 orregulator2,respectively.When a high signalisappliedtobothEN1 and EN2, bothregulatorsentersleepmode, therebyreducingtheinputcurrentto2 mA atTJ = +25°C. For each regulator,thereisan internaldischargetransistortodischargetheoutputcapacitorwhen theregulator isturnedoff(disabled). The PG1 pinreportsthe voltageconditionat VOUT1 . The PG1 pincan be used to implementa SVS (RESET, POR, orpower on reset)forthecircuitrysuppliedby regulator1.The PG2 pinreportsthevoltageconditionsat VOUT2 .The PG2 pincan be used toimplementa SVS (poweron reset)forthecircuitrysuppliedby regulator2. The TPS704xx featuresa RESET (SVS, POR, or power on reset).RESET isan activelow,open drainoutput and requiresa pull-upresistorfornormaloperation.When pulledup,RESET goes intoa highimpedance state (thatis,logichigh)aftera 120-ms delaywhen bothofthefollowingconditionsaremet.First,VIN1 must be above theundervoltagecondition.Second, themanual reset(MR) pinmust be ina highimpedance state.To monitor VOUT1 ,thePG1 outputpincan be connectedtoMR. To monitorVOUT2 ,thePG2 outputpincan be connectedto MR. RESET can be used todrivepower on resetora low-batteryindicator.IfRESET isnotused,itcan be left floating. Internalbiasvoltagesare powered by VIN1 and require2.7V forfullfunctionality.Each regulatorinputhas an undervoltagelockoutcircuitthatpreventseach outputfromturningon untiltherespectiveinputreaches2.5V.

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TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 www.ti.com SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications. ORDERING INFORMATION (1) VOLTAGE (V)(2) PACKAGE- SPECIFIED LEAD TEMPERATURE ORDERING TRANSPORT PRODUCT VOUT1 VOUT2 (DESIGNATOR) RANGE (TJ) NUMBER MEDIA, QUANTITY TPS70402PWP Tube,60 TPS70402 Adjustable Adjustable HTSSOP-24 (PWP) –40°C to+125°C TPS70402PWPR Tape and Reel,2000 TPS70445PWP Tube,60 TPS70445 3.3V 1.2V HTSSOP-24 (PWP) –40°C to+125°C TPS70445PWPR Tape and Reel,2000 TPS70448PWP Tube,60 TPS70448 3.3V 1.5V HTSSOP-24 (PWP) –40°C to+125°C TPS70448PWPR Tape and Reel,2000 TPS70451PWP Tube,60 TPS70451 3.3V 1.8V HTSSOP-24 (PWP) –40°C to+125°C TPS70451PWPR Tape and Reel,2000 TPS70458PWP Tube,60 TPS70458 3.3V 2.5V HTSSOP-24 (PWP) –40°C to+125°C TPS70458PWPR Tape and Reel,2000 (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orvisitthe deviceproductfolderatti.com. (2) Forfixed1.20V operation,tieFB toOUT. ABSOLUTE MAXIMUM RATINGS (1) Over operatingfree-airtemperaturerange(unlessotherwisenoted). TPS704xx UNIT Inputvoltagerange:VIN1,VIN2 (2) –0.3to+7 V VoltagerangeatEN1, EN2 –0.3to+7 V Outputvoltagerange(VOUT1 ,VSENSE1 ) 5.5 V Outputvoltagerange(VOUT2 ,VSENSE2 ) 5.5 V Maximum RESET, PG1, PG2 voltage 7 V Maximum MR voltage VIN1 V Peak outputcurrent Internallylimited — Continuoustotalpower dissipation See DissipationRatingsTable — Operatingvirtualjunctiontemperaturerange,TJ –40 to+150 °C Storagetemperaturerange,Tstg –65 to+150 °C ESD rating,HBM 2 kV (1) Stressesbeyond thoselistedunderabsolutemaximum ratingsmay cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunderrecommended operating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) Allvoltagesaretiedtonetworkground. Copyright© 2000–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3

TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 www.ti.com DISSIPATION RATINGS DERATINGPACKAGE AIR FLOW (CFM) TA ≤ +25°C TA = +70°C TA = +85°CFACTOR 0 3.067W 30.67mW/°C 1.687W 1.227W PWP (1) 250 4.115W 41.15mW/°C 2.265W 1.646W (1) Thisparameterismeasured withtherecommended copperheatsinkpatternon a 4-layerPCB, 1 oz.copperon a 4-inby 4-inground layer.Formore information,refertoTItechnicalbriefSLMA002 . RECOMMENDED OPERATING CONDITIONS Over operatingtemperaturerange(unlessotherwisenoted). MIN MAX UNIT Inputvoltage,VI (1)(regulator1 and 2) 2.7 6 V Outputcurrent,IO (regulator1) 0 1 A Outputcurrent,IO (regulator2) 0 2 A Outputvoltagerange(foradjustableoption) 1.22 5.5 V Operatingvirtualjunctiontemperature,TJ –40 +125 °C (1) To calculatetheminimum inputvoltageformaximum outputcurrent,use thefollowingequation:VI(min)= VO(max) + VDO(max load).

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Line□regulation□(mV)□=□(%/V)□x Vo x□1000(V 2.7) 100 /c45Imax 100 /c45Imax oLine□regulation□(mV)□=□(%/V)□x Vo (3) IfVO < 1.8V thenVImax = 6 V,VImin= 2.7V: IfVO > 2.5V thenVImax = 6 V,VImin= VO + 1 V: TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 www.ti.com SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010

ELECTRICAL CHARACTERISTICS

Over recommended operatingjunctiontemperaturerange(TJ = –40°C to+125°C),VIN1 orVIN2 = VOUT(nom) + 1 V,IO = 1 mA, EN = 0 V,C OUT1 = 22 mF,and C OUT2 = 47 mF (unlessotherwisenoted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.7V < VIN < 6 V, FB connectedtoVO 1.22Reference TJ = +25°C voltage 2.7V < VIN < 6 V, FB connectedtoVO 1.196 1.244 2.7V < VIN < 6 V, TJ = +25°C 1.21.2V Output (VOUT2 ) 2.7V < VIN < 6 V, 1.176 1.224 (2) 2.8V < VIN < 6 V, TJ = +25°C 1.81.8V Output (VOUT2 ) 2.8V < VIN < 6 V, 1.764 1.836 3.5V < VIN < 6 V, TJ = +25°C 2.52.5V Output (VOUT2 ) 3.5V < VIN < 6 V, 2.45 2.55 4.3V < VIN < 6 V, TJ = +25°C 3.33.3V Output (VOUT2 ) 4.3V < VIN < 6 V, 3.234 3.366 Quiescentcurrent(GND current)for See (2) TJ = +25°C 185 regulator1 and regulator2,EN1 = EN2 mA See (2) 250= 0 V (1) VO + 1 V < VIN ≤ 6 V, TJ = +25°C (1) 0.01Outputvoltagelineregulation(∆VO /VO ) %Vforregulator1 and regulator2 (3) VO + 1 V < VIN ≤ 6 V (1) 0.1 Load regulationforVOUT 1 and VOUT2 TJ = +25°C 1 mV Outputnoise Regulator1 79 Vn voltage BW = 300 Hz to50 kHz, C O = 33 mF,TJ = +25°C mVRMS Regulator2 77(TPS70451) Regulator1 1.75 2.2 Outputcurrentlimit VOUT = 0 V A Regulator2 3.8 4.5 Thermalshutdownjunctiontemperature +150 °C Regulator1 EN1 = VIN,EN2 = VIN TJ = +25°C 1 2II Standby mA(standby)current Regulator2 EN1 = VIN,EN2 = VIN 10 Power- Regulator1 f= 1 kHz TJ = +25°C (1) 65 supplyripplePSRR dBrejection Regulator2 f= 1 kHz TJ = +25°C (1) 60 (TPS70451) RESET Terminal Minimum inputvoltageforvalidRESET IRESET = 300 mA, V(RESET) ≤ 0.8V 1.0 1.3 V t(RESET) RESET pulseduration 80 120 160 ms Outputlowvoltage VIN = 3.5V, I(RESET) = 1 mA 0.15 0.4 V Leakage current V(RESET) = 6 V 1 mA (1) Minimum inputoperatingvoltageis2.7V orVO(typ)+ 1 V,whicheverisgreater.Maximum inputvoltage= 6 V,minimum output current= 1 mA. (2) IO = 1 mA to1 A forRegulator1 and 1 mA to2 A forRegulator2. Copyright© 2000–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5

TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over recommended operatingjunctiontemperaturerange(TJ = –40°C to+125°C),VIN1 orVIN2 = VOUT(nom) + 1 V, IO = 1 mA, EN = 0 V,C OUT1 = 22 mF,and C OUT2 = 47 mF (unlessotherwisenoted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN1/VIN2 Terminal UVLO threshold 2.4 2.65 V UVLO hysteresis 110 mV PG1/PG2 Terminal Minimum inputvoltageforvalidPGx I(PGx) = 300 mA, V(PGx) ≤ 0.8V 1.0 1.3 V Tripthresholdvoltage VO decreasing 92 95 98 %V OUT Hysteresisvoltage Measured atVO 0.5 %V OUT tr(PGx) Risingedge deglitch 30 ms Outputlowvoltage VIN = 2.7V, I(PGx) = 1 mA 0.15 0.4 V Leakage current V(PGx) = 6V 1 mA EN1/EN2 Terminal High-levelENx inputvoltage 2 V Low-levelENx inputvoltage 0.7 V Inputcurrent(ENx) –1 1 mA MR Terminal High-levelinputvoltage 2 V Low-levelinputvoltage 0.7 V Pull-upcurrentsource 6 mA VOUT1 Terminal IO = 1 A,VIN1 = 3.2V TJ = +25°C 160 Dropoutvoltage(4) mV IO = 1 A,VIN1 = 3.2V 250 Peak outputcurrent 2 ms pulsewidth 1.2 A Dischargetransistorcurrent VOUT1 = 1.5V 7.5 mA VOUT2 Terminal Peak outputcurrent 2 ms pulsewidth 3 A Dischargetransistorcurrent VOUT2 = 1.5V 7.5 mA FB Terminal Inputcurrent:TPS70402 FB = 1.8V 1 mA (4) Inputvoltage(VIN1 orVIN2)= VO(typ)– 100 mV. For1.5-V,1.8-V,and 2.5-Vregulators,thedropoutvoltageislimitedby inputvoltage range.The 3.3-Vregulatorinputissetto3.2V toperformthistest.

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/c45 /c45 Thermal Shutdown 2.5□V +/c45 Current Sense Reference Vref Vref ENA_1 10k/c87 ENA_1 120□ms Delay 0.95□x□Vref VSENSE1 0.95□x□Vref VSENSE2 Rising□Edge Deglitch ENA_1 ENA_2 Current Sense +/c45 ENA_2 ENA_2 FB2Vref VIN1□(2□Pins) GND EN1 EN2 VIN2 (2□Pins) VSENSE1 (see□Note□A) PG1 MR RESET VSENSE2 (see□Note□A) VIN1 PG1 Comp Rising□Edge Deglitch PG2PG2 Comp VOUT1 (2□Pins) VOUT2 (2□Pins) 2.5□V UVLO2 Comp /c45 /c45 10k/c87 TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 www.ti.com SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 DEVICE INFORMATION FixedVoltageVersion A. For most applications,VSENSE1 and VSENSE2 shouldbe externallyconnectedto VOUT1 and VOUT2 , respectively,as closeas possibleto the device.For otherimplementations,referto SENSE terminalconnectiondiscussioninthe ApplicationInformationsection. Copyright© 2000–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7

/c45 /c45 Thermal Shutdown 2.5□V +/c45 Current Sense Reference Vref Vref ENA_1 FB1 ENA_1 120□ms Delay 0.95□x□Vref FB1 0.95□x□Vref FB2 Rising□Edge Deglitch ENA_1 ENA_2 Current Sense +/c45 ENA_2 ENA_2 FB2Vref VIN1□(2□Pins) GND EN1 EN2 VIN2 (2□Pins) FB1 (see□Note□A) PG1 MR RESET FB2 (see□Note□A) VIN1 PG1 Comp Rising□Edge Deglitch PG2PG2 Comp VOUT1 (2□Pins) VOUT2 (2□Pins) 2.5□V UVLO2 Comp /c45 /c45 TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 www.ti.com AdjustableVoltageVersion A. For most applications,FB1 and FB2 shouldbe externallyconnectedtoresistordividersas closeas possibletothe device.For otherimplementations,referto FB terminalsconnectiondiscussionin the ApplicationInformation section.

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t t t MR Input RESET Output 120□ms Delay 120□ms Delay VRES Output Undefined Output Undefined VRES standards□for□semiconductor□symbology. RES RESRESET (see□Note□A) VPG t t t PG1□Output VIT+ (see□Note□B) VIN1 VOUT1 VPG1 V (see□Note□B) VUVLO VUVLO PG1 Threshold Voltage Output Undefined Output Undefined NOTES□A:□V is□the□minimum□input□voltage□for□a□valid□PG.□The□symbol V is□not□currently□listed□within□EIA□or□JEDEC standards□for□semiconductor□symbology. PG1 PG1 V trip□voltage□is□typically□5%□lower□than□the□output□voltage□(95%V ).□V to□V is□the□hysteresis□voltage.IT IT/c45 /c45O IT+NOTES (see□Note□A) IT/c45 TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 www.ti.com SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 RESET Timing Diagram PG1 Timing Diagram Copyright© 2000–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9

t t PG2 Output VIN2 t VIT+ (see□Note□A) VOUT2 V (see□Note□A) Threshold Voltage IT/c45 NOTE□A: V trip□voltage□is□typically□5%□lower□than□the□output□voltage□(95%V ).□V to□V is□the□hysteresis□voltage.IT IT/c45 /c45O IT+ TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 www.ti.com PG2 Timing Diagram (assuming VIN1 alreadypowered up) TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. EN1 6 I ActivelowenableforVOUT1 EN2 7 I ActivelowenableforVOUT2 GND 9 — Ground GND/HEATSI 1,12,13,24 — Ground/heatsinkNK MR 5 I Manual resetinput,activelow,pulledup internally NC 4,17,20 — No connection PG1 19 O Open drainoutput,lowwhen VOUT1 voltageislessthan95% ofthenominalregulatedvoltage PG2 18 O Open drainoutput,lowwhen VOUT2 voltageislessthan95% ofthenominalregulatedvoltage RESET 8 O Open drainoutput,SVS (power-onreset)signal,activelow VIN1 2,3 I Inputvoltageofregulator1 VIN2 10,11 I Inputvoltageofregulator2 VOUT1 22,23 O Outputvoltageofregulator1 VOUT2 14,15 O Outputvoltageofregulator2 VSENSE1 /FB1 21 I Regulator1 outputvoltagesense/regulator1 feedbackforadjustable VSENSE2 /FB2 16 I Regulator2 outputvoltagesense/regulator2 feedbackforadjustable

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TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 www.ti.com SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 DetailedDescription The TPS704xx low dropoutregulatorfamilyprovidesdualregulatedoutputvoltageswithindependentenable functions.These devicesprovidefasttransientresponseand highaccuracywithsmalloutputcapacitors,while drawinglow quiescentcurrent.Other featuresare integratedSVS (power-onreset,RESET) and power good (PG1, PG2) thatmonitoroutputvoltagesand providelogicoutputto the system.These differentiatedfeatures providea completepower solution. The TPS704xx, unlikemany otherLDOs, featuresverylow quiescentcurrentthatremainsvirtuallyconstanteven withvaryingloads.ConventionalLDO regulatorsuse a PNP pass element,thebase currentofwhichisdirectly proportionaltotheloadcurrentthroughtheregulator(IB = IC /b).The TPS704xx uses a PMOS transistortopass current;because thegateofthePMOS isvoltage-driven,operatingcurrentislow and stableoverthefullload range. Pin Functions Enable (EN1, EN2) The EN terminalsareinputsthatenableorshutdown each respectiveregulator.IfEN isata voltagehighsignal, therespectiveregulatorisinshutdownmode. When EN goes tovoltagelow,therespectiveregulatorisenabled. Power-Good (PG1,PG2) The PG terminalsare open drain,activehigh outputterminalsthatindicatethe statusof each respective regulator.When VOUT1 reaches95% ofitsregulatedvoltage,PG1 goes toa highimpedance state.When VOUT2 reaches95% ofitsregulatedvoltage,PG2 goes toa highimpedance state.Each PG goes toa low impedance statewhen itsrespectiveoutputvoltageispulledbelow 95% (thatis,goes to an overloadcondition)of its regulatedvoltage.The open drainoutputsofthePG terminalsrequirea pull-upresistor. Manual Reset Pin MR isan activelow inputterminalused to triggera resetcondition.When MR ispulledto logiclow,a POR (RESET) occurs.The terminalhas a 6-mA pull-upcurrenttoVIN1;however,itisrecommended thatthepinbe pulledhightoVIN1 when itisnotused. Sense (VSENSE1 ,VSENSE2 ) The sense terminalsof fixed-outputoptionsmust be connectedto the regulatoroutputs,and the connection should be as shortas possible.Internally,the sense terminalconnectsto high-impedance,wide-bandwidth amplifiersthrougha resistor-dividernetworkand noisepickupfeedsthroughtotheregulatoroutput.Itisessential toroutethesense connectioninsuch a way as tominimizeoravoidnoisepickup.AddingRC networksbetween sense terminalsand VOUT terminalstofilternoiseisnotrecommended because thesenetworkscan cause the regulatorstooscillate. Copyright© 2000–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11

TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 www.ti.com FB1 and FB2 FB1 and FB2 are inputterminalsused foradjustable-outputdevicesand must be connectedto the external feedbackresistordivider.FB1 and FB2 connectionsshouldbe as shortas possible.Itisessentialtoroutethem in such a way as to minimizeor avoidnoisepickup.Adding RC networksbetween FB terminalsand VOUT terminalstofilternoiseisnotrecommended because thesenetworkscan cause theregulatorstooscillate. RESET Indicator RESET isan activelow,open drainoutputand requiresa pullupresistorfornormaloperation.When pulledup, RESET goes intoa highimpedance state(thatis,logichigh)aftera 120-ms delaywhen bothofthefollowing conditionsare met. First,VIN1 must be above the undervoltagecondition.Second, the manual reset(MR) pin must be ina highimpedance state.To monitorVOUT1 ,thePG1 outputpincan be connectedtoMR. To monitor VOUT2 ,thePG2 outputpincan be connectedtoMR. IfRESET isnotused,itcan be leftfloating. VIN1 and VIN2 VIN1 and VIN2 areinputstoeach regulator.Internalbiasvoltagesarepowered by VIN1. VOUT1 and VOUT2 VOUT1 and VOUT2 areoutputterminalsofeach regulator.

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1.785 1.79 1.795 1.8 1.805 0 500 1000 1500 2000 1.81 1.815 V =□2.8□V T =□25 C V IN2 J OUT2 /c176 I Output□Current mAO /c45 /c45 V Output□Voltage VO /c45 /c45 3.27 3.28 3.29 3.30 3.31 0 200 400 600 800 100 0 3.32 3.33 V =□4.3□V T =□25 C V IN1 J OUT1 /c176 I Output□Current mAO /c45 /c45 V Output□Voltage VO /c45 /c45 TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 www.ti.com SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 TYPICAL CHARACTERISTICS TableofGraphs FIGURE vs Outputcurrent Figure1 and Figure2 VO Outputvoltage vs Junctiontemperature Figure3 toFigure4 Ground current vs Junctiontemperature Figure5 PSRR Power-supplyrejectionratio vs Frequency Figure6 toFigure9 Outputspectralnoisedensity vs Frequency Figure10 toFigure13 ZO Outputimpedance vs Frequency Figure14 toFigure17 vs Temperature Figure18 and Figure19 Dropoutvoltage vs Inputvoltage Figure20 and Figure21 Load transientresponse Figure22 and Figure23 Linetransientresponse(VOUT1 ) Figure24 Linetransientresponse(VOUT2 ) Figure25 VO Outputvoltage vs Time (start-up) Figure26 and Figure27 Equivalentseriesresistance(ESR) vs Outputcurrent Figure29 toFigure32 TPS70451 TPS70451 OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs OUTPUT CURRENT OUTPUT CURRENT Figure1. Figure2. Copyright© 2000–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13

/c45 40 /c45 25 /c45 10 5 20 35 50 65 80 95 110 125 3.234 3.254 3.274 3.294 3.314 3.334 3.354 T Junction□T emperature C/c45 /c45J /c176 IO =□1□mA V V IN1 OUT1 =□4.3□V I =□1□AO V Output□Voltage VO /c45 /c45 1.764 1.774 1.784 1.794 1.804 1.814 1.824 1.834 /c45 40 /c45 25 /c45 10 5 20 35 50 65 80 95 110 125 IO =□1□mA V V IN2 OUT2 =□2.8□V IO =□2□A V Output□Voltage VO /c45 /c45 T Junction□T emperature C/c45 /c45J /c176 150 160 170 180 190 200 /c45 40 /c45 25 /c45 10 5 20 35 50 65 80 95 110 125 210 Regulator□1□and□Regulator□2 Ground□Current A /c45/c32/c109 T Junction□T emperature C/c45 /c45J /c176 I I =□1□mA OUT1 OUT2 =□1□mA I I =□2□A OUT1 OUT2 =□1□A TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) TPS70451 TPS70451 OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE Figure3. Figure4. TPS70451 GROUND CURRENT vs JUNCTION TEMPERATURE Figure5.

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10 100 1□k 10□k 100□k 1 M V =□4.3□V V =□3.3□V I =□1□A C =□22 F IN1 OUT1 O O /c109 PSRR Power□Supply□Rejection□Ratio dB /c45 /c45 f Frequency Hz/c45 /c45 100 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 10 100 1□k 10□k 100□k 1 M V =□4.3□V V =□3.3□V I =□10□mA C =□22 F IN1 OUT1 O O /c109 PSRR Power□Supply□Rejection□Ratio dB /c45 /c45 f Frequency Hz/c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 10 100 1□k 10□k 100□k 1 M V =□2.8□V V =□1.8□V I =□10□mA C =□47 F IN2 OUT2 O O /c109 PSRR Power□Supply□Rejection□Ratio dB /c45 /c45 100 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 f Frequency Hz/c45 /c45 10 100 1□k 10□k 100□k 1 M PSRR Power□Supply□Rejection□Ratio dB /c45 /c45 100 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 f Frequency Hz/c45 /c45 V =□2.8□V V =□1.8□V I =□2□A C =□47 F IN2 OUT2 O O /c109 TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 www.ti.com SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) TPS70451 TPS70451 POWER-SUPPLY REJECTION RATIO POWER-SUPPLY REJECTION RATIO vs vs FREQUENCY FREQUENCY Figure6. Figure7. TPS70451 TPS70451 POWER-SUPPLY REJECTION RATIO POWER-SUPPLY REJECTION RATIO vs vs FREQUENCY FREQUENCY Figure8. Figure9. Copyright© 2000–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15

0.01 0.1 100 1□k 10□k 100□k f Frequency Hz/c45 /c45 V =□4.3□V V =□3.3□V C =□22 F I =□10□mA T =□25 C IN1 OUT1 OUT1 O J /c109 /c176 Output□Spectral□Noise□Density /c45/c32/c109 Hz/c214 0.01 0.1 100 1□k 10□k 100□k V =□2.8□V V =□1.8□V C =□47 F I =□10□mA T =□25 C IN2 OUT2 OUT2 O J /c109 /c176 f Frequency Hz/c45 /c45 Output□Spectral□Noise□Density /c45/c32/c109 Hz/c214 0.01 0.1 100 1□k 10□k 100□k V =□2.8□V V =□1.8□V C =□47 F I =□2□A T =□25 C IN2 OUT2 OUT2 O J /c109 /c176 f Frequency Hz/c45 /c45 Output□Spectral□Noise□Density /c45/c32/c109 Hz/c214 0.01 0.1 100 1□k 10□k 100□k V =□4.3□V V =□3.3□V C =□22 F I =□1□mA T =□25 C IN1 OUT1 OUT1 O J /c109 /c176 f Frequency Hz/c45 /c45 Output□Spectral□Noise□Density /c45/c32/c109 Hz/c214 TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT SPECTRAL NOISE DENSITY OUTPUT SPECTRAL NOISE DENSITY vs vs FREQUENCY FREQUENCY Figure10. Figure11. OUTPUT SPECTRAL NOISE DENSITY OUTPUT SPECTRAL NOISE DENSITY vs vs FREQUENCY FREQUENCY Figure12. Figure13.

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0.1 0.01 10 100 1□k 10□k 100□k 1 M 10 M V =□3.3□V I =□10□mA C =□22 F OUT1 O O /c109 Z Output□ImpedanceO /c45 /c45 /c87 f Frequency Hz/c45 /c45 0.1 0.01 10 100 1□k 10□k 100□k 1 M 10 M V =□3.3□V I =□1□A C =□22 F OUT1 O O /c109 Z Output□ImpedanceO /c45 /c45 /c87 f Frequency Hz/c45 /c45 0.1 0.01 10 100 1□k 10□k 100□k 1 M 10 M V =□1.8□V I =□10□mA C =□47 F OUT2 O O /c109 Z Output□ImpedanceO /c45 /c45 /c87 f Frequency Hz/c45 /c45 0.1 0.01 10 100 1□k 10□k 100□k 1 M 10 M V =□1.8□V I =□2□A C =□47 F OUT2 O O /c109 Z Output□ImpedanceO /c45 /c45 /c87 f Frequency Hz/c45 /c45 TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 www.ti.com SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) OUTPUT IMPEDANCE OUTPUT IMPEDANCE vs vs FREQUENCY FREQUENCY Figure14. Figure15. OUTPUT IMPEDANCE OUTPUT IMPEDANCE vs vs FREQUENCY FREQUENCY Figure16. Figure17. Copyright© 2000–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17

/c45 40 /c45 25 /c45 10 5 20 35 50 65 80 95 110 125 100 150 200 250 IO =□1□A V V =□3.2□V OUT1 IN1 T T emperature C/c45 /c45 /c176 Dropout□Voltage /c45mV /c45 40 /c45 25 /c45 10 5 20 35 50 65 80 95 110 125 IO =□100□mA IO =□10□mA IO =□1□mA V V =□3.2□V OUT1 IN1 T T emperature C/c45 /c45 /c176 Dropout□Voltage /c45mV 100 150 200 250 2.5 3 3.5 4 4.5 5 5.5 300 V I =□1□A OUT1 O V Input□Voltage VI /c45 /c45 Dropout□Voltage /c45mV T =□125 CJ /c176 T = 40 CJ /c45 /c176 T =□25 CJ /c176 100 150 200 250 2.5 3 3.5 4 4.5 5 5.5 300 V I =□2□A OUT2 O V Input□Voltage VI /c45 /c45 T =□125 CJ /c176 T = 40 CJ /c45 /c176 T =□25 CJ /c176 Dropout□Voltage /c45mV TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) TPS70451 TPS70451 DROPOUT VOLTAGE DROPOUT VOLTAGE vs vs TEMPERATURE TEMPERATURE Figure18. Figure19. TPS70402 TPS70402 DROPOUT VOLTAGE DROPOUT VOLTAGE vs vs INPUT VOLTAGE INPUT VOLTAGE Figure20. Figure21.

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/c45 50 V =□1.8□V I =□2□A C =□47 F OUT2 O O /c109 t Time ms/c45 /c45 /c68 /c45 /c45 V Change□in mV O Output□Voltage I Output□Current AO /c45 /c45 0.5 /c45 50 /c45 100 V =□4.3□V V =□3.3□V C =□22 F IN1 OUT1 O /c109 /c68 /c45 /c45 V Change□in mV O Output□Voltage I Output□Current AO /c45 /c45 t Time ms/c45 /c45 0 20 40 60 80 100 120 140 160 180 20 100 2.8 100 3.8 200 V =□1.8□V I =□2□A C =□47 F OUT2 O O /c109 t Time s/c45 /c45 /c109 /c68 /c45 /c45 V Change□in mV O Output□Voltage V Input□Voltage VI/c45 /c45 0 20 40 60 80 100 120 140 160 180 200 4.3 5.3 100 V =□3.3□V I =□1□A C =□22 F OUT1 O O /c109 t Time s/c45 /c45 /c109 /c68 /c45 /c45 V Change□in mV O Output□Voltage V Input□Voltage VI/c45 /c45 TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 www.ti.com SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE Figure22. Figure23. LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE Figure24. Figure25. Copyright© 2000–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19

V =□3.3□V I =□1□A C =□22 F V =□4.3□V =□High OUT1 O O IN1 /c109 EN2 Enable□Voltage /c45V V Output□Voltage VO /c45 /c45 t Time ms/c45 /c45 0 2 V =□1.8□V I =□2□A C =□47 F V =□2.8□V =□High OUT2 O O IN2 /c109 EN1 t Time ms/c45 /c45 Enable□Voltage /c45V V Output□Voltage VO /c45 /c45 IN EN OUT GND ESR VIN COUT T o□Load RL TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT VOLTAGE AND ENABLE VOLTAGE OUTPUT VOLTAGE AND ENABLE VOLTAGE vs vs TIME (START-UP) TIME (START-UP) Figure26. Figure27. Figure28.TestCircuitforTypicalRegions ofStability

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0.1 0.01 0 0.2 REGION□OF□INSTABILITY V =□3.3□VOUT1 C =□220 F/c109O 15□m/c87 I Output□Current/c45 /c45O A ESR Equivalent□Series□Resistance /c45 /c87 /c45 0.1 0.01 0 0.2 REGION□OF□INSTABILITY V =□3.3□VOUT1 C =□22 F/c109O ESR Equivalent□Series□Resistance /c45 /c87 /c45 50□m/c87 I Output□Current/c45 /c45O A 0.1 0.01 REGION□OF□INSTABILITY V =□1.8□VOUT2 C =□680 F/c109O 15□m/c87 I Output□Current/c45 /c45O A ESR Equivalent□Series□Resistance /c45 /c87 /c45 0.1 0.01 0 0.2 REGION□OF□INSTABILITY V =□1.8□VOUT2 C =□47 F/c109O 50□m/c87 I Output□Current/c45 /c45O A ESR Equivalent□Series□Resistance /c45 /c87 /c45 TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 www.ti.com SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE (1) EQUIVALENT SERIES RESISTANCE (1) vs vs OUTPUT CURRENT OUTPUT CURRENT Figure29. Figure30. TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE (1) EQUIVALENT SERIES RESISTANCE (1) vs vs OUTPUT CURRENT OUTPUT CURRENT Figure31. Figure32. (1)Equivalentseriesresistance(ESR) referstothetotalseriesresistance,includingtheESR ofthecapacitor,any seriesresistanceadded externally,and PWB traceresistancetoC O . Copyright© 2000–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21

Side View□(a) End□View□(b) DIE Thermal Pad Bottom□View□(c) TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 www.ti.com THERMAL INFORMATION Thermally-EnhancedTSSOP-24 (PWP — PowerPAD ™ ) The thermally-enhancedPWP package is based on the 24-pinTSSOP, but includesa thermalpad [see Figure33(c)]toprovidean effectivethermalcontactbetween theIC and theprintedwiringboard(PWB). Traditionally,surfacemount and power have been mutuallyexclusiveterms. A varietyof scaled-down TO220-typepackages have leadsformedas gullwingstomake them applicableforsurface-mountapplications. These packages, however, sufferfrom severalshortcomings:they do not address the very low profile requirements(<2 mm) ofmany oftoday’s advanced systems,and theydo notoffera pin-counthighenough to accommodate increasingintegration.On theotherhand,traditionallow-powersurface-mountpackages require power-dissipationderatingthatseverelylimitstheusablerangeofmany high-performanceanalogcircuits. The PWP package (thermally-enhancedTSSOP) combines fine-pitchsurface-mounttechnologywiththermal performancecomparabletomuch largerpower packages. The PWP package isdesignedto optimizethe heat transferto the PWB. Because of the verysmallsizeand limitedmass ofa TSSOP package,thermalenhancement isachievedby improvingthethermalconductionpaths thatremove heatfrom thecomponent.The thermalpad isformed usinga lead-framedesign(patentpending) and manufacturingtechniquetoprovidetheuserwithdirectconnectiontotheheat-generatingIC.When thispad issolderedorotherwisecoupledtoan externalheatdissipator,highpower dissipationintheultrathin,fine-pitch, surface-mountpackage can be reliablyachieved. Figure33. Views ofThermally-EnhancedPWP Package Because the conductionpath has been enhanced, power-dissipationcapabilityisdeterminedby the thermal considerationsinthe PWB design.For example,simplyaddinga localizedcopper plane(heat-sinksurface), which is coupled to the thermalpad, enables the PWP package to dissipate2.5 W in freeair(reference Figure35(a),8 cm 2 of copper heat sinkand naturalconvection).Increasingthe heat-sinksizeincreasesthe power dissipationrangeforthecomponent.The power dissipationlimitcan be furtherimprovedby addingairflow to a PWB/IC assembly (see Figure34 and Figure35).The linedrawn at 0.3 cm 2 inFigure34 and Figure35 indicatesperformanceattheminimum recommended heat-sinksize,illustratedinFigure36.

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1 4 60.3 Natural Convection 50□ft/min 250□ft/min 300□ft/min 100□ft/min 150□ft/min 200□ft/min Copper□Heatsink□Area /c45 cm R Thermal□Resistance /c45 C/W /c113JA /c45/c176 TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 www.ti.com SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 The thermalpad isdirectlyconnectedtothesubstrateoftheIC,which fortheTPS704xx seriesisa secondary electricalconnectiontodeviceground.The heat-sinksurfacethatisadded tothePWP can be a groundplaneor leftelectricallyisolated.In TO220-type surface-mountpackages,the thermalconnectionisalsothe primary electricalconnectionfora giventerminalwhich isnot always ground.The PWP package providesup to 24 independentleads thatcan be used as inputsand outputs(Note: leads 1, 12, 13, and 24 are internally connectedtothethermalpad and theIC substrate). THERMAL RESISTANCE vs COPPER HEATSINK AREA Figure34. Copyright© 2000–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23

0.5 0 2 4 6 1.5 2.5 3.5 0.3 300 ft/min 150□ft/min Natural□Convection TA =□55/c176 C (b) 0.5 0 2 4 6 1.5 2.5 3.5 0.3 300□ft/min 150□ft/min Natural□Convection TA =□105/c176 C (c) 0.5 0 2 4 6 1.5 2.5 3.5 80.3 300□ft/min 150□ft/min Natural□Convection TA =□25/c176 C (a) Copper□Heatsink□Size /c45 cm P Power□Dissipation□Limit /c45 W D /c45 Copper□Heatsink□Size /c45 cm P Power□Dissipation□Limit /c45 W D /c45 Copper□Heatsink□Size /c45 cm P Power□Dissipation□Limit /c45 W D /c45 TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 www.ti.com Figure35. Power RatingsofthePWP Package atAmbient Temperatures of+25°C, +55°C, and +105°C

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Board□size Board□material FR4 Copper□trace/heat□sink 1□oz Exposed□pad□mounting 63/67□tin/lead□solder Heatsink□Area 1 oz Copper 3.2□in 3.2□in/c180 P =D(max) T T /c45Jmax A R/c113 JA(system) P =D(total) V V /c45IN1 OUT1( ( V V /c45IN2 OUT2( (/c180 I +□V /c180 +OUT1 IN1 I Q I Q /c180 /c180 I +□VOUT2 IN2 P =D(total) V V /c45IN1 OUT1( ( V V /c45IN2 OUT2( (/c180 I +OUT1 /c180 IOUT2 P =D(max) T T /c45Jmax A R/c113 JA(system) = +125 C 55 C/c45/c176 /c176 +50/c176 C/W =□1.4□W P =D(total) V V /c45IN1 OUT1( ( V V /c45IN2 OUT2( (/c180 I +OUT1 /c180 IOUT2 TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 www.ti.com SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 Figure36 isan example ofa thermally-enhancedPWB layoutforuse withthenew PWP package.Thisboard configurationwas used inthe thermalexperimentsthatgeneratedthe power ratingsshown inFigure34 and Figure35.As discussedearlier,copperhas been added on thePWB toconductheataway fromthedevice.R qJA forthisassembly isillustratedinFigure34 as a functionof heat-sinkarea.A familyof curvesisincludedto illustratetheeffectofairflowintroducedintothesystem. Figure36. PWB Layout (IncludingCopper HeatsinkArea)forThermally-EnhancedPWP Package From Figure 34, R qJA for a PWB assembly can be determined and used to calculatethe maximum power-dissipationlimitforthecomponent/PWB assembly,withtheequation: where:

TJmax isthemaximum specifiedjunctiontemperature(+150°C absolutemaximum limit,+125°C recommended operatinglimit)and TA istheambienttemperature. (1) PD(max) shouldthen be appliedto the internalpower dissipatedby the TPS704xx regulator.The equationfor calculatingtotalinternalpower dissipationoftheTPS704xx is: (2) SincethequiescentcurrentoftheTPS704xx isverylow,thesecond term isnegligible,furthersimplifyingthe equationto: (3) For the case where TA = +55°C, airflow= 200 ft/min,copper heat-sinkarea = 4 cm 2, the maximum power-dissipationlimitcan be calculated.First,from Figure34,we findthesystem R qJA is+50°C/W; therefore, themaximum power-dissipationlimitis: (4) Ifthesystem implementsa TPS704xx regulator,where VIN1 = 5.0V,VIN2 = 2.8V, IOUT1 = 500 mA, and IOUT2 = 800 mA, theinternalpower dissipationis: (5) Copyright© 2000–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25

Thermal□Pad□on PWP□Package Minimum□Recommended Heatsink□Area TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 www.ti.com Comparing PD(total)withPD(max) revealsthatthepower dissipationinthisexample does notexceed thecalculated limit.When itdoes, one of two correctiveactionsshould be made: raisingthe power-dissipationlimitby increasingtheairflowortheheat-sinkarea,orloweringtheinternalpower dissipationoftheregulatorby reducing the inputvoltageor the loadcurrent.In eithercase,the above calculationsshouldbe repeatedwiththe new system parameters.Thisparameterismeasured withtherecommended copperheatsinkpatternon a 4-layer PWB, 2 oz.coppertraceson 4-in× 4-ingroundlayer.Simultaneousand continuousoperationofbothregulator outputsatfullloadmay exceed thepower dissipationratingofthePWP package. Mounting Information The primaryrequirementistocompletethethermalcontactbetween thethermalpad and thePWB metal.The thermalpad isa solderablesurfaceand isfullyintendedtobe solderedatthetimethecomponent ismounted. Althoughvoidinginthethermal-padsolder-connectionisnotdesirable,up to50% voidingisacceptable.The data includedinFigure34 and Figure36 are forsolderedconnectionswithvoidingbetween 20% and 50%. The thermalanalysisshows no significantdifferenceresultingfromthevariationinvoidingpercentage. Figure37 shows thesolder-masklandpatternforthePWP package.The minimum recommended heat-sinkarea isalsoillustrated.Thisissimplya copperplaneunder thebody extentofthepackage,includingmetalrouted underterminals1,12,13,and 24. Figure37. PWP Package Land Pattern

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2□V <0.7□V >2□V <0.7□V TPS704xxPWP (Fixed□Output□Option)

0.22 F/c109

47 F/c109

22 F/c109 250□k/c87

250□k/c87 RESET RESET VIN VIN1 VIN2 VOUT1 VSENSE1 PG1 MR MR VOUT1 EN1 EN2 EN1 EN2 VSENSE2 VOUT2 PG2 PG2 VOUT2 95% 95% PG2 PG1 NOTES:□A.□t :□Time□at□which□V is□greater□than□V and is□logic□high. B.□The□timing□diagram□is□not□drawn□to□scale.

1 IN UVLO MR

120□ms EN2 EN1 VOUT2 VOUT1 MR MR(PG2□tied□to ) RESET TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 www.ti.com SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010

APPLICATION INFORMATION

Sequencing Timing Diagrams This sectionprovidesa number of timingdiagrams showing how this device functionsin different configurations. same fixedinputvoltagegreaterthan VUVLO . PG2 is tiedtoMR. EN1 and EN2 are initiallyhigh; therefore,both regulatorsareoff,and PG1 and PG2 (tiedtoMR) are atlogiclow.SinceMR isatlogiclow,RESET isalso at logiclow.When EN1 istakento logiclow,VOUT1 turnson.Later,when EN2 istakentologiclow,VOUT2 turnson. When VOUT1 reaches95% of itsregulated outputvoltage,PG1 goes tologichigh.When VOUT2 reaches 95% of itsregulatedoutputvoltage,PG2 (tiedtoMR) goes tologichigh.When VIN1 isgreater than VUVLO and M R (tiedto PG2) isat logichigh, RESET ispulledto logichighaftera 120-ms delay. When EN1 and EN2 are returnedtologichigh,both devicespower down and both PG1, PG2 (tiedto MR2), and RESET returntologiclow. Figure38. Timing When VOUT1 IsEnabled BeforeVOUT2 Copyright© 2000–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27

2□V 0.7□V TPS704xxPWP (Fixed□Output□Option)

22 F/c109

250□k/c87 250□k/c87 250□k/c87

2□V <0.7□V >2□V <0.7□V EN2 EN1 VIN2 VIN1 VIN VOUT2 VSENSE2 MR PG2 RESET VSENSE1 VOUT1 MR RESET PG2 VOUT2 VOUT1 95% 95% EN2 EN1 VOUT1 VOUT2 PG2 PG1 MR RESET NOTES:□A.□t :□Time□at□which□V is□greater□than□V and is□logic□high. B.□The□timing□diagram□is□not□drawn□to□scale.

120□ms TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 www.ti.com same fixedinputvoltagegreaterthan VUVLO . MR is initiallylogichighbutiseventuallytoggled. EN1 and EN2 are initiallyhigh; therefore,both regulatorsareoff,and PG1 and PG2 areatlogiclow. Since VIN1 isgreaterthan VUVLO and MR isat logic high,RESET isalsoatlogichigh.When EN2 istaken tologiclow,VOUT2 turnson.Later,when EN1 istaken to logiclow,VOUT1 turnson. When VOUT2 reaches 95% of itsregulatedoutputvoltage,PG2 goes to logichigh.When VOUT1 reaches95% ofitsregulated outputvoltage,PG1 goes tologichigh.When MR is taken to logiclow,RESET istaken low.When MR returnsto logichigh,RESET returnsto logichigh aftera 120-ms delay. Figure39. Timing When MR isToggled

(Fixed□Output□Option)

0.22 F/c109 22 F/c109

250□k/c87 250□k/c87

2□V <0.7□V >2□V <0.7□V EN1 EN2 EN1 EN2 VIN1 VIN2 VIN RESET VOUT1 VSENSE1 PG1 MR VSENSE2 VOUT2 PG2 VOUT2 RESET PG2 VOUT1 95% 95% EN2 EN1 VOUT1 VOUT2 PG2 PG1 MR MR(PG1□tied□to ) RESET FAULT□ON□VOUT1 NOTES:□A.□t :□Time□at□which□V is□greater□than□V and is□logic□high. B.□The□timing□diagram□is□not□drawn□to□scale.

120□ms TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 www.ti.com SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 same fixedinputvoltagegreaterthan VUVLO . PG1 is tiedtoMR. EN1 and EN2 are initiallyhigh; therefore,both regulatorsareoff,and PG1 (tiedtoMR) and PG2 are atlogiclow.SinceMR isatlogiclow,RESET isalso at logiclow.When EN2 istakento logiclow,VOUT2 turnson.Later,when EN1 istakentologiclow,VOUT1 turnson. When VOUT2 reaches95% of itsregulated outputvoltage,PG2 goes tologichigh.When VOUT1 reaches 95% of itsregulatedoutputvoltage,PG1 goes to logichigh.When VIN1 isgreaterthan VUVLO and MR (tiedto PG2) is at logichigh,RESET is pulledto logichigh aftera 120-ms delay.When a faulton VOUT1 causes itto fallbelow 95% of its regulatedoutputvoltage,PG1 (tiedto MR) goes to logiclow.SinceMR islogiclow,RESET goes tologic low.VOUT2 isunaffected. Figure40. Timing When There isa Faulton VOUT1 Copyright© 2000–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29

TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 www.ti.com For a typicalapplication,a ceramicinputbypass capacitor(0.22mF to 1 mF) isrecommended. Thiscapacitor shouldbe as closeto the inputpinsas possible.Due to the impedance of the inputsupply,largetransient currentscause the inputvoltageto droop.Ifthisdroop causes the inputvoltageto drop below the UVLO threshold,the deviceturnsoff.Therefore,itisrecommended to placea largercapacitorin parallelwiththe ceramicbypass capacitorat the regulatorinput.The sizeof thiscapacitordepends on the outputcurrent,the responsetimeofthemain power supply,and themain power supplydistancetotheregulator.Ata minimum, the capacitorshouldbe sizedto ensure thatthe inputvoltagedoes not drop below the minimum UVLO threshold voltageduringnormaloperatingconditions. Output Capacitor As withmost LDO regulators,theTPS704xx requiresan outputcapacitorconnectedbetween OUT and GND to stabilizetheinternalcontrolloop.The minimum recommended capacitancevalueforVOUT1 is22 mF and theESR (equivalentseriesresistance)must be between 50 m Ω and 800 m Ω.The minimum recommended capacitance valueforVOUT2 is47 mF and theESR must be between 50 m Ω and 2 Ω.Solidtantalumelectrolytic,aluminum electrolytic,and multilayerceramiccapacitorsare allsuitable,providedtheymeet the requirementsdescribed above.Largercapacitorsprovidea widerrange ofstabilityand betterloadtransientresponse.Table1 givesa partiallistingof surface-mountcapacitorssuitableforuse with the TPS704xx forfasttransientresponse applications. Thisinformation,alongwiththeESR graphs,isincludedtoassistinselectionofsuitablecapacitanceforuser applications.When necessarytoachievelow heightrequirementsalongwithhighoutputcurrentand/orhighload capacitance,severalhigherESR capacitorscan be used inparalleltomeet theguidelinesabove. Table1.PartialListingofTPS704xx-Compatible Surface-MountCapacitors VALUE MANUFACTURER MFR PART NO. 680 mF Kemet T510X6871004AS 470 mF Sanyo 4TPB470M 150 mF Sanyo 4TPC150M 220 mF Sanyo 2R5TPC220M 100 mF Sanyo 2R5TPC220M 68 mF Sanyo 10TPC68M 68 mF Kemet T495D6861006AS 47 mF Kemet T495D4761010AS 33 mF Kemet T495C3361016AS 22 mF Kemet T495C2261010AS

R1□= V V OUT REF /c45 1 /c180 R2( ( OUTPUT□VOLTAGE PROGRAMMING□GUIDE VO VI OUT FB GND EN IN <0.7□V >2.0 V TPS70402 0.1 /c109F OUTPUT VOLTAGE R1 R2 2.5□V 3.3□V 3.6□V UNIT 31.6 51.1 59.0 30.1 30.1 30.1 k/c87 k/c87 k/c87 TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 www.ti.com SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 Programming theTPS70402 AdjustableLDO Regulator The outputvoltageof the TPS70402 adjustableregulatorsisprogrammed usingexternalresistordividersas shown inFigure41. ResistorsR1 and R2 shouldbe chosen forapproximatelya 50-mA dividercurrent.Lower valueresistorscan be used,but offerno inherentadvantageand waste more power.Highervaluesshouldbe avoidedas leakage currentsat the sense terminalincreasethe outputvoltageerror.The recommended designprocedureisto choose R2 = 30.1kΩ tosetthedividercurrentatapproximately50 mA,and thencalculateR1 usingEquation6: (6) where:

VREF = 1.224V typ(theinternalreferencevoltage) Figure41. TPS70402 AdjustableLDO RegulatorProgramming RegulatorProtection Both TPS704xx PMOS-pass transistorshave built-inback diodesthatconductreversecurrentswhen theinput voltagedropsbelow theoutputvoltage(forexample,duringpower-down).Currentisconductedfromtheoutput totheinputand isnotinternallylimited.When extendedreversevoltageisanticipated,externallimitingmay be appropriate. The TPS704xx also featuresinternalcurrentlimitingand thermalprotection.During normal operation,the TPS704xx regulator1 limitsoutputcurrenttoapproximately1.75A (typ)and regulator2 limitsoutputcurrentto approximately3.8 A (typ).When currentlimitingengages, the outputvoltagescalesback linearlyuntilthe overcurrentconditionends.While currentlimitingisdesignedto preventgrossdevicefailure,care shouldbe taken not to exceed the power dissipationratingsof the package.Ifthe temperatureof the deviceexceeds +150°C (typ),thermal-protectioncircuitryshuts itdown. Once the devicehas cooled below +130°C (typ), regulatoroperationresumes. Copyright© 2000–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31

TPS70445,TPS70448 TPS70451,TPS70458 TPS70402 SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 www.ti.com

REVISION HISTORY

NOTE: Page numbers forpreviousrevisionsmay differfrompage numbers inthecurrentversion. Changes from RevisionE (February2010)toRevisionF Page Changes from RevisionD (December, 2007)toRevisionE Page

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TPS70402PWP ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70402PWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70402PWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70402PWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70445PWP ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70445PWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70445PWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70445PWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70448PWP ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70448PWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70448PWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70448PWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70451PWP ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70451PWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70451PWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70451PWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70458PWP ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70458PWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70458PWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70458PWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2010 Addendum-Page 1

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2010 Addendum-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS70402PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS70445PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS70448PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS70451PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS70458PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2

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Summary

DUAL-OUTPUT, LOW DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS

Description