10HSI-S008-R0-C

10HSI-S008-R0-C HIROSE | Alldatasheet

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Copyright © 2010 Hirose Electric USA, Inc. Signal Integrity Report IT3 Mezzanine Connector (32mm) Version 2.1 January 28, 2010 10HSI-S008-R0-C HIROSE ELECTRIC (U.S.A.), INC. 20400 STEVENS CREEK BLVD., SUITE 250 SAN JOSE, CA 95014 PHONE: 408-253-9640, FAX: 408-253-9641

Signal Integrity Report – IT3 (32mm) Page ii Table of Contents

Signal Integrity Report – IT3 (32mm) Page iii

Revision History

Name Date Reason For Changes Version Fernando Cheng 8-17-09 First created 1.0 Fernando Cheng 12-10-09 Updated time-domain data 2.0 Fernando Cheng 1-28-09 Updated time-domain data 2.1

Signal Integrity Report – IT3 (32mm) Page 5 Figure 3 shows the cross section of interposer. The loosely-coupled design gives 50.24 ohm impedance for single-ended signals and 98.87 ohm impedance for differential signals, with process variations. The line-to-line coupling is 0.80%, and the pair-to-pair coupling is 0.36%. Figure 3 Cross-section of interposer 3. Differential Signals

3.1 Frequency-Domain Modeling

3.1.1 S parameters (connector only)

Figure 4 shows the simulation model for IT3-32 mm (connector only). We used symmetry to combine four quarter models created from HFSS into a 60-port single-ended Touchstone file. The 60-port single-ended model was then converted into a 30-port differential Touchstone file. Figure 4 IT3-32mm simulation model

Signal Integrity Report – IT3 (32mm) Page 6

3.1.1.1 Fully populated pin assignment

For fully-populated pin assignment, as shown in Figure 5, Ports 1-2 are grouped into Pair 1, and Ports 3-4 are grouped into Pair 2, …, etc. Figure 6 shows the corresponding SDD for pair 8 (or Ports 15-16), where the insertion loss (IL), return loss (RL), and crosstalk can be clearly seen, and are summarized in Table 1. The impedance and trace delay values for each of the 15 differential pairs are shown in Table 2. Figure 7 shows the return loss (RL) comparison with the IEEE802.3ap spec for the center pair 8. Figure 8 - Figure 11 show the power sum and insertion-to-crosstalk ratio (ICR) profile comparison with the IEEE802.3ap spec of NEXT and FEXT, respectively. Figure 5 Fully populated pin assignment Figure 6 SDD for pair 8 (ports 15-16) of connector only

Signal Integrity Report – IT3 (32mm) Page 7 FREQUENCY (GHZ) INSERTION LOSS (DB) RETURN LOSS (DB) WORST PAIR-TO-PAIR NEXT (DB) WORST PAIR-TO-PAIR FEXT (DB) Table 1 Summary of SDD for pair 8 (ports 15-16) of connector only Table 2 Summary of connector’s differential impedance and delay at 1.0 GHz Figure 7 RL profile for pair 8 of connector only

Signal Integrity Report – IT3 (32mm) Page 15 Figure 22 Power Sum of FEXT for pair 4 of connector only for 50% pin density configuration Figure 23 ICR profile of FEXT for pair 4 of connector only for 50% pin density configuration

3.1.2 S parameters (vias only)

The electrical performance of the via depends on the connector’s footprint and PCB stackup. The PCB stackup is usually customer-specific. An example is given in Figure 24. The stackup consists of 30 layers, totaling 121.78mil in thickness. To have ~100 Ohms differential impedance, the signal line width and spacing are set to 3.5 mil and 7.5 mil, respectively, with ε r=3.80 and tanδ=0.01. The via models used in this document are extracted from the demo board. In this document, we consider the connector to be mounted from the top layer 1. Thus, a large layer number corresponds

Signal Integrity Report – IT3 (32mm) Page 16 to a short via stub (Note that in IT3_demo_board_v2.doc, a larger routing layer corresponds to a longer via-stub). The via transition through the middle layer 16 of the PCB was studied in order to test a relatively long via stub of ~60mil. Figure 25 shows the top and side views of the transition which includes the PCB layers of the traces connected to each via. Via models through layers 3, layer 12, layer 16, layer 19, and layer 28 have been modeled to study the effects of the insertion loss for short and long via stubs. Only three routing layers are needed to route all differential pairs on the IT3 connector (with two pairs exiting on one side and three on the other side of the connector, as observed in Figure 25) The ports have been numbered such that 1 to 30 correspond to the top side of the PCB, and 31 to 60 are for the PCB trace connections. Ports 1-2 are grouped into pair 1, and ports 3-4 are grouped into pair 2, etc. Figure 26 shows the corresponding SDD for pair 8 (or ports 15-16) of via transition with PCB routing on layer 16. Layer No. Mil Solder mask 0.5 1 TOP 2.84 Pre-preg 4.5 2 Ground 0.7 Core 3 3 Sig 1 0.7 Pre-preg 3.5 4 Sig 2 0.7 Core 3 5 Ground 0.7 Pre-preg 3.5 6 Ground 0.7 Core 3 7 Sig 3 0.7 Pre-preg 3.5 8 Sig 4 0.7 Core 3 9 Ground 0.7 Pre-preg 3.5 10 Ground 0.7 Core 3 11 Sig 5 0.7 Pre-preg 3.5 12 Sig 6 0.7 Core 3 13 Ground 0.7 Pre-preg 3.5 14 Ground 0.7 Core 3 15 Sig 7 0.7 Pre-preg 3.5

Signal Integrity Report – IT3 (32mm) Page 17 16 Sig 8 0.7 Core 3 17 Ground 0.7 Pre-preg 3.5 18 Ground 0.7 Core 3 19 Sig 9 0.7 Pre-preg 3.5 20 Sig10 0.7 Core 3 21 Ground 0.7 Pre-preg 3.5 22 Ground 0.7 Core 3 23 Sig11 0.7 Pre-preg 3.5 24 Sig12 0.7 Core 3 25 Ground 0.7 Pre-preg 3.5 26 Ground 0.7 Core 3 27 Sig13 0.7 Pre-preg 3.5 28 Sig14 0.7 Core 3 29 Ground 0.7 Pre-preg 4.5 30 BOTTOM 2.84 Solder mask 0.5 Total thickness (mil) 121.78 Figure 24 Sample PCB stackup

Signal Integrity Report – IT3 (32mm) Page 18 Figure 25 Top and side views of via transition with PCB routed on layer 16 Figure 26 SDD for center pair 8 of via transition with routing on layer 16

3.1.3 S parameters (vias + connector + vias)

Figure 27 and Figure 32 show the SDD response (i.e., insertion loss, return loss, NEXT, and FEXT) for pair 8 and pair 4 for 100% and 50% pin density configuration of the cascaded vias/connector/vias with PCB routing in the 16th layer for both via transitions. All PCB traces coming out from the vias have been matched to 10.507mm. The results at various frequencies of interest are summarized in Table 5 and Table 6 for 100% and 50% pin density configuration respectively. Figure 28 - Figure 31 and Figure 33 - Figure 36 show the power sum and insertion-to- crosstalk ratio (ICR) profile comparison with the IEEE802.3ap spec of NEXT and FEXT for the different pin density configurations.

3.1.3.1 Fully populated pin assignment

Signal Integrity Report – IT3 (32mm) Page 23 Figure 35 Power Sum of FEXT for pair 4 of via+connector+via transition with routing on layer 16 for 50% pin density configuration Figure 36 ICR profile of FEXT for pair 4 of via+connector+via transition with routing on layer 16 for 50% pin density configuration

3.1.4 W-element Model (PCB trace)

The signal traces in the PCB follow the cross section in Figure 37 for 100 Ohms differential impedance. The corresponding W-element model and differential S parameters are shown in Figure 38 and Figure 39. The RL comparisons with the IEEE 802.3ap spec for the full channel model with the connector, vias and PCB traces of 76.2mm + 76.2mm (3” + 3”) and 152.4mm + 152.4mm (6” + 6”) are shown in Figure 40 and Figure 41.

Signal Integrity Report – IT3 (32mm) Page 26 Figure 41 RL profile for pair 8 of cascaded model of connector, vias and 152.4mm+152.4mm (6”+6”) PCB traces

3.2 Time-Domain Simulation

3.2.1 Impedance Profile (connector only)

The impedance profiles for center pair 8, right edge pair 10, top edge pair 14, and top corner pair 15 of the fully populated model (connector only), as portrayed in Figure 42, are shown in Figure 43 - Figure 46. Figure 42 Differential pairs for fully populated model

Signal Integrity Report – IT3 (32mm) Page 28 Figure 46 Impedance profile for top corner pair 15 of IT3-32mm (connector only) @60ps rise time (20% to 80%) and 5.25GHz BW, and @30ps rise time (20% to 80%) and 10.5GHz BW The receptacles show higher impedance in the connector-only TDR waveforms because IT3 was designed intentionally with slightly higher impedance in the receptacle to offset the via’s (and via stub’s) low impedance, as shown in the next section.

3.2.2 Impedance Profile (vias + connector + vias)

The impedance profiles for center pair 8, right edge pair 10, top edge pair 14, and top corner pair 15 of the fully populated model (vias + connector + vias), as portrayed in Figure 42, are shown in Figure 47, Figure 48, Figure 49 and Figure 50. The via models for center pair 8 and right edge pair 10 are routed on layer 16, the top edge pair 14 vias are routed on layer 28 (short via stub), and the vias for the top corner pair 15 are routed on layer 19. Figure 47 Impedance profile for center pair 8 of IT3-32mm (vias+connector+vias) with routing on layer 16 @60ps rise time (20% to 80%) and 5.25GHz BW, and @30ps rise time (20% to 80%) and 10.5GHz BW Vias Interposer Vias Receptacle Receptacle

Signal Integrity Report – IT3 (32mm) Page 29 Figure 48 Impedance profile for right edge pair 10 of IT3-32mm (vias+connector+vias) with routing on layer 16 @60ps rise time (20% to 80%) and 5.25GHz BW, and @30ps rise time (20% to 80%) and 10.5GHz BW Figure 49 Impedance profile for top edge pair 14 of IT3-32mm (vias+connector+vias) with routing on layer 28 @60ps rise time (20% to 80%) and 5.25GHz BW, and @30ps rise time (20% to 80%) and 10.5GHz BW Figure 50 Impedance profile for top corner pair 15 of IT3-32mm (vias+connector+vias) with routing on layer 19 @60ps rise time (20% to 80%) and 5.25GHz BW, and @30ps rise time (20% to 80%) and 10.5GHz BW

3.2.3 TDR and TDT waveforms (connector only)

3.2.3.1 Fully populated pin assignment

Signal Integrity Report – IT3 (32mm) Page 35 Figure 59 TDR and TDT waveforms @120ps rise time (20% to 80%) and 2.625GHz BW for pair 4 of IT3-32mm for 50% pin density configuration 20% TO 80% RISE TIME (PS) WORST PAIR-TO-PAIR NEXT (%) WORST PAIR-TO-PAIR FEXT (%) 30 0.082 0.142 60 0.045 0.082 120 0.023 0.042 Table 9 Summary of Time-domain SDD for pair 4 of IT3-32mm for 50% pin density configuration

3.2.4 Time-Domain Crosstalk (connector only)

The total differential cross-talk values in % for at 60ps (20% to 80%) rise time and 5.25GHz bandwidth for center pair 8 of the fully populated model and, pair 4 for 60% and 50% pin density are shown in Figure 60, Figure 61 and Figure 62. The outer column (top row as portrait in Figure 60) exhibits higher crosstalk as it is only surrounded by one ground plane.

3.2.4.1 Fully populated pin assignment

Figure 60 Differential cross-talk (in %) from simulations for center pair 8 and step input @ 60ps (20% to 80%) rise time and 5.25GHz BW

Signal Integrity Report – IT3 (32mm) Page 36 3.2.4.2 60% density pin assignment Figure 61 Differential cross-talk (in %) from simulations for pair 4 of 60% pin density configuration and step input @ 60ps (20% to 80%) rise time and 5.25GHz BW 3.2.4.3 50% density pin assignment Figure 62 Differential cross-talk (in %) from simulations for pair 4 of 50% pin density configuration and step input @ 60ps (20% to 80%) rise time and 5.25GHz BW

3.2.5 System Voltage and Timing Margins

To demonstrate the IT3’s performance, we ran simulations for the following setup: „ Ideal voltage source with package via. „ Center pair of the IT3 connector with via transition in the 16th PCB routing layer. „ 152.4mm (6 inches) PCB trace from driver to IT3 connector, and 152.4mm (6 inches) PCB trace from IT3 connector to receiver, including via transition to the receiver. The 16th routing layer was chosen to demonstrate that the channel works even with long via stubs of ~60mil, which allows for more design flexibility. Note: Since the time steps used for the simulations were of 1ps, the timing jitter values have an error margin of 1ps. The eye height is defined as the absolute maximum eye opening.

3.2.5.1 Fully populated pin assignment

The full channel includes package-via models without crosstalk effects at the transmitter and receiver. The following eye diagrams account for these package-via effects, which are not included in the channel model defined in the IEEE 802.3ap spec. For the center-pair channel, the models for package via and connector via are identical (i.e. same via stub length). Table 10, Table 11 and Table 12 show the optimized tap coefficients for the maximum eye opening at various data rates for the channel without the connector and connector vias (Base Case 1), for the channel without the connector only (Base Case 2), and for the full channel.

Signal Integrity Report – IT3 (32mm) Page 38 Data Rate (Gbps) PRE- CURSOR[1] MAIN CURSOR POST- CURSOR[1] 6.25 -0.0487 0.8014 -0.1499 10 -0.0942 0.7252 -0.1806 Table 12 Full channel: optimum tap setting coefficients for center pair 8 of IT3-32mm connector Figure 64 Base case 1, 2 and full channel eye diagram at receiver input for 3.125Gbps data rate with routing on layer 16 and 14 FEXT

Signal Integrity Report – IT3 (32mm) Page 39 Figure 65 Base case 1, 2 and full channel eye diagram at receiver input for 5Gbps data rate with routing on layer 16 and 14 FEXT

Signal Integrity Report – IT3 (32mm) Page 42 Data Rate (Gbps) PRE- CURSOR[3] PRE- CURSOR[2] PRE- CURSOR[1] MAIN CURSOR POST- CURSOR[1] POST- CURSOR[2] POST- CURSOR[3] Table 17 Full channel: optimum tap setting coefficients for center pair 4 of IT3-32mm connector for 50% pin density configuration Figure 68 Base case 1, 2 and full channel eye diagram at receiver input for 5Gbps data rate with routing on layer 16 and 6 FEXT for 50% pin density configuration

Signal Integrity Report – IT3 (32mm) Page 43 Figure 69 Base case 1, 2 and full channel eye diagram at receiver input for 6.25Gbps data rate with routing on layer 16 and 6 FEXT for 50% pin density configuration

Signal Integrity Report – IT3 (32mm) Page 45 Figure 72 Base case 1, 2 and full channel eye diagram at receiver input for 20Gbps data rate with routing on layer 16 and 6 FEXT for 50% pin density configuration Timing Jitter (ps) Eye Height (mV) Data Rate (Gbps) IT3 Base Case 1 ΔIT3 ΔIT3 (%) IT3 Base Case 1 ΔIT3 ΔIT3 (%) Table 18 Comparison of eye height and timing fuzz between full channel and Base Case 1 at the receiver’s input with 6 FEXT for 50% pin density configuration Timing Jitter (ps) Eye Height (mV) Data Rate (Gbps) IT3 Base Case 2 ΔIT3 ΔIT3 (%) IT3 Base Case 2 ΔIT3 ΔIT3 (%) Table 19 Comparison of eye height and timing fuzz between full channel and Base Case 2 at the receiver’s input with 6 FEXT for 50% pin density configuration

Signal Integrity Report – IT3 (32mm) Page 46 4. Single-ended Signals

4.1 Frequency-Domain Modeling

4.1.1 S parameters (connector only)

A 60-port single-ended Touchstone file was used as described in Section 3.1.1. The single-ended pin assignment is shown in Figure 73. For our analyses, we consider ports 3-27 and ports 33-57. Figure 74 shows the corresponding S-parameters for port 15, where the insertion loss (IL), return loss (RL), and crosstalk can be clearly seen, and are summarized in Table 20. Impedance and trace delay values for each of the 30 single-ended traces are shown in Table 21. Figure 75 and Figure 76 show the absolute sum of near-end and far-end crosstalk, respectively. Figure 73 Single-ended pin assignment Figure 74 S-parameters for port 15 of connector only

Signal Integrity Report – IT3 (32mm) Page 47 FREQUENCY (MHZ) INSERTION LOSS (DB) RETURN LOSS (DB) WORST PAIR-TO-PAIR NEXT (DB) WORST PAIR-TO-PAIR FEXT (DB) Table 20 Summary of S-parameters for port 15 of connector only Table 21 Summary of connector’s single-ended impedance and delay at 1.0 GHz Figure 75 Power Sum of NEXT for port 15 of connector only

Signal Integrity Report – IT3 (32mm) Page 48 Figure 76 Power Sum of FEXT for port 15 of connector only

4.1.2 S parameters (vias only)

Figure 77 shows the single-ended via model S-parameters of port 15, as described in Section 3.1.2. Figure 77 S-parameters for port 15 of via transition with routing on layer 16

4.1.3 S parameters (vias + connector + vias)

Figure 78 shows the S-parameters (i.e., insertion loss, return loss, NEXT, and FEXT) for port 15 of the cascaded vias/connector/vias model with PCB routing in the 16th layer for both via

Signal Integrity Report – IT3 (32mm) Page 50 Figure 80 Power Sum of FEXT for port 15 of vias+connector+vias transition with routing on layer 16

4.1.4 W-element Model (PCB trace)

The signal traces in the PCB follow the cross section in Figure 81 for 50 Ohms single-ended impedance. The corresponding W-element model and S parameters are shown in Figure 82 and Figure 83. Figure 81 Cross section of single-ended PCB trace

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4.2 Time-Domain Simulation

4.2.1 Impedance Profile (connector only)

The impedance profiles for center port 15, right edge port 20, top edge port 29, and top corner port 30, as portrayed in Figure 84, are shown in Figure 85, Figure 86, Figure 87 and Figure 88. Figure 84 Single-ended pins for fully populated model Figure 85 Impedance profile for center port 15 of IT3-32mm (connector only) @120ps rise time (20% to 80%) and 2.625GHz BW

Signal Integrity Report – IT3 (32mm) Page 54 Figure 88 Impedance profile for top corner port 30 of IT3-32mm (connector only) @120ps rise time (20% to 80%) and 2.625GHz BW

4.2.2 Impedance Profile (via + connector + via)

The impedance profiles for center port 15, right edge port 20, top edge port 29, and top corner port 30 of the fully populated model (via + connector + via) as portrayed in Figure 84, are shown in Figure 89, Figure 90, Figure 91 and Figure 92. The via model for center port 15 and right edge port 20 are routed on layer 16, and the top edge port 29 and top corner port 30 vias are routed on layer 19. Since the same differential via models were used for our single-ended model analysis, each via will have additional coupling from an adjacent via with routing on the same layer. Figure 89 Impedance profile for center port 15 of IT3-32mm (via+connector+via) with routing on layer 16 @120ps rise time (20% to 80%) and 2.625GHz BW

Signal Integrity Report – IT3 (32mm) Page 56 Figure 92 Impedance profile for top corner port 30 of IT3-32mm (via+connector+via) with routing on layer 16 @120ps rise time (20% to 80%) and 2.625GHz BW

4.2.3 TDR and TDT waveforms (connector only)

Figure 93 - Figure 95 show the TDR and TDT waveforms at 120ps and 150ps and 180ps rise times (20% to 80%) for port 15 of IT3-32mm. The worst cross-talk values to the center port are summarized in Table 23. Figure 93 TDR and TDT waveforms @120ps rise time (20% to 80%) and 2.625GHz BW for port 15 of IT3-32mm

Signal Integrity Report – IT3 (32mm) Page 57 Figure 94 TDR and TDT waveforms @150ps rise time (20% to 80%) and 2.1GHz BW for port 15 of IT3-32mm Figure 95 TDR and TDT waveforms @180ps rise time (20% to 80%) and 1.75GHz BW for port 15 of IT3-32mm 20% TO 80% RISE TIME (PS) WORST PAIR-TO-PAIR NEXT (%) WORST PAIR-TO-PAIR FEXT (%) 120 1.733 1.825 150 1.502 1.416 180 1.340 1.159 Table 23 Summary of Time-domain cross-talk for port 15 of IT3-32mm

4.2.4 Time-Domain Crosstalk (connector only)

Signal Integrity Report – IT3 (32mm) Page 58 The total single-ended cross-talk values in % at 120ps (20% to 80%) rise time and 2.625GHz bandwidth for port 15 is shown in Figure 96. Figure 96 Single-ended cross-talk (in %) from simulations for port 15 and step input @ 120ps (20% to 80%) rise time and 2.625GHz BW

4.2.5 System Voltage and Timing Margins

To demonstrate the IT3’s performance for single-ended signals, we ran simulations for the following setup: „ Ideal voltage source with package via. „ Center pin of IT3 connector with via transition in the 16th PCB routing layer. „ 152.4mm (6 inches) PCB trace from driver to IT3 connector, and 152.4mm (6 inches) PCB trace from IT3 connector to receiver, including via transition to the receiver. Note: Since the time steps used for the simulations were of 1ps, the timing jitter values have an error margin of 1ps. The eye height is defined as the absolute maximum eye opening.

Signal Integrity Report – IT3 (32mm) Page 59 Figure 97 Base case 1, 2 and full channel eye diagram at single-ended receiver input for 1600Mbps data rate with routing on layer 16 and 14 FEXT Timing Jitter (ps) Eye Height (mV) Data Rate (Mbps) IT3 Base Case 1 ΔIT3 ΔIT3 (%) IT3 Base Case 1 ΔIT3 ΔIT3 (%) Table 24 Comparison of eye height and timing fuzz between single-ended full channel and Base Case 1 at the receiver’s input with 14 FEXT Timing Jitter (ps) Eye Height (mV) Data Rate (Mbps) IT3 Base Case 2 ΔIT3 ΔIT3 (%) IT3 Base Case 2 ΔIT3 ΔIT3 (%) Table 25 Comparison of eye height and timing fuzz between single-ended full channel and Base Case 2 at the receiver’s input with 14 FEXT

Signal Integrity Report – IT3 (32mm) Page 60 5. Measurement

5.1 Measurement Setup

To measure the connector’s performance directly we pre-characterized and de-embedded the test boards to eliminate the effects of SMAs, traces and vias. The characterization boards were designed to have minimal effect on the connector’s performance. The traces have controlled impedance of 50Ω and coplanar traces were used to minimize the crosstalk from trace to trace. Please refer to the document IT3_Characterization_Board_v09.doc for more details about the characterization board for IT3. The measurement setup is shown in Figure 98. Figure 98 Measurement setup IT3-32mm was also tested in a 12” channel with 120mil FR408 board, mid-layer routing, and 8- aggressor cross-talk, as shown in Figure 99. Please refer to the document IT3_demo_board_v2.doc for more details about the demo board for IT3. Figure 99 Demo board setup

Signal Integrity Report – IT3 (32mm) Page 61

5.2 Differential Signals

5.2.1 Measurement vs. Simulation Correlation (connector only) Figure 101 and Figure 102 show the measurement vs. simulation correlation of insertion loss (IL), return loss (RL) and differential S parameters (SDD) between two nearest neighboring pairs for the center differential pair 8 (as shown in Figure 100). Good correlation was observed for all IL, RL, near-end cross-talk (NEXT), and far-end cross-talk (FEXT). Figure 100 Differential NEXT and FEXT for center pair 8 were measured for 8 surrounding neighbors Figure 101 Measurement vs. simulation correlation of IL and RL for center pair (for IT3-32mm) as shown in Figure 100

Signal Integrity Report – IT3 (32mm) Page 62 Figure 102 Measurement vs. simulation correlation of differential S parameters between two nearest neighbors (for IT3-32mm) as shown in Figure 100

Signal Integrity Report – IT3 (32mm) Page 65 Figure 107 IEEE 802.3ap RL spec for center pair 8

5.2.2 Time-Domain NEXT and FEXT

Differential NEXT and FEXT were measured for 8 surrounding neighbors of the center differential pair (see Figure 100) and converted into time-domain data. Figure 108 and Figure 109 show the maximum differential NEXT and FEXT (in %) from each neighbor with step input at 60ps (20% to 80%) rise time with 5.25 GHz bandwidth. The center box corresponds to the absolute sum of NEXT and FEXT from all 8 surrounding pairs. Figure 108 Differential cross-talk (in %) from measurements for step input @ 60ps (20% to 80%) rise time and 5.25GHz BW for center pair 8 and 8 FEXT Figure 109 Differential cross-talk (in %) from measurements for step input @ 60ps (20% to 80%) rise time and 5.25GHz BW for center pair 8 and 8 NEXT

Signal Integrity Report – IT3 (32mm) Page 66 Note: We measured crosstalk values of the inner wafer’s pairs with respect to the center pair and replicated them to the outer column 1.

5.2.3 Impedance profile

From the time domain results, the impedance profile is extracted and compared with simulation results, as shown in Figure 110. Figure 110 Impedance profile comparison between measurements and simulation for center differential pair @60ps rise time (20% to 80%) and 5.25GHz BW

5.3 Single-ended Signals

5.3.1 Measurement vs. Simulation Correlation (connector only) Figure 112 and Figure 113 show the measurement vs. simulation correlation of insertion loss (IL), return loss (RL) and single-ended S parameters (SDD for the center port 15 (as shown in Figure 111). Good correlation was observed for all IL, RL, near-end cross-talk (NEXT), and far-end cross-talk (FEXT). Figure 111 Single-ended NEXT and FEXT for center port 15 were measured for 14 surrounding neighbors Zmea max = 110.55 Ω Zsim max = 105.11 Ω Zsim min = 98.02Ω Zmea max = 98.50 Ω

Signal Integrity Report – IT3 (32mm) Page 67 Figure 112 Measurement vs. simulation correlation of IL and RL for center port (for IT3-32mm) as shown in Figure 111

Signal Integrity Report – IT3 (32mm) Page 68 Figure 113 Measurement vs. simulation correlation of single-ended S parameters (for IT3-32mm) as shown in Figure 111

5.3.2 Time-Domain NEXT and FEXT

Single-ended NEXT and FEXT were measured for 14 surrounding neighbors of the center port (see Figure 111) and converted into time-domain data. Figure 114 and Figure 115 show the maximum single-ended NEXT and FEXT (in %) from each neighbor with step input at 60ps (20% to 80%) rise time with 2.625 GHz bandwidth. The center box corresponds to the absolute sum of NEXT and FEXT from all 14 surrounding ports. Figure 114 Single-ended cross-talk (in %) from measurements for step input @ 120ps (20% to 80%) rise time and 2.625GHz BW for center port 15 and 14 FEXT Figure 115 Single-ended cross-talk (in %) from measurements for step input @ 120ps (20% to 80%) rise time and 2.625GHz BW for center port 15 and 14 NEXT Note: We measured crosstalk values of the inner wafer’s pairs with respect to the center port and replicated them to the outer column 1.

Signal Integrity Report – IT3 (32mm) Page 69

5.3.3 Impedance profile

From the time domain results, the impedance profile is extracted and compared with simulation results, as shown in Figure 116. Figure 116 Impedance profile comparison between measurements and simulation for center port @120ps rise time (20% to 80%) and 2.625GHz BW 6. Appendix Zmea max = 54.43 Ω Zsim max = 52.84 Ω

Signal Integrity Report – IT3 (32mm) Page 71 Figure 118 3-tap transmitter equalization setup