STF5N105K5 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 14
Technical content
Datasheet sections
- 1 Electrical ratings
- 2 Electrical characteristics
- 2.1 Electrical characteristics (curves)
- 3 Test circuits
- 4 Package mechanical data
- 4.1 TO-220FP package mechanical data
- 5 Revision history
Features
Order code VDS RDS(on) max. ID PTOT STF5N105K5 1050 V 3.5 Ω 3 A 25 W Worldwide best FOM (figure of merit) Ultra low gate charge 100% avalanche tested Zener-protected
Applications
Switching applications
Description
This N-channel Zener-protected Power MOSFET is designed using ST’s revolutionary avalanche- rugged very high voltage MDmesh™ K5 technology, based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance, and ultra-low gate charge for applications which require superior power density and high efficiency. Table 1: Device summary Part number Marking Package Packaging STF5N105K5 5N105K5 TO-220FP Tube
1 Electrical ratings
Table 2: Absolute maximum ratings Symbol Parameter Value Unit VGS Gate- source voltage ± 30 V ID Drain current (continuous) at TC = 25 °C 3 (1) A ID Drain current (continuous) at TC = 100 °C 2 (1) A IDM (2) Drain current (pulsed) 12 A PTOT Total dissipation at TC = 25 °C 25 W IAR Max current during repetitive or single pulse avalanche 1 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID=IAS, VDD= 50 V) 85 mJ VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t=1 s; TC=25 °C) 2500 V dv/dt (3) Peak diode recovery voltage slope 4.5 V/ns dv/dt (4) MOSFET dv/dt ruggedness 50 V/ns Tj Operating junction temperature - 55 to 150 °C Tstg Storage temperature Notes: (1)Limited only by maximum junction temperature (2)Pulse width limited by safe operating area. (3)ISD ≤ 3 A, di/dt ≤ 100 A/µs, VDS(peak) ≤ V(BR)DSS (4)VDS ≤ 840 V Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case max 5 °C/W Rthj-amb Thermal resistance junction-amb max 62.5 °C/W
2 Electrical characteristics
(TCASE = 25 °C unless otherwise specified). Table 4: On/off states Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)DSS Drain-source breakdown voltage VGS= 0, ID = 1 mA 1050 V IDSS Zero gate voltage drain current VGS = 0, VDS = 1050 V 1 µA VGS = 0, VDS = 1050 V, Tc=125 °C 50 µA IGSS Gate body leakage current VDS = 0, VGS = ± 20 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA 3 4 5 V RDS(on) Static drain-source on- resistance VGS = 10 V, ID= 1.5 A 2.9 3.5 Ω Table 5: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance VGS=0, VDS =100 V, f=1 MHz - 210 - pF Coss Output capacitance - 16 - pF Crss Reverse transfer capacitance - 0.5 - pF Co(tr)(1) Equivalent capacitance time related VGS = 0, VDS = 0 to 840 V - 26 - pF Co(er)(2) Equivalent capacitance energy related - 10 - pF RG Intrinsic gate resistance f = 1MHz open drain - 9 - Ω Qg Total gate charge VDD = 840 V, ID = 3 A VGS =10 V Figure 16: "Gate charge test circuit" - 12.5 - nC Qgs Gate-source charge - 2 - nC Qgd Gate-drain charge - 9.5 - nC Notes: (1)Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS (2)energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS Table 6: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD = 525V, ID = 1.5 A, RG=4.7 Ω, VGS=10 V Figure 18: " Unclamped inductive load test circuit" - 15.5 - ns tr Rise time - 8.5 - ns td(off) Turn-off delay time - 31 - ns tf Fall time - 24 - ns
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance K 10-4 Tp(s)10-3 10-2 10-1 10010-3 10-2 10-1 GC20940 ID 00 5 VDS(V)10 (A) VGS=10, 11V GIPG290820141204FSR ID 5 7 VGS(V)9 (A) 6 8 10 VDS=20V GIPG290820141334FSR 0 4 82 6 400 200 600 800 Qg(nC) VGS (V) VDS VDS (V) 1200 1210 VDS=840V ID=3A GIPG290820141348FSR RDS(on) 1.5 0 2 ID(A) (Ω) 1 3 VGS=10V 2.5 3.5 GIPG290820141400FSR
0 VDS(V)
(µJ) 400200 600 800 GIPG290820141419FSR Figure 14: Output capacitance stored energy vs temperature
3 Test circuits
Figure 15: Switching times test circuit for resistive load Figure 16: Gate charge test circuit Figure 17: Test circuit for inductive load switching and diode recovery times Figure 18: Unclamped inductive load test circuit Figure 19: Unclamped inductive waveform Figure 20: Switching time waveform
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
4.1 TO-220FP package mechanical data
Figure 21: TO-220FP package outline
Table 9: TO-220FP mechanical data Dim. mm Min. Typ. Max. A 4.4 4.6 B 2.5 2.7 D 2.5 2.75 E 0.45 0.7 F 0.75 F1 1.15 1.70 F2 1.15 1.70 G 4.95 5.2 G1 2.4 2.7 H 10 10.4 L3 28.6 30.6 L4 9.8 10.6 L5 2.9 3.6 L6 15.9 16.4 L7 9 9.3 Dia 3 3.2
5 Revision history
Table 10: Document revision history Date Revision Changes 17-Jul-2014 1 First release. 01-Sep-2014 2 Document status promoted from preliminary to production data. Inserted Section 3.1: "Electrical characteristics (curves)". Minor text changes. 02-Sep-2014 3 Updated title in cover page. 03-Oct-2014 4 Updated: Figure 3: "Thermal impedance", Figure 6: "Gate charge vs gate-source voltage" and Figure 8: "Capacitance variations" 15-Oct-2014 5 Updated Table 2: "Absolute maximum ratings"