1048576

TM124BBK32F TI | Alldatasheet

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TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS649A – DECEMBER 1994 – REVISED JUNE 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Organization TM124BBK32F . . . 1 048 576 × 32 TM248CBK32F . . . 2 097 152 × 32 Single 5-V Power Supply (±10% Tolerance) 72-Pin Single-In-Line Memory Module (SIMM) for Use With Socket TM124BBK32F – Utilizes Two 16-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages TM248CBK32F – Utilizes Four 16-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages Long Refresh Period 16 ms (1024 Cycles) All Inputs, Outputs, Clocks Fully TTL Compatible 3-State Output Common CAS Control for Eight Common Data-In and Data-Out Lines in Four Blocks Enhanced Page-Mode Operation With CAS-Before-RAS (CBR), RAS-Only, and Hidden Refresh Presence Detect Performance Ranges: ACCESS ACCESS ACCESS READ TIME TIME TIME OR tRAC tAA tCAC WRITE CYCLE (MAX) (MAX) (MAX) (MIN) ’124BBK32F-60 60 ns 30 ns 15 ns 110 ns ’124BBK32F-70 70 ns 35 ns 18 ns 130 ns ’124BBK32F-80 80 ns 40 ns 20 ns 150 ns ’248CBK32F-60 60 ns 30 ns 15 ns 110 ns ’248CBK32F-70 70 ns 35 ns 18 ns 130 ns ’248CBK32F-80 80 ns 40 ns 20 ns 150 ns Low Power Dissipation Operating Free-Air Temperature Range 0°C to 70°C Gold-Tabbed Versions Available:† – TM124BBK32F – TM248CBK32F Tin-Lead (Solder) Tabbed Versions Available: – TM124BBK32U – TM248CBK32U

description

The TM124BBK32F is a 32-megabit dynamic random-access memory (DRAM) organized as four times 1048576 × 8 in a 72-pin SIMM. The SIMM is composed of two TMS418160DZ, 1 048 576 × 16-bit DRAMs, each in a 42-lead plastic SOJ package mounted on a substrate with decoupling capacitors. The TMS418160DZ is described in the TMS418160 data sheet. The TM124BBK32F SIMM is available in the single-sided BK-leadless module for use with sockets. TM248CBK32F The TM248CBK32F is a 64-megabit DRAM organized as four times 2 097 152 × 8 in a 72-pin SIMM. The SIMM is composed of four TMS418160DZ, 1 048 576 × 16-bit DRAMs, each in a 42-lead plastic SOJ package mounted on a substrate with decoupling capacitors. The TMS418160DZ is described in the TMS418160 data sheet. The TM248CBK32F SIMM is available in the double-sided BK-leadless module for use with sockets. operation The TM124BBK32F operates as two TMS418160DZs connected as shown in the functional block diagram and Table 1. The TM248CBK32F operates as four TMS418160DZs connected as shown in the functional block † Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions. PRODUCTION DATA information is current as of publication date.

TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS649A – DECEMBER 1994 – REVISED JUNE 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 PRESENCE DETECT SIGNAL (PIN) PD1 (67) PD2 (68) PD3 (69) PD4 (70) 80 ns VSS VSS NC VSS TM124BBK32F 70 ns VSS VSS VSS NC 60 ns VSS VSS NC NC 80 ns NC NC NC VSS TM248CBK32F 70 ns NC NC VSS NC 60 ns NC NC NC NC NC NC CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC W NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS BK SINGLE-IN-LINE MEMORY MODULE (TOP VIEW) TM124BBK32F (SIDE VIEW) PIN NOMENCLATURE A0–A9 Address Inputs CAS0–CAS3 Column-Address Strobe DQ0–DQ31 Data In/Data Out NC No Connection PD1– PD4 Presence Detects RAS0–RAS3 Row-Address Strobe VCC 5-V Supply VSS Ground W Write Enable TM248CBK32F (SIDE VIEW) VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VCC NC NC DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 NC VCC RAS3 RAS2 NC NC VSS

Table 1. Connection Table † Side 2 applies to the TM248CBK32F only.

TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS649A – DECEMBER 1994 – REVISED JUNE 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) – 1 V to 7 V Voltage range on any pin (see Note 1) – 1 V to 7 V Short-circuit output current 50 mA Power dissipation: TM124BBK32F, TM124BBK32U 2 W TM248CBK32F, TM248CBK32U 4 W Operating free-air temperature range, TA 0°C to 70°C Storage temperature range, Tstg – 55°C to 125°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.5 5.5 V VIH High-level input voltage 2.4 6.5 V VIL Low-level input voltage (see Note 2) – 1 0.8 V TA Operating free-air temperature NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS ’124BBK32F-60 ’124BBK32F-70 ’124BBK32F-80 UNIT PARAMETER TEST CONDITIONS MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltage IOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage) VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 5.5 V, VO = 0 V to VCC, CAS high ± 10 ± 10 ± 10 µA ICC1 Read- or write-cycle current VCC = 5.5 V, Minimum cycle 180 160 140 mA ICC2 Standby current VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high mA ICC2 Standby current VIH = VCC – 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high mA ICC3 Average refresh current (RAS only or CBR) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) 180 160 140 mA ICC4 Average page current VCC = 5.5 V, tPC = MIN, RAS low, CAS cycling 180 160 140 mA

TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS649A – DECEMBER 1994 – REVISED JUNE 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)† PARAMETER TEST CONDITIONS ’248CBK32F-60 ’248CBK32F-70 ’248CBK32F-80 UNIT PARAMETER TEST CONDITIONS MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltage IOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leak- age) VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 5.5 V, VO = 0 V to VCC, CAS high ± 20 ± 20 ± 20 µA ICC1 Read- or write-cycle current (see Note 3) VCC = 5.5 V, Minimum cycle 184 164 144 mA ICC2 Standby current VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high mA ICC2 Standby current VIH = VCC – 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high mA ICC3 Average refresh current (RAS only or CBR) (see Note 3) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) 360 320 280 mA ICC4 Average page current (see Note 4) VCC = 5.5 V, tPC = MIN, RAS low, CAS cycling 184 164 144 mA † For test conditions shown as MIN/MAX, use the appropriate value specified under recommended operating conditions. NOTES: 3. Measured with a maximum of one address change while RAS = VIL Measured with a maximum of one address change while CAS = VIH capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 5) PARAMETER ’124BBK32F ’248CBK32F UNIT PARAMETER MIN MAX MIN MAX UNIT Ci(A) Input capacitance, A0–A9 pF Ci(R) Input capacitance, RAS inputs pF Ci(C) Input capacitance, CAS inputs pF Ci(W) Input capacitance, W pF Co(DQ) Output capacitance on DQ0–DQ31 pF NOTE 5: VCC = 5 V ± 0.5 V, and the bias on pins under test is 0 V.

TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS649A – DECEMBER 1994 – REVISED JUNE 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER ’124BBK32F-60 ’248CBK32F-60 ’124BBK32F-70 ’248CBK32F-70 ’124BBK32F-80 ’248CBK32F-80 UNIT MIN MAX MIN MAX MIN MAX tAA Access time from column address ns tCAC Access time from CAS low ns tRAC Access time from RAS low ns tCPA Access time from column precharge ns tCLZ CAS to output in low-impedance state ns tOH Output disable time from start of CAS high ns tOFF Output disable time after CAS high (see Note 6) ns NOTE 6: tOFF is specified when the output is no longer driven. timing requirements over recommended ranges of supply voltage and operating free-air temperature ’124BBK32F-60 ’248CBK32F-60 ’124BBK32F-70 ’248CBK32F-70 ’124BBK32F-80 ’248CBK32F-80 UNIT MIN MAX MIN MAX MIN MAX tRC Cycle time, random read or write (see Note 7) 110 130 150 ns tRWC Cycle time, read-write 155 181 205 ns tPC Cycle time, page-mode read or write (see Notes 7 and 8) ns tRASP Pulse duration, page mode, RAS low 100 000 100 000 100 000 ns tRAS Pulse duration, nonpage mode, RAS low 10 000 10 000 10 000 ns tCAS Pulse duration, CAS low 10 000 10 000 10 000 ns tCP Pulse duration, CAS high ns tRP Pulse duration, RAS high (precharge) ns tWP Pulse duration, W low ns tASC Setup time, column address before CAS low ns tASR Setup time, row address before RAS low ns tDS Setup time, data before CAS low ns tRCS Setup time, W high before CAS low ns tCWL Setup time, W low before CAS high ns tRWL Setup time, W low before RAS high ns tWCS Setup time, W low before CAS low ns tWRP Setup time, W high before RAS low (CBR refresh only) ns tCAH Hold time, column address after CAS low ns tRHCP Hold time, RAS high from CAS precharge ns tDH Hold time, data after CAS low ns tRAH Hold time, row address after RAS low ns tRCH Hold time, W high after CAS high (see Note 9) ns tRRH Hold time, W high after RAS high (see Note 9) ns NOTES: 7. All cycles assume tT = 5 ns. To assure tPC min, tASC should be ≥ tCP. Either tRRH or tRCH must be satisfied for a read cycle.

TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS649A – DECEMBER 1994 – REVISED JUNE 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued) ’124BBK32F-60 ’248CBK32F-60 ’124BBK32F-70 ’248CBK32F-70 ’124BBK32F-80 ’248CBK32F-80 UNIT MIN MAX MIN MAX MIN MAX tWCH Hold time, W low after CAS low ns tWRH Hold time, W high after RAS low (CBR refresh only) ns tCHR Delay time, RAS low to CAS high (CBR refresh only) ns tCRP Delay time, CAS high to RAS low ns tCSH Delay time, RAS low to CAS high ns tCSR Delay time, CAS low to RAS low (CBR refresh only) ns tRAD Delay time, RAS low to column address (see Note 10) ns tRAL Delay time, column address to RAS high ns tCAL Delay time, column address to CAS high ns tRCD Delay time, RAS low to CAS low (see Note 10) ns tRPC Delay time, RAS high to CAS low (CBR only) ns tRSH Delay time, CAS low to RAS high ns tREF Refresh time interval ms tT Transition time ns NOTE 10: The maximum value is specified only to assure access time. device symbolization (TM124BBK32F illustrated) TM124BBK32F -SS YYMMT YY = Year Code MM = Month Code T = Assembly Site Code -SS = Speed Code NOTE: Location of symbolization may vary.

TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS649A – DECEMBER 1994 – REVISED JUNE 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

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