STSJ100NHS3LL STMICROELECTRONICS | Alldatasheet

Document overview

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  • PDF pages: 12

Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuit
  • 4 Package mechanical data
  • 5 Revision history

N-channel 30V - 0.0032Ω - 20A - PowerSO-8™ STripFET™III Power MOSFET plus monolithic schottky General features ■ Optimal RDS(on) x Qg trade-off @ 4.5V ■ Reduced switching losses ■ Reduced conduction losses ■ Improved junction-case thermal resistance

Description

This product utilizes the latest advanced design rules of ST’s proprietary STripFET™ technology and a propriertary process for integrating a monolithic scottky diode. The new Power MOSFET is optimized for the most demanding synchronous switch function in DC-DC converter for Computer and Telecom.

Applications

■ Switching application Internal schematic diagram Type V DSS RDS(on) ID STSJ100NHS3LL 30V 0.0042 Ω 20A(1) 1. This value is rated accordingly to Rthj-pcb PowerSO-8 Order codes Part number Marking Package Packaging STSJ100NHS3LL 100HS3L- PowerSO-8 Tape & reel

1 Electrical ratings

Table 1. Absolute maximum ratings

  1. This value is rated accordingly to Rthj-pcb
  2. This value is rated according to Rthj-c
  3. Pulse width limited by safe operating area

Table 2. Thermal data

  1. When mounted on 1 inch² FR-4 board, 2oz Cu (t<10sec.)

Table 3. Avalanche data

2 Electrical characteristics

Table 4. On/off states Table 5. Dynamic

  1. Pulsed: pulse duration=300µs, duty cycle 1.5%

Table 6. Switching times Table 7. Source drain diode

  1. Pulse width limited by safe operating area
  2. Pulsed: pulse duration=300µs, duty cycle 1.5%

2.1 Electrical characteris tics (curves)

Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Normalized B VDSS vs temperature Figure 6. Static drain-source on resistance

3 Test circuit

Figure 12. Switching times test circuit for Figure 13. Gate charge test circuit Figure 14. Test circuit for inductive load Figure 15. Unclamped inductive load test Figure 16. Unclamped inductive wavefo rm Figure 17. Switching time waveform

STSJ100NHS3LL Packag e mechanical data

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at : www.st.com

DIM. mm. inch A 1.75 0.068 a1 0.1 0.25 0.003 0.009 a2 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.019 c1 45° (typ.) D 4.8 5.0 0.188 0.196 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 e4 2.79 0.110 F 3.8 4.0 0.14 0.157 L 0.4 1.27 0.015 0.050 M0 . 6 0 . 0 2 3 S8 ° ( m a x . ) PowerSO-8™ MECHANICAL DATA

5 Revision history

Table 8. Revision history 13-Jan-2006 1 Initial release.