100311QC

100311 FAIRCHILD | Alldatasheet

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I Low output-to-output skew I 2000V ESD protection I 1:9 low skew clock driver I Differential inputs and outputs I Available to industrial grade temperature range (PLCC package only) Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Connection Diagram 28-Pin PLCC Truth Table Order Number Package Number Package Description 100311QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100311QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Pin Names Description CLKIN, CLKIN Differential Clock Inputs EN Enable CLK 0–8, CLK0–8 Differential Clock Outputs VBB VBB Output NC No Connect CLKIN CLKIN EN CLK n CLK n LHLLH HLLHL XXHLH

www.fairchildsemi.com 2 100311 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho- sen to guarantee operation under “worst case” conditions. Storage Temperature (TSTG ) −65°C to +150°C Maximum Junction Temperature (TJ) +150°C Pin Potential to Ground Pin (VEE ) −7.0V to +0.5V Input Voltage (DC) V EE to +0.5V Output Current (DC Output HIGH) −50 mA ESD (Note 2) ≥2000V Case Temperature (TC ) Commercial 0 °C to +85°C Industrial −40°C to +85°C Supply Voltage (VEE ) −5.7V to −4.2V Symbol Parameter Min Typ Max Units Conditions VOH Output HIGH Voltage −1025 −955 −870 mV V IN = VIH (Max) Loading with VOL Output LOW Voltage −1830 −1705 −1620 mV or V IL (Min) 50 Ω to −2.0V VOHC Output HIGH Voltage −1035 mV V IN = VIH Loading with VOLC Output LOW Voltage −1610 mV or V IL (Max) 50 Ω to −2.0V VBB Output Reference Voltage −1380 −1320 −1260 mV I VBB = −300 µA VDIFF Input Voltage Differential 150 mV Required for Full Output Swing VCM Common Mode Voltage V CC − 2.0 V CC − 0.5 V VIH Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal for All Inputs VIL Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal for All Inputs IIL Input LOW Current 0.50 µAV IN = VIL (Min) IIH Input HIGH Current V IN = VIH (Max) CLKIN, CLKIN 100 µA EN 250 ICBO Input Leakage Current −10 µAV IN = VEE IEE Power Supply Current −115 −57 mA Inputs Open

3 www.fairchildsemi.com 100311 Commercial Version (Continued) VEE = −4.2V to −5.7V, VCC = VCCA = GND Note 4: fMAX = the highest frequency at which output VOL /VOH levels still meet VIN specifications. The F311 will function @ 1 GHz. Note 5: tPS describes opposite edge skews, i.e. the difference between the delay of a differential output signal pair’s LOW-to-HIGH and HIGH-to-LOW prop- agation delays. With differential signal pairs, a LOW-to-HIGH or HIGH-to-LOW transition is defined as the transition of the true output or input pin. Note 6: tOSLH describes in-phase gate-to-gate differential propagation skews with all differential outputs going LOW-to-HIGH; tOSHL describes the same con- ditions except with the outputs going HIGH-to-LOW. Note 7: tOST describes the maximum worst case difference in any of the tPS , tOSLH or tOST delay paths combined. Note 8: The skew specifications pertain to differential I/O paths. Industrial Version VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C Symbol Parameter TC = 0°CT C = +25°CT C = +85°C Units Conditions Min Typ Max Min Typ Max Min Typ Max fMAX Max Toggle Frequency 750 750 750 MHz (Note 4) CLKIN to Qn tPLH Propagation Delay, tPHL CLKIN n to CLKn tPHL SEL to Output tPS LH –HL Skew 10 30 10 30 10 30 ps (Note 5)(Note 8) tOSLH Gate–Gate Skew LH 20 50 20 50 20 50 (Note 6)(Note 8) tOSHL Gate–Gate Skew HL 20 50 20 50 20 50 (Note 6)(Note 8) tOST Gate–Gate LH–HL Skew 30 60 30 60 30 60 (Note 7)(Note 8) tS Setup Time 250 250 300 ps EN n to CLKINn tH H o l d T i m e 000 p s EN n to CLKINn tR Release Time 300 300 300 ps EN n to CLKINn tTLH Transition Time 275 500 750 275 480 750 275 460 750 ps Figure 4 tTHL 20% to 80%, 80% to 20% Symbol Parameter TC = −40°CT C = 0°C to +85°C Units Conditions Min Max Min Max VOH Output HIGH Voltage −1085 −870 −1025 −870 mV V IN = VIH (Max) Loading with VOL Output LOW Voltage −1830 −1575 −1830 −1620 mV or V IL (Min) 50 Ω to −2.0V VOHC Output HIGH Voltage −1095 −1035 mV V IN = VIH Loading with VOLC Output LOW Voltage −1565 −1610 mV or V IL (Min) 50 Ω to −2.0V VBB Output Reference Voltage −1395 −1255 −1380 −1260 mV I VBB = −300 µA VDIFF Input Voltage Differential 150 150 mV Required for Full Output Swing VCM Common Mode Voltage V CC − 2.0 VCC − 0.5 VCC − 2.0 VCC − 0.5 V VIH Input HIGH Voltage −1170 −870 −1165 −870 mV Guaranteed HIGH Signal for All Inputs

www.fairchildsemi.com 4 100311 Industrial Version (Continued) VEE = −4.2V to −5.7V, VCC = VCCA = GND Note 9: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho- sen to guarantee operation under “worst case” conditions. VEE = −4.2V to −5.7V, VCC = VCCA = GND Note 10: fMAX = the highest frequency of which output VOL /VOH levels still meet VIN specifications. The F311 will function @ 1 GHz Note 11: tPS describes opposite edge skews, i.e. the difference between the delay of a differential output signal pair's LOW-to-HIGH and HIGH-to-LOW prop- agation delays. With differential signal pairs, a LOW-to-HIGH or HIGH-to-LOW transition is defined as the transition of the true output or input pin. Note 12: tOSLH describes in-phase gate differential propagation skews with all differential outputs going LOW-to-HIGH; tOSHL describes the same conditions except with the outputs going HIGH-to-LOW. Note 13: tOST describes the maximum worst case difference in any of the tPS , tOSLH or tOST delay paths combined. Note 14: The skew specifications pertain to differential I/O paths. Symbol Parameter TC = −40°CT C = 0°C to +85°C Units Conditions Min Max Min Max VIL Input LOW Voltage −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal for All Inputs IIL Input LOW Current 0.50 0.50 µAV IN = VIL (Min) IIH Input HIGH Current V IN = VIH (Max) CLKIN, CLKIN 100 100 µA EN 250 250 ICBO Input Leakage Current −10 −10 µAV IN = VEE IEE Power Supply Current −115 −57 −115 −57 mA Inputs Open VPP Minimum Input Swing 150 150 mV VCMR Common Mode Range V CC −2.0 V CC −0.5 V CC −2.0 V CC −0.5 V Symbol Parameter TC = −40°CT C = +25°CT C = +85°C Units Conditions Min Typ Max Min Typ Max Min Typ Max fMAX Max Toggle Frequency 750 750 750 MHz (Note 10) CLKIN to Q n tPLH Propagation Delay, tPHL CLKIN n to CLKn tPHL SEL to Output tPS LH –HL Skew 10 30 10 30 10 30 (Note 11)(Note 14) tOSLH Gate–Gate Skew LH 20 50 20 50 20 50 ps (Note 12)(Note 14) tOSHL Gate–Gate Skew HL 20 50 20 50 20 50 (Note 12)(Note 14) tOST Gate–Gate LH–HL Skew 30 60 30 60 30 60 (Note 13)(Note 14) tS Setup Time 250 250 300 ps EN n to CLKINn tH Hold Time 0 0 0 ps EN n to CLKINn tR Release Time 300 300 300 ps EN n to CLKINn tTLH Transition Time 275 500 750 275 480 750 275 460 750 ps Figure 4 tTHL 20% to 80%, 80% to 20%

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100311 Low Skew 1:9 Differential Clock Driver

Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com