10010

F10016 FAIRCHILD | Alldatasheet

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F10010'* F10016” GENERAL DESCRIPTION — The F 10010 is a high-speed synchronous, presettable, Loaic SYMBOL cascadable BCD Decade Counter and the F10016 is a high-speed synchronous, pre- settable, cascadable 4-Bit Binary Counter. They are multifunction MSI building blocks useful for a large number of counting, digital integration, and conversion applications. Up to nine devices can be cascaded with no speed degradation using standard 10K gates. A multidecade synchronous counter up to 150 MHz can be built, Typical count frequency is 200 MHz Features include assertion inputs and outputs on each of the four master/slave suas wos counting flip-flops. Terminal count is generated internally in a manner that allows oy en synchronous loading at nearly the speed of the basic counter. PEP Py Pa Pa we—ojoe™ BINARY COUNTERTC[O— 4 (# @ HIGH SPEED COUNT... 200 MHz TYPICAL COUNT FREQUENCY nr Cha °. ‘© INTERNAL COUNT ENABLE—FOR HIGHEST SPEED EXPANSION ae 8 © ASYNCHRONOUS MASTER RESET 200 ne ae ‘© 50 DRIVE CAPABILITY ‘© WIRED-OR CAPABILITY @ SEPARATE Vcc PINS—ELIMINATE NOISE COUPLING ‘© INTERNAL 50 k@ INPUT PULL DOWNS, @ SINGLE -5.2 V POWER SUPPLY Voct=1 (6) Voce= 16 4) Vee=8 (12) (= Flatpak PIN NAMES CONNECTION DIAGRAM PE Parallel Load Enable (Active LOW) DIP (TOP VIEW) PACKAGE OUTLINE 68 Ph Parallel Inputs cP Clock Input (Clocks on Positive Transition) cE Count Enable (LOW to Count) MR Master Reset (HIGH Forces all Q Outputs LOW) Te Terminal Count (10010, LOW at HLLH; 10016 LOW at HHHH) Yea 1 vcce Qn Counter Outputs a [] o2 % [J °% re [] ce Cael D1 wn eq tL] °s Pol) [J P2 ve Q] He 712

FAIRCHILD ECL DATASHEET © F10010 « F10016 LOGIC DIAGRAM F10010 — — — — . oe mi FIC ———- 3 ag, ELE : wesrer eo gwel |, une aw | Illy ame ae PUD a> + . D) . te pete iB © e faa lates fo ot (“io Tose : oe | | (se A | { it + + i a a T® oo —_ ! - Lp-x} Lene. a ipa LOGIC DIAGRAM F10016 Lo >] __ I | a | 29) _ a Te Jone masre a AVE, i ° ee 25 0B ae bts pasren a auve | | _ gaat J To _ Bebe ott pitts = [Slto = im: siLois { ED _ Sele 2 | or. OB2tp ss Lo! o “Tio oA PH T : i T wn [i s rt jf a 8 ot - — : — re “noepenerene Note that this diagram is provided for understanding of logic operation only. It should not be used for valuation of propaga tion delays as many gate functions are achieved internally without incurring a full gate delay, FUNCTIONAL DESCRIPTION — The F10010 is a high-speed BCD Decade Counter and the F10016 is a high-speed Binary Counter. The four master/slave flip-flops are fully synchronous and are driven in parallel through a clock driver. The masters are loaded during the LOW period of the clock pulse. During the LOW to HIGH transition of the clock, the master is disabled from the input and data is transferred to the slaves and then to the outputs. When the clock is. HIGH, the masters are inhibited from changing and the master/slave data path remains open. During the HIGH to LOW transition of the clock, the master/slave data path is inhibited, followed by the enabling of the masters for the acceptance of Inputs from the counting logic, parallel entry, or count hold logic. The Terminal Count (TC) is generated at count 9 (HLLH) on the 10010 and at count 15 (HHHH) on the 10016. The TC output is available simultaneously with the Q outputs through the use of unique lookahead logic and a fifth slave which i loaded during the LOW gorton of the clock cycte. Tis feature In conjunction withthe triggered Count Enable (CE) and the Parallel Enable (PE) select the mode of operation as shown in the table next page. The status of these control lines is sampled only during the LOW to HIGH transition of the clock. The Master Reset (MR) function is asynchronous. When HIGH, It overrides all other commands and forces all Q out- puts LOW and the TC HIGH. 7-13

FAIRCHILD ECL DATASHEET © F10010 * F10016 TRUTH TABLE (ee [we [clr | L L L Z_ | Load Parallel (Pp to Qn) Letow H L L Z | Load Parallel (Pp to Qn) H=HIGH Voltage Level . 4 7 2 | Count 2 clock Pulse (LOW to HIGH) Hq 4 t z Hold ZZ = Clock Pulse (HIGH to LOW) x x L ZZ | Masters Respond; Slaves Hold x x H X | Reset (Qq=LOW, TC = HIGH) STATE DIAGRAMS F10010 F10016 C-O+-2FEEE C}+-0}-2-G+-4) bg ) fg (3) mo a) i IG 5) a) te) 4 o-) -f) -E--E-L) NOTE: The 10010 can be preset to any state, but will not count beyond @ (HLLH). It preset to state 10, 11, 12, 19, 14 or 15, it will return to its normal sequence within two clock pulses. DC CHARACTERISTICS: Veg = - 5.2 V, Voc = GND SYMBOL CHARACTERISTIC ee [A | UNITS: CONDITIONS WH Input Current HIGH 265 | yA | 25°C ViN=VIHA MR (Pin 12) 700 lee Power Supply Current - 115 Outputs Open, Pin 12 Tied to Vi 114

FAIRCHILD ECL DATASHEET © F10010 © F10016 ‘SWITCHING CHARACTERISTICS: Veg = -5.2 V, Ta =25°C SYMBOL CHARACTERISTIC LIMITS UNITS: CONDITIONS pe [we pa | foount | Count Frequency zo | | Mme See Figure 1 tPLH Propagation Delay 36 ns Clock to Output (Qn of TC) tPHL Propagation Delay 50 ns See Figure 2 Clock to Output (Qp or T) {PHL Propagation Delay ns See Figure 3 Master Reset to Output ‘TLH Output Transition Time 13 33 as LOW to HIGH (20% to 80%) {THLE Output Transition Time 1.3 3.3 ns See Figure 2 HIGH to LOW (80% to 20%) ts Set-Up Time Prior to Clock Pp to CP th Hold Time After Clock ns Pp tocP ts ‘Set-Up Time Prior to Clock ns PE or CE to CP th Hold Time After Clock PE or CE to CP SWITCHING CIRCUITS AND WAVEFORMS memes gree coos teeta. R29 a1 07 03"°] we: ™ m Fe ee Tie, SEI weseune cxsex wet - | | soars | ser Ly and = equal tength $0 8impedance ines y= 509 terminationof scope CL =Jigand stray capacitance <6.0pF eon Decoupling 1 uF from gndto Vee and Voc, ‘ours ron wee romaibomuchy tour=iifron vee Vee -32V our Fig.1. Maximum Count Frequency aac

FAIRCHILD ECL DATASHEET ¢ F10010 © F10016 SWITCHING CIRCUITS AND WAVEFORMS (Cont'd) Yee rus ? Es 5 = [ss | - I ES 070 PHP velo i celo— Tome o 002 w= 10m HR 45 04 09 a37° “=| — fe tase fa ay

7 Fr tom ri mu

ogonveourrur = ea a 2 | Len | tm, LyandLg= equal lengthS0@impedancelines Decoupling 0.1 uF from gn to Vee and Veg Fy =509 termination of scope Voot=Voo2=20¥ C= Jig and stray capacitance <6.0 pF Vee= -32V Fig.2. Clock toOutput Yoo Es os i 100 te ES ie « . cefo rer 0 19 ‘wit = 108 MP 09.01 02 05" = 202020 nwt oa as Ly and La = equal length 502 impedance lines = i Fy =502 termination of scope -— wats ——-} | =digand stray capacitance <5.0 pF mb Decoupling 0.1 uF from gnd to Vee and Veg Ne lo Voo1=Voc2=20V gournt K om Vee= ~32V wl Fig.3. Master Reset to Output eae

FAIRCHILD ECL DATASHEET ¢ F10010 ¢ F10016

APPLICATION INFORMATION

RaTio_| po Pr {21 P3 Procnannaaste a = [see fa a 2 a nance —ofoe™ "0 7192 a a oie | 2 SREB A Po Peete i an oc ce 14 cpe pot ic chet fe The F10016 may be connected to divide by any modulo from 2 to 16. The table illustrates the inputs required for each modulo. The terminal count output is utilized to load the parallel data, this in turn determines the number of clock pulses which will occur before TC goes LOW again. 4 a Lb m | te Lu 4 Le tu u LL | FP du 7 1 L Tee Par Pars so riot ref rv rofo a rroos refo roe ref Fun 09 04 02 Os SFR Op 0% Oe Oy ‘SFR_Op 0% 02 O3 Fun 09 03 2 03 SFun_09 04 02 23 ‘CASCADE COUNTERS USING OR GATES FOR CARRY PROPAGATION