0832CCN

ADC0832CCN TI1 | Alldatasheet

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ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N www.ti.com SNAS531B –AUGUST 1999–REVISED MARCH 2013 ADC0831-N/ADC0832-N/ADC0834-N/ADC0838-N8-BitSerialI/OA/DConverterswith MultiplexerOptions Check forSamples: ADC0831-N ,ADC0832-N ,ADC0834-N ,ADC0838-N 1FEATURES KEY SPECIFICATIONS 2• TIMICROWIRE Compatible— DirectInterfaceto • Resolution:8 Bits COPS FamilyProcessors • TotalUnadjusted Error:±½ LSB and ±1 LSB

• Easy InterfacetoAllMicroprocessors,or • SingleSupply:5 VDC Operates “Stand-Alone” • Low Power: 15 mW
• Operates Ratiometricallyor with5 VDC Voltage • Conversion Time: 32 μsReference
• No Zero or Full-ScaleAdjustRequired DESCRIPTION
• 2-,4-or 8-ChannelMultiplexerOptions with The ADC0831 series are 8-bit successive Address Logic approximationA/D converterswitha serialI/O and configurableinputmultiplexerswithup to8 channels.• Shunt RegulatorAllows OperationwithHigh The serialI/O is configuredto comply withthe TIVoltageSupplies MICROWIRE serialdataexchange standardforeasy• 0V to5V InputRange withSingle5V Power interfacetotheCOPS familyofprocessors,and can Supply interfacewithstandardshiftregistersorμPs.
• Remote OperationwithSerialDigitalData Link The 2-,4- or 8-channelmultiplexersare software
• TTL/MOS Input/OutputCompatible configuredforsingle-endedor differentialinputsas wellas channelassignment.• 0.3in.Standard Width,8-,14-or 20-PinPDIP Package The differentialanalogvoltageinputallowsincreasing
• 20 Pin PLCC Package (ADC0838-N Only) thecommon-mode rejectionand offsettingtheanalog zero inputvoltagevalue.In addition,the voltage• SOIC Package referenceinputcan be adjustedto allowencoding any smalleranalogvoltagespan to the full8 bitsof resolution. TypicalApplication Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 1999–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N SNAS531B –AUGUST 1999–REVISED MARCH 2013 www.ti.com Connection Diagrams Figure4. ADC0831-N SingleDifferentialInput Figure1. ADC0838-N 8-ChannelMux SOIC/PDIP Package (DW or NFH) Top View COM internallyconnectedtoGND. VREF internallyconnectedtoVCC . Top View Figure5. ADC0832-N 2-ChannelMUX PDIP Package (P)Top View Figure2. ADC0832-N 2-ChannelMUX Figure6. ADC0831-N SingleDifferentialInput COM internallyconnectedtoA GND Top View Figure3. ADC0834-N 4-ChannelMUX SOIC/PDIP (NPA or NFF) Top View Figure7. ADC0838-N 8-ChannelMUX These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates.

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ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N www.ti.com SNAS531B –AUGUST 1999–REVISED MARCH 2013 AbsoluteMaximum Ratings(1)(2)(3) CurrentintoV+ (4) 15 mA SupplyVoltage,VCC (4) 6.5V LogicInputs −0.3VtoVCC + 0.3V Voltage AnalogInputs −0.3VtoVCC + 0.3V Pin(5) ±5 mA InputCurrentper Package ±20 mA StorageTemperature −65°C to+150°C Package Dissipation atTA = 25°C (BoardMount) 0.8W Lead Temperature(Soldering10 sec.) PDIP Package 260°C Vapor Phase (60sec.) 215°C Infrared(15sec.) 220°C ESD Susceptibility(6) 2000V (1) Allvoltagesaremeasured withrespecttothegroundplugs. (2) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.DC and AC electricalspecificationsdo not applywhen operatingthedevicebeyond itsspecifiedoperatingconditions. (3) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. (4) Internalzenerdiodes(6.3to8.5V)areconnectedfromV+ toGND and VCC toGND. The zeneratV+ can operateas a shuntregulator and isconnectedtoVCC viaa conventionaldiode.SincethezenervoltageequalstheA/D's breakdown voltage,thediodeinsuresthat VCC willbe belowbreakdown when thedeviceispowered fromV+. FunctionalityisthereforeensuredforV+ operationeven thoughthe resultantvoltageatVCC may exceed thespecifiedAbsoluteMax of6.5V.Itisrecommended thata resistorbe used tolimitthemax currentintoV+. (See Figure24 inFunctionalDescription) (5) When theinputvoltage(VIN)atany pinexceedsthepower supplyrails(VIN < V− orVIN > V+)theabsolutevalueofcurrentatthatpin shouldbe limitedto5 mA orless.The 20 mA package inputcurrentlimitsthenumber ofpinsthatcan exceed thepower supply boundarieswitha 5 mA currentlimittofour. (6) Human body model,100 pF dischargedthrougha 1.5kΩ resistor. OperatingRatings(1)(2) SupplyVoltage,VCC 4.5VDC to6.3VDC ADC0832/8CIWM ADC0834BCN, ADC0838BCV, −40°C to+85°CADC0831/2/4/8CCN,ADC0838CCVTemperatureRange (TMIN ≤ TA ≤ TMAX ) ADC0831/2/4/8CCWM 0°C to+70°C (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.DC and AC electricalspecificationsdo not applywhen operatingthedevicebeyond itsspecifiedoperatingconditions. (2) Allvoltagesaremeasured withrespecttothegroundplugs. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:ADC0831-N ADC0832-N ADC0834-N ADC0838-N

ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N SNAS531B –AUGUST 1999–REVISED MARCH 2013 www.ti.com Converterand MultiplexerElectricalCharacteristics The followingspecificationsapplyforVCC = V+ = VREF = 5V,VREF ≤ VCC +0.1V,TA = Tj= 25°C, and fCLK = 250 kHz unless otherwisespecified.Boldfacelimitsapplyfrom TMIN toTMAX . BCV, CCV, CCWM, BCNCIWM Devices and CCN Devices Parameter Conditions Units Tested Design Tested DesignTyp (1) Typ (1) Limit(2) Limit(3) Limit(2) Limit(3) CONVERTER AND MULTIPLEXER CHARACTERISTICS ADC0838BCV ±½ ±½ ADC0834BCN ±½ ±½ Total ADC0838CCV ±1 ±1 Unadjusted VREF = 5.00V (4) LSB (Max) ADC0831/2/4/8CCN ±1 ±1Error ADC0831/2/4/8CCWM ±1 ±1 ADC0832/8CIWM ±1 Maximum Common-Mode Input VCC VCC VCC +0.05 VRange (6) +0.05 +0.05 Minimum Common-Mode Input GND GND GND VRange (6) −0.05 −0.05 −0.05 DC Common-Mode Error ±1/16 ±¼ ±1/16 ±¼ ±¼ LSB 15 mA intoV+, VCC =Change inzeroerrorfromVCC =5V N.C., 1 1 1 LSBtointernalzeneroperation(7) VREF = 5V VZ,internaldiode MIN 15 mA intoV+ 6.3 6.3 6.3 breakdown (atV+)(7) MAX 8.5 8.5 8.5 V Power SupplySensitivity VCC = 5V ± 5% ±1/16 ±¼ ±¼ ±1/16 ±¼ ±¼ LSB On Channel= 5V −0.2 −0.2 −1 μA OffChannel= 0V −1IOFF ,OffChannelLeakage Current(8) On Channel= 0V +0.2 +0.2 +1 μA OffChannel= 5V +1 On Channel= 0V −0.2 −0.2 −1 μA OffChannel= 5V −1 ION ,On ChannelLeakage Current(8) On Channel= 5V +0.2 +0.2 +1 μA OffChannel= 0V +1 (1) Typicalsareat25°C and representmost likelyparametricnorm. (2) TestedlimitsareensuredtoTI's AOQL (AverageOutgoingQualityLevel). (3) Ensuredbutnot100% productiontested.These limitsarenotused tocalculateoutgoingqualitylevels. (4) Totalunadjustederrorincludesoffset,full-scale,linearity,and multiplexererrors. (5) Cannot be testedforADC0832-N. (6) ForVIN(−)≥ VIN(+)thedigitaloutputcode willbe 0000 0000.Two on-chipdiodesaretiedtoeach analoginput(seeFunctionalBlock Diagram)whichwillforwardconductforanaloginputvoltagesone diodedropbelowgroundorone diodedropgreaterthantheVCC supply.Be careful,duringtestingatlowVCC levels(4.5V),as highlevelanaloginputs(5V)can cause thisinputdiodeto conduct— especiallyatelevatedtemperatures,and cause errorsforanaloginputsnearfull-scale.The spec allows50 mV forwardbiasof eitherdiode.Thismeans thatas longas theanalogVIN orVREF does notexceed thesupplyvoltageby more than50 mV, theoutput code willbe correct.To achievean absolute0 VDC to5 VDC inputvoltagerangewillthereforerequirea minimum supplyvoltageof4.950 VDC overtemperaturevariations,initialtoleranceand loading. (7) Internalzenerdiodes(6.3to8.5V)areconnectedfromV+ toGND and VCC toGND. The zeneratV+ can operateas a shuntregulator and isconnectedtoVCC viaa conventionaldiode.SincethezenervoltageequalstheA/D's breakdown voltage,thediodeinsuresthat VCC willbe belowbreakdown when thedeviceispowered fromV+. FunctionalityisthereforeensuredforV+ operationeven thoughthe resultantvoltageatVCC may exceed thespecifiedAbsoluteMax of6.5V.Itisrecommended thata resistorbe used tolimitthemax currentintoV+. (See Figure24 inFunctionalDescription) (8) Leakage currentismeasured withtheclocknotswitching.

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ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N www.ti.com SNAS531B –AUGUST 1999–REVISED MARCH 2013 Converterand MultiplexerElectricalCharacteristics(continued) The followingspecificationsapplyforVCC = V+ = VREF = 5V,VREF ≤ VCC +0.1V,TA = Tj= 25°C, and fCLK = 250 kHz unless otherwisespecified.Boldfacelimitsapplyfrom TMIN toTMAX . BCV, CCV, CCWM, BCNCIWM Devices and CCN Devices Parameter Conditions Units Tested Design Tested DesignTyp (1) Typ (1) Limit(2) Limit(3) Limit(2) Limit(3) DIGITAL AND DC CHARACTERISTICS VIN(1),Logical“1”InputVoltage(Min) VCC = 5.25V 2.0 2.0 2.0 V VIN(0),Logical“0”InputVoltage VCC = 4.75V 0.8 0.8 0.8 V(Max) IIN(1),Logical“1”InputCurrent(Max) VIN = 5.0V 0.005 1 0.005 1 1 μA IIN(0),Logical“0”InputCurrent(Max) VIN = 0V −0.00−0.005 −1 −1 −1 μA5 VCC = 4.75V VOUT(1),Logical“1”OutputVoltage IOUT = −360 μA 2.4 2.4 2.4 V(Min) IOUT = −10 μA 4.5 4.5 4.5 V IOUT ,TRI-STATE OutputCurrent VOUT = 0V −0.1 −3 −0.1 −3 −3 μA (Max) VOUT = 5V 0.1 3 0.1 +3 +3 μA ISOURCE ,OutputSourceCurrent VOUT = 0V −14 −6.5 −14 −7.5 −6.5 mA(Min) ISINK,OutputSinkCurrent(Min) VOUT = VCC 16 8.0 16 9.0 8.0 mA Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:ADC0831-N ADC0832-N ADC0834-N ADC0838-N

ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N SNAS531B –AUGUST 1999–REVISED MARCH 2013 www.ti.com AC Characteristics The followingspecificationsapplyforVCC = 5V,tr = tf = 20 ns and 25°C unlessotherwisespecified. Tested Design LimitParameter Conditions Typ (1) Limit(2) Limit(3) Units Min 10 kHz fCLK ,ClockFrequency Max 400 kHz tC ,ConversionTime Not includingMUX AddressingTime 8 1/fCLK Min 40 % ClockDutyCycle(4) Max 60 % tSET-UP ,CS FallingEdge orData InputValid 250 nstoCLK RisingEdge tHOLD ,Data InputValidafterCLK Rising 90 nsEdge C L=100 pF tpd1,tpd0— CLK FallingEdge toOutputData Data MSB First 650 1500 nsValid(5) Data LSB First 250 600 ns C L=10 pF,R L=10k (See TRI-STATE 125 250 nst1H ,t0H ,— RisingEdge ofCS toData Output TestCircuitsand Waveforms) and SARS Hi–Z C L=100 pf,R L=2k 500 ns C IN,CapacitanceofLogicInput 5 pF C OUT ,CapacitanceofLogicOutputs 5 pF (1) Typicalsareat25°C and representmost likelyparametricnorm. (2) TestedlimitsareensuredtoTI's AOQL (AverageOutgoingQualityLevel). (3) Ensuredbutnot100% productiontested.These limitsarenotused tocalculateoutgoingqualitylevels. (4) A 40% to60% clockdutycyclerangeinsuresproperoperationatallclockfrequencies.Inthecase thatan availableclockhas a duty cycleoutsideoftheselimits,theminimum, timetheclockishighortheminimum timetheclockislowmust be atleast1 μs.The maximum timetheclockcan be highis60 μs.The clockcan be stoppedwhen lowso longas theanaloginputvoltageremainsstable. (5) Sincedata,MSB first,istheoutputofthecomparatorused inthesuccessiveapproximationloop,an additionaldelayisbuiltin(see ADC0838-N FunctionalBlockDiagram)toallowforcomparatorresponsetime.

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ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N www.ti.com SNAS531B –AUGUST 1999–REVISED MARCH 2013 TypicalPerformance Characteristics Unadjusted OffsetErrorvs.VREF Voltage LinearityErrorvs.VREF Voltage Figure8. Figure9. LinearityErrorvs.Temperature LinearityErrorvs.fCLK Figure10. Figure11. Power Supply Currentvs. Temperature (ADC0838-N, ADC0831-N, ADC0834-N) Output Currentvs.Temperature Note:ForADC0832-N add IREF . Figure12. Figure13. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:ADC0831-N ADC0832-N ADC0834-N ADC0838-N

ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N SNAS531B –AUGUST 1999–REVISED MARCH 2013 www.ti.com TypicalPerformance Characteristics(continued) Power Supply Currentvs.fCLK Figure14. Leakage CurrentTestCircuit TRI-STATE TestCircuitsand Waveforms t1H t1H t0H t0H

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ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N www.ti.com SNAS531B –AUGUST 1999–REVISED MARCH 2013 Timing Diagrams Figure15.Data InputTiming Figure16.Data Output Timing Figure17.ADC0831-N StartConversion Timing *LSB firstoutputnotavailableon ADC0831-N. Figure18. ADC0831-N Timing Figure19. ADC0832-N Timing Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:ADC0831-N ADC0832-N ADC0834-N ADC0838-N

ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N SNAS531B –AUGUST 1999–REVISED MARCH 2013 www.ti.com Figure20. ADC0834-N Timing

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ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N www.ti.com SNAS531B –AUGUST 1999–REVISED MARCH 2013 *Make sureclockedge #18 clocksintheLSB beforeSE istakenlow Figure21. ADC0838-N Timing Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:ADC0831-N ADC0832-N ADC0834-N ADC0838-N

ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N SNAS531B –AUGUST 1999–REVISED MARCH 2013 www.ti.com ADC0838-N FunctionalBlock Diagram *Some ofthesefunctions/pinsarenotavailablewithotheroptions. Note 1:FortheADC0834-N, D1 isinputdirectlytotheD inputofSELECT 1.SELECT 0 isforcedtoa “1”.FortheADC0832-N, DI isinputdirectlytotheDI inputof ODD/SIGN. SELECT 0 isforcedtoa “0”and SELECT 1 isforcedtoa “1”.

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ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N www.ti.com SNAS531B –AUGUST 1999–REVISED MARCH 2013 FunctionalDescription MultiplexerAddressing The designof these convertersutilizesa sample-datacomparatorstructurewhich providesfora differential analoginputtobe convertedby a successiveapproximationroutine. The actualvoltageconvertedisalways the differencebetween an assigned“+” inputterminaland a “−” input terminal.The polarityofeach inputterminalofthepairbeingconvertedindicateswhichlinetheconverterexpects tobe themost positive.Iftheassigned“+”inputislessthanthe“−”inputtheconverterrespondswithan allzeros outputcode. A unique inputmultiplexingscheme has been utilizedto providemultipleanalog channels with software- configurablesingle-ended,differential,or a new pseudo-differentialoptionwhich willconvertthe difference between the voltageat any analoginputand a common terminal.The analogsignalconditioningrequiredin transducer-baseddata acquisitionsystems is significantlysimplifiedwith thistype of inputflexibility.One converterpackage can now handleground referencedinputsand truedifferentialinputsas wellas signalswith some arbitraryreferencevoltage. A particularinputconfigurationis assigned duringthe MUX addressingsequence, priorto the startof a conversion.The MUX addressselectswhich of the analoginputsare to be enabledand whetherthisinputis single-endedordifferential.Inthedifferentialcase,italsoassignsthepolarityofthechannels.Differentialinputs are restrictedtoadjacentchannelpairs.For example channel0 and channel1 may be selectedas a different pairbutchannel0 or1 cannotactdifferentiallywithany otherchannel.Inadditiontoselectingdifferentialmode thesignmay alsobe selected.Channel 0 may be selectedas thepositiveinputand channel1 as thenegative inputorviceversa.Thisprogrammabilityisbestillustratedby theMUX addressingcodes shown inthefollowing tablesforthevariousproductoptions. The MUX address isshiftedintothe converterviathe DI line.Because the ADC0831-N containsonlyone differentialinputchannelwitha fixedpolarityassignment,itdoes notrequireaddressing. The common inputlineon theADC0838-N can be used as a pseudo-differentialinput.Inthismode, thevoltage on thispinistreatedas the“−”inputforany oftheotherinputchannels.Thisvoltagedoes nothave tobe analog ground;itcan be any referencepotentialwhich iscommon to allof the inputs.Thisfeatureismost usefulin single-supplyapplicationwhere theanalogcircuitrymay be biasedup toa potentialotherthanground and the outputsignalsareallreferredtothispotential. Table1.Multiplexer/PackageOptions Single-EndedMUX Mode Number ofAnalog Channels PartNumber Number ofPackage Pins Single-Ended Differential ADC0831-N 1 1 8 ADC0832-N 2 1 8 ADC0834-N 4 2 14 ADC0838-N 8 4 20 Table2.MUX Addressing:ADC0838 -N Single-EndedMUX Mode MUX Address Analog Single-EndedChannel # SGL/ ODD/ SELECT 0 1 2 3 4 5 6 7 COM DIF SIGN 1 0 1 0 0 0 + − 1 0 0 1 + − 1 0 1 0 + − 1 0 1 1 + − 1 1 0 0 + − 1 1 0 1 + − 1 1 1 0 + − 1 1 1 1 + − Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:ADC0831-N ADC0832-N ADC0834-N ADC0838-N

ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N SNAS531B –AUGUST 1999–REVISED MARCH 2013 www.ti.com Table3.MUX Addressing:ADC0838 -N DifferentialMUX Mode MUX Address Analog DifferentialChannel-Pair# SGL/ ODD/ SELECT 0 1 2 3 DIF SIGN 1 0 0 1 2 3 4 5 6 7 0 0 0 0 + − 0 0 0 1 + − 0 0 1 0 + − 0 0 1 1 + − 0 1 0 0 − + 0 1 0 1 − + 0 1 1 0 − + 0 1 1 1 − + Table4.MUX Addressing:ADC0834-N Single-EndedMUX Mode MUX Address Channel # SELECT SGL /DIF ODD /SIGN 0 1 2 3 1 0 0 + 1 0 1 + 1 1 0 + 1 1 1 + Table5.MUX Addressing:ADC0834-N DifferentialMUX Mode MUX Address Channel # SELECT SGL /DIF ODD /SIGN 0 1 2 3 0 0 0 + − 0 0 1 + − 0 1 0 − + 0 1 1 − + Table6.MUX Addressing:ADC0832-N Single-EndedMUX Mode MUX Address Channel # SGL /DIF ODD /SIGN 0 1 1 0 + 1 1 + Table7.MUX Addressing:ADC0832-N DifferentialMUX Mode MUX Address Channel # SGL /DIF ODD /SIGN 0 1 0 0 + − 0 1 − + Since the inputconfigurationisunder softwarecontrol,itcan be modified,as required,at each conversion.A channel can be treatedas a single-ended,ground referencedinputforone conversion;then itcan be reconfiguredas partofa differentialchannelforanotherconversion.Figure22 illustratestheinputflexibilitywhich can be achieved. The analoginputvoltagesforeach channelcan rangefrom50 mV below groundto50 mV above VCC (typically 5V) withoutdegradingconversionaccuracy.

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ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N www.ti.com SNAS531B –AUGUST 1999–REVISED MARCH 2013 THE DIGITAL INTERFACE A most importantcharacteristicoftheseconvertersistheirserialdatalinkwiththecontrollingprocessor.Usinga serialcommunicationformatofferstwo very significantsystem improvements;itallowsmore functionto be includedintheconverterpackage withno increaseinpackage sizeand itcan eliminatethetransmissionoflow levelanalogsignalsby locatingtheconverterrightattheanalogsensor;transmittinghighlynoiseimmune digital databack tothehostprocessor. To understandtheoperationoftheseconvertersitisbesttorefertotheTimingDiagrams and FunctionalBlock Diagram and tofollowa completeconversionsequence.Forclaritya separatediagramisshown ofeach device. 1.A conversionisinitiatedby firstpullingtheCS (chipselect)linelow.Thislinemust be heldlow fortheentire conversion.The converterisnow waitingfora startbitand itsMUX assignmentword. 2.A clockisthengeneratedby theprocessor(ifnotprovidedcontinuously)and outputtotheA/D clockinput.

8 Single-Ended 8 Pseudo-Differential

4 Differential Mixed Mode

Figure22. Analog InputMultiplexerOptions fortheADC0838-N 3. On each risingedge of the clockthe statusof the data in(DI)lineisclockedintothe MUX addressshift register.The startbitisthefirstlogic“1” thatappearson thisline(allleadingzerosare ignored).Followingthe startbittheconverterexpectsthenext2 to4 bitstobe theMUX assignmentword. 4. When the startbithas been shiftedintothe startlocationof the MUX register,the inputchannelhas been assigned and a conversionis about to begin.An intervalof ½ clockperiod(where nothinghappens) is automaticallyinsertedtoallowtheselectedMUX channeltosettle.The SAR statuslinegoes highatthistimeto signalthata conversionisnow inprogressand theDI lineisdisabled(itno longeracceptsdata). 5.The dataout(DO) linenow comes outofTRI-STATE and providesa leadingzeroforthisone clockperiodof MUX settlingtime. 6.When theconversionbegins,theoutputoftheSAR comparator,which indicateswhethertheanaloginputis greaterthan(high)or lessthan(low)each successivevoltagefrom theinternalresistorladder,appearsatthe DO lineon each fallingedge oftheclock.Thisdataistheresultoftheconversionbeingshiftedout(withthe MSB coming first)and can be readby theprocessorimmediately. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:ADC0831-N ADC0832-N ADC0834-N ADC0838-N

ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N SNAS531B –AUGUST 1999–REVISED MARCH 2013 www.ti.com 7.After8 clockperiodstheconversioniscompleted.The SAR statuslinereturnslow toindicatethis½ clock cyclelater. 8.Iftheprogrammer prefers,thedatacan be providedinan LSB firstformat[thismakes use oftheshiftenable (SE) controlline].All8 bitsoftheresultarestoredinan outputshiftregister.On deviceswhichdo notincludethe SE controlline,thedata,LSB first,isautomaticallyshiftedouttheDO line,aftertheMSB firstdatastream.The DO linethengoes low and stayslow untilCS isreturnedhigh.On theADC0838-N theSE lineisbroughtoutand ifheldhigh,thevalueoftheLSB remainsvalidon theDO line.When SE isforcedlow,thedataisthenclocked outLSB first.The ADC0831-N isan exceptioninthatitsdataisonlyoutputinMSB firstformat. 9.Allinternalregistersareclearedwhen theCS lineishigh.Ifanotherconversionisdesired,CS must make a hightolowtransitionfollowedby addressinformation. The DI and DO linescan be tiedtogetherand controlledthrougha bidirectionalprocessorI/Obitwithone wire. Thisispossiblebecause theDI inputisonly“looked-at”duringtheMUX addressingintervalwhiletheDO lineis stillina highimpedance state. ReferenceConsiderations The voltageappliedtothereferenceinputtotheseconvertersdefinesthevoltagespan oftheanaloginput(the differencebetween VIN(MAX) and VIN(MIN)) overwhich the256 possibleoutputcodes apply.The devicescan be used ineitherratiometricapplicationsor insystems requiringabsoluteaccuracy.The referencepinmust be connectedtoa voltagesourcecapableofdrivingthereferenceinputresistanceoftypically3.5kΩ.Thispinisthe topofa resistordividerstringused forthesuccessiveapproximationconversion. Ina ratiometricsystem,theanaloginputvoltageisproportionaltothevoltageused fortheA/D reference.This voltageistypicallythesystempower supply,so theVREF pincan be tiedtoVCC (doneinternallyon theADC0832- N). This techniquerelaxesthe stabilityrequirementsof the system referenceas the analog inputand A/D referencemove togethermaintainingthesame outputcode fora giveninputcondition. For absoluteaccuracy,where theanaloginputvariesbetween veryspecificvoltagelimits,thereferencepincan be biasedwitha timeand temperaturestablevoltagesource.The LM385 and LM336 referencediodesaregood lowcurrentdevicestouse withtheseconverters. The maximum valueofthereferenceislimitedtotheVCC supplyvoltage.The minimum value,however,can be quitesmall(seeTypicalPerformanceCharacteristics)toallowdirectconversionsoftransduceroutputsproviding lessthana 5V outputspan.Particularcaremust be takenwithregardtonoisepickup,circuitlayoutand system errorvoltagesourceswhen operatingwitha reducedspan due totheincreasedsensitivityoftheconverter(1 LSB equalsVREF /256). a)Ratiometric b)Absolutewitha reduced Span Figure23. ReferenceExamples

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ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N www.ti.com SNAS531B –AUGUST 1999–REVISED MARCH 2013 The Analog Inputs The most importantfeatureoftheseconvertersisthattheycan be locatedrightattheanalogsignalsourceand throughjusta few wirescan communicate witha controllingprocessorwitha highlynoiseimmune serialbit stream.This in itselfgreatlyminimizescircuitryto maintainanalog signalaccuracywhich otherwiseismost susceptibletonoisepickup.However,a few words areinorderwithregardtotheanaloginputsshouldtheinput be noisytobeginwithorpossiblyridingon a largecommon-mode voltage. The differentialinputof theseconvertersactuallyreducesthe effectsof common-mode inputnoise,a signal common tobothselected“+” and “−” inputsfora conversion(60 Hz ismost typical).The timeintervalbetween samplingthe“+” inputand thenthe“−” inputis½ ofa clockperiod.The change inthecommon-mode voltage duringthisshorttimeintervalcan cause conversionerrors.Fora sinusoidalcommon-mode signalthiserroris: where

• fCM isthefrequencyofthecommon-mode signal
• VPEAK isitspeak voltagevalue
• fCLK ,istheA/D clockfrequency (1) For a 60 Hz common-mode signaltogeneratea ¼ LSB error(≈5 mV) withtheconverterrunningat250 kHz,its peak valuewould have tobe 6.63V whichwould be largerthanallowedas itexceeds themaximum analoginput limits. Due tothesamplingnatureoftheanaloginputsshortspikesofcurrententerthe“+”inputand exitthe“−”inputat the clockedges duringthe actualconversion.These currentsdecay rapidlyand do not cause errorsas the internalcomparatorisstrobedattheend ofa clockperiod.Bypass capacitorsattheinputswillaveragethese currentsand cause an effectiveDC currentto flowthroughthe outputresistanceof the analogsignalsource. Bypass capacitorsshouldnotbe used ifthesourceresistanceisgreaterthan1 kΩ. ThissourceresistancelimitationisimportantwithregardtotheDC leakagecurrentsofinputmultiplexeras well. The worst-caseleakagecurrentof±1 μA over temperaturewillcreatea 1 mV inputerrorwitha 1 kΩ source resistance.An op amp RC activelow pass filtercan providebothimpedance bufferingand noisefilteringshould a highimpedance signalsourcebe required. OptionalAdjustments Zero Error The zero of the A/D does not requireadjustment.Ifthe minimum analoginputvoltagevalue,VIN(MIN), isnot grounda zerooffsetcan be done.The convertercan be made tooutput0000 0000 digitalcode forthisminimum inputvoltageby biasingany VIN (−)inputatthisVIN(MIN)value.Thisutilizesthedifferentialmode operationofthe A/D. The zeroerroroftheA/D converterrelatestothelocationofthefirstriserofthetransferfunctionand can be measured by groundingtheVIN(−)inputand applyinga smallmagnitudepositivevoltagetotheVIN(+)input.Zero erroristhe differencebetween the actualDC inputvoltagewhich isnecessaryto justcause an outputdigital code transitionfrom0000 0000 to0000 0001 and theideal½ LSB value(½ LSB=9.8 mV forVREF =5.000VDC ). Full-Scale The full-scaleadjustmentcan be made by applyinga differentialinputvoltagewhichis1 ½ LSB down fromthe desiredanalog full-scalevoltagerange and then adjustingthe magnitude of the VREF input(orVCC forthe ADC0832) fora digitaloutputcode whichisjustchangingfrom1111 1110 to1111 1111. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:ADC0831-N ADC0832-N ADC0834-N ADC0838-N

ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N SNAS531B –AUGUST 1999–REVISED MARCH 2013 www.ti.com Adjustingforan ArbitraryAnalog InputVoltageRange IftheanalogzerovoltageoftheA/D isshiftedaway fromground(forexample,toaccommodate an analoginput signalwhichdoes notgo toground),thisnew zeroreferenceshouldbe properlyadjustedfirst.A VIN (+)voltage whichequalsthisdesiredzeroreferenceplus½ LSB (wheretheLSB iscalculatedforthedesiredanalogspan, using 1 LSB= analog span/256)is appliedto selected“+” inputand the zero referencevoltageat the corresponding“−”inputshouldthenbe adjustedtojustobtainthe00HEX to01HEX code transition. The full-scaleadjustmentshouldbe made [withthe properVIN(−) voltageapplied]by forcinga voltageto the VIN(+)inputwhichisgivenby: where

• VMAX = thehighend oftheanaloginputrange
• VMIN = thelowend (theoffsetzero)oftheanalogrange.(Botharegroundreferenced.) (2) The VREF (orVCC ) voltageisthenadjustedtoprovidea code change from FE HEX toFFHEX .Thiscompletesthe adjustmentprocedure. Power Supply A uniquefeatureoftheADC0838-N and ADC0834-N istheinclusionofa zenerdiodeconnectedfrom theV+ terminalto ground which alsoconnectsto the VCC terminal(whichisthe actualconvertersupply)througha silicondiode,as shown inFigure24(1). Figure24. An On-Chip Shunt RegulatorDiode Thiszenerisintendedforuse as a shuntvoltageregulatortoeliminatetheneed forany additionalregulating components.Thisismost desirableifthe converteristo be remotelylocatedfrom the system power source. Figure25 and Figure27 illustratetwo usefulapplicationsofthison-boardzenerwhen an externaltransistorcan be afforded. An importantuse oftheinterconnectingdiodebetween V+ and VCC isshown inFigure26 and Figure28.Here, thisdiodeisused as a rectifiertoallowtheVCC supplyfortheconvertertobe derivedfrom theclock.The low currentrequirementsoftheA/D and therelativelyhighclockfrequenciesused (typicallyintherangeof10k–400 kHz) allowsusingthesmallvaluefiltercapacitorshown tokeep therippleon theVCC linetowellunder¼ ofan LSB. The shuntzenerregulatorcan alsobe used inthismode. Thisrequiresa clockvoltageswing which isin excessofVZ.A currentlimitforthezenerisneeded,eitherbuiltintotheclockgeneratorora resistorcan be used fromtheCLK pintotheV+ pin. (1) Internalzenerdiodes(6.3to8.5V)areconnectedfromV+ toGND and VCC toGND. The zeneratV+ can operateas a shuntregulator and isconnectedtoVCC viaa conventionaldiode.SincethezenervoltageequalstheA/D's breakdown voltage,thediodeinsuresthat VCC willbe belowbreakdown when thedeviceispowered fromV+. FunctionalityisthereforeensuredforV+ operationeven thoughthe resultantvoltageatVCC may exceed thespecifiedAbsoluteMax of6.5V.Itisrecommended thata resistorbe used tolimitthemax currentintoV+. (See Figure24 inFunctionalDescription)

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APPLICATIONS

*4.5V≤ VCC ≤ 6.3V Figure25.Operatingwitha Temperature Figure26.GeneratingVCC from theConverter ClockCompensated Reference *4.5V≤ VCC ≤ 6.3V Figure27.Using theA/D as Figure28.Remote Sensing— theSystem Supply Regulator Clock and Power on 1 Wire Figure29. DigitalLinkand Sample ControllingSoftwarefortheSeriallyOrientedCOP420 and theBit Programmable I/OINS8048 Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:ADC0831-N ADC0832-N ADC0834-N ADC0838-N

ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N SNAS531B –AUGUST 1999–REVISED MARCH 2013 www.ti.com Cop Coding Example Mnemonic Instruction LEI ENABLESSIO'sINPUTANDOUTPUT SC C=1 OGI G0=0(CS=0) CLRA CLEARSACCUMULATOR AISC1 LOADSACCUMULATORWITH1 XAS EXCHANGESSIOWITHACCUMULATOR ANDSTARTSSKCLOCK LDD LOADSMUXADDRESSFROMRAM INTOACCUMULATOR NOP - XAS LOADSMUXADDRESSFROM ACCUMULATOR 8INSTRUCTIONS XAS READSHIGHORDERNIBBLE(4BITS) INTOACCUMULATOR XIS PUTSHIGHORDERNIBBLEINTORAM CLERA CLEARSACCUMULATOR RC C=0 XAS READSLOWORDERNIBBLEINTO ACCUMULATORANDSTOPSSK XIS PUTSLOWORDERNIBBLEINTORAM OGI G0=1(CS=1) LEI DISABLESSIO'sINPUTANDOUTPUT

8048 Coding Example

START:ANLP1,#0F7H;SELECTA/D(CS=0) MOVB,#5 ;BITCOUNTER←5 MOVA,#ADDR;A←MUXADDRESS LOOP1:RRCA ;CY←ADDRESSBIT JC ONE ;TESTBIT ;BIT=0 ZERO:ANLP1,#0FEH;DI←0 JMPCONT ;CONTINUE ;BIT=1 ONE: ORLP1,#1 ;DI←1 CONT:CALLPULSE ;PULSESK0→1→0 DJNZB,LOOP1 ;CONTINUEUNTIL DONE CALLPULSE ;EXTRACLOCKFOR SYNC MOVB,#8 ;BITCOUNTER←8 LOOP2:CALLPULSE ;PULSESK0→1→0 IN A,P1 ;CY←DO RRCA RRCA MOVA,C ;A←RESULT RLCA ;A(0)←BITANDSHIFT MOVC,A ;C←RESULT DJNZB,LOOP2 ;CONTINUEUNTIL DONE RETR ;PULSESUBROUTINE PULSE:ORLP1,#04 ;SK←1 NOP ;DELAY ANLP1,#0FBH;SK←0 RET

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ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N www.ti.com SNAS531B –AUGUST 1999–REVISED MARCH 2013 *Pinoutsshown forADC0838-N. Forallotherproductstieto pinfunctionsas shown. Figure30. A “Stand-Alone” Hook-Up forADC0838-N Evaluation Figure31. Low-Cost Remote Temperature Sensor Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:ADC0831-N ADC0832-N ADC0834-N ADC0838-N

ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N SNAS531B –AUGUST 1999–REVISED MARCH 2013 www.ti.com Figure32. Digitizinga CurrentFlow *VIN(−)= 0.15VCC 15% ofVCC ≤ VXDR ≤ 85% ofVCC Figure33. OperatingwithRatiometricTransducers Figure34. Span Adjust:0V≤VIN≤3V

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ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N www.ti.com SNAS531B –AUGUST 1999–REVISED MARCH 2013 Figure35. Zero-Shiftand Span Adjust:2V ≤ VIN ≤ 5V Figure36. ObtainingHigherResolution-9-BitA/D Controllerperformsa routinetodeterminewhichinputpolarity(9-bitexample)orwhichchannelpair(10-bitexample) providesa non-zerooutputcode.Thisinformationprovidestheextrabits. Figure37. ObtainingHigherResolution-10-BitA/D Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:ADC0831-N ADC0832-N ADC0834-N ADC0838-N

ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N SNAS531B –AUGUST 1999–REVISED MARCH 2013 www.ti.com Diodesare1N914 Figure38. ProtectingtheInput DO = all1s if+VIN > −VIN DO = all0s if+VIN < −VIN Figure39. High Accuracy Comparators

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• Uses one more wirethanloadcellitself
• Two mini-DIPscouldbe mounted insideloadcellfordigitaloutputtransducer
• Electronicoffsetand gaintrimsrelaxmechanicalspecsforgauge factorand offset
• Low levelcelloutputisconvertedimmediatelyforhighnoiseimmunity Figure40. DigitalLoad Cell
• Allpower suppliedby loop
• 1500V isolationatoutput Figure41. 4 mA-20 mA CurrentLoop Converter Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:ADC0831-N ADC0832-N ADC0834-N ADC0838-N

ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N SNAS531B –AUGUST 1999–REVISED MARCH 2013 www.ti.com

• No power requiredremotely
• 1500V isolation Figure42. IsolatedData Converter

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ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N www.ti.com SNAS531B –AUGUST 1999–REVISED MARCH 2013 Figure43. Two Wire Interfacefor8 Channels Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:ADC0831-N ADC0832-N ADC0834-N ADC0838-N

ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N SNAS531B –AUGUST 1999–REVISED MARCH 2013 www.ti.com Figure44. Two Wire 1-ChannelsInterface

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ADC0831-N,ADC0832-N,ADC0834-N,ADC0838-N www.ti.com SNAS531B –AUGUST 1999–REVISED MARCH 2013

REVISION HISTORY

Changes from RevisionA (March 2013)toRevisionB Page Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:ADC0831-N ADC0832-N ADC0834-N ADC0838-N

www.ti.com 1-Nov-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples ADC0831CCN NRND PDIP P 8 40 TBD Call TI Call TI -40 to 85 ADC 0831CCN ADC0831CCN/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br) SN | CU SN Level-1-NA-UNLIM -40 to 85 ADC 0831CCN ADC0831CCWM/NOPB ACTIVE SOIC NPA 14 50 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 ADC0831 CCWM ADC0831CCWMX/NOPB ACTIVE SOIC NPA 14 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 ADC0831 CCWM ADC0832CCN NRND PDIP P 8 40 TBD Call TI Call TI -40 to 85 ADC 0832CCN ADC0832CCN/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br) SN | CU SN Level-1-NA-UNLIM -40 to 85 ADC 0832CCN ADC0832CCWM NRND SOIC NPA 14 50 TBD Call TI Call TI -40 to 85 ADC0832 CCWM ADC0832CCWM/NOPB ACTIVE SOIC NPA 14 50 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 ADC0832 CCWM ADC0832CCWMX NRND SOIC NPA 14 1000 TBD Call TI Call TI -40 to 85 ADC0832 CCWM ADC0832CCWMX/NOPB ACTIVE SOIC NPA 14 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 ADC0832 CCWM ADC0834CCN/NOPB ACTIVE PDIP NFF 14 25 Green (RoHS & no Sb/Br) SN | CU SN Level-1-NA-UNLIM -40 to 85 ADC0834CCN ADC0834CCWM NRND SOIC NPA 14 50 TBD Call TI Call TI -40 to 85 ADC0834 CCWM ADC0834CCWM/NOPB ACTIVE SOIC NPA 14 50 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 ADC0834 CCWM ADC0834CCWMX/NOPB ACTIVE SOIC NPA 14 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 ADC0834 CCWM ADC0838CCN NRND PDIP NFH 20 18 TBD Call TI Call TI -40 to 85 ADC0838CCN ADC0838CCN/NOPB ACTIVE PDIP NFH 20 18 Green (RoHS & no Sb/Br) SN Level-1-NA-UNLIM -40 to 85 ADC0838CCN ADC0838CCWM NRND SOIC DW 20 36 TBD Call TI Call TI -40 to 85 ADC0838 CCWM

www.ti.com 1-Nov-2013 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples ADC0838CCWM/NOPB ACTIVE SOIC DW 20 36 Green (RoHS & no Sb/Br) SN | CU SN Level-3-260C-168 HR -40 to 85 ADC0838 CCWM ADC0838CCWMX NRND SOIC DW 20 1000 TBD Call TI Call TI -40 to 85 ADC0838 CCWM ADC0838CCWMX/NOPB ACTIVE SOIC DW 20 1000 Green (RoHS & no Sb/Br) SN | CU SN Level-3-260C-168 HR -40 to 85 ADC0838 CCWM ADC0838CIWM/NOPB ACTIVE SOIC DW 20 36 Green (RoHS & no Sb/Br) SN | CU SN Level-3-260C-168 HR -40 to 85 ADC0838 CIWM ADC0838CIWMX NRND SOIC DW 20 1000 TBD Call TI Call TI -40 to 85 ADC0838 CIWM ADC0838CIWMX/NOPB ACTIVE SOIC DW 20 1000 Green (RoHS & no Sb/Br) SN | CU SN Level-3-260C-168 HR -40 to 85 ADC0838 CIWM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

www.ti.com 1-Nov-2013 Addendum-Page 3 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC0831CCWMX/NOPB SOIC NPA 14 1000 367.0 367.0 38.0 ADC0832CCWMX SOIC NPA 14 1000 367.0 367.0 38.0 ADC0832CCWMX/NOPB SOIC NPA 14 1000 367.0 367.0 38.0 ADC0834CCWMX/NOPB SOIC NPA 14 1000 367.0 367.0 38.0 ADC0838CCWMX SOIC DW 20 1000 367.0 367.0 45.0 ADC0838CCWMX/NOPB SOIC DW 20 1000 367.0 367.0 45.0 ADC0838CIWMX SOIC DW 20 1000 367.0 367.0 45.0 ADC0838CIWMX/NOPB SOIC DW 20 1000 367.0 367.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 Pack Materials-Page 2

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