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Technical content
Features
- D u a l 7 . 0 m max high side switch (at 25 °C)
- Operating voltage range of 6.0 to 20 V with sleep current < 5.0 µA, extended mode from 4.0 to 28 V
- 8 . 0 MHz 16-bit 3.3 V and 5.0 V SPI control and status reporting with daisy chain capability
- PWM module using external clock or calibratable internal oscillator with programmable outputs delay management
- Smart overcurrent shutdown compliant to huge inrush current, severe short-circuit, overtemperature protections with time limited auto-retry, and Fail-safe mode, in case of MCU damage
- Output OFF or ON OpenLoad detection compliant to bulbs or LEDs and short to battery detection. Analog current feedback with selectable ratio and board temperature feedback.
Figure 1. 07XSC200 Simplified Application Diagram
ORDERING INFORMATION
Range (TA) Package MC07XSC200EK - 40 to 125 °C 32 SOIC VDD I/O I/O SO SCLK CSB SI I/O I/O I/O A/D VPWR FSB WAKE SI SCLK CSB SO RSTB IN0 IN1 CSNS FSI GND HS1 HS0 GND LOAD LOAD MCU VDD VDD VDD VPWR I/O CLOCK 07XSC200
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1 Internal Block Diagram
Figure 2. 07XSC200 Simplified Internal Block Diagram
2 Pin Connections
2.1 Pinout Diagram
Figure 3. 07XSC200 Pin Connection
2.2 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 22. Table 1. 07XSC200 Pin Definitions well as place the device in a low current Sleep mode.
2 CSB Input Chip Select (Active
4 SI Input Serial Input This is a command data input pin connected to the SPI Serial Data Output of
the MCU or to the SO pin of the previous device of a daisy chain of devices. This is an external voltage input pin used to supply power to the SPI circuit. SI pin of the next device of a daisy chain of devices. pins must be shorted to board level.
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for the high current switch. These pins must be shorted at board level. the state of the outputs after a watchdog time-out occurs.
27 CSNS Output Output Current
This pin is used to output a current proportional to the designated HS0-1 output. mode through embedded PWM module. 29 IN0 Input Direct Input 0 This input pin is used to directly control the output HS0. 30 IN1 Input Direct Input 1 This input pin is used to directly control the output HS1.
31 FSB Output Fault Status (Active
32 WAKE Input Wake This pin is used to input a Logic [1] signal so as to enable the watchdog timer
Table 1. 07XSC200 Pin Definitions (continued)
3 Electrical Characteristics
3.1 Maximum Ratings
Table 2. Maximum Ratings
- Load Dump at 25 °C (400 ms)
- Maximum Operating Voltage
- Reverse Battery VPWR(SS) -18 V VDD Supply Voltage Range VDD -0.3 to 5.5 V Input / Output Voltage (4) -0.3 to VDD + 0.3 V WAKE Input Clamp Current ICL(WAKE) 2.5 mA CSNS Input Clamp Current ICL(CSNS) 2.5 mA HS [0:1] Voltage
- P o s i t i v e
- Negative VHS[0:1] -24 V Output Current per Channel
- Nominal Continuous Current(1)
- Short-circuit Transient Current
- Reverse Continuous Current(1) IHS[0:1] 116 -26 A High Side Breakdown Voltage VPWR - VHS 47 V HS[0,1] Output Clamp Energy using single pulse method(2) ECL [0:1] 100 mJ ESD Voltage(3)
- Human Body Model (HBM) for HS[0:1], VPWR and GND
- Human Body Model (HBM) for other pins
- Charge Device Model (CDM) Corner Pins (1, 27, 28, 57) All Other Pins VESD1 VESD2 VESD3 VESD4 ± 8000 ± 2000 ± 750 ± 500 V Notes 1. Continuous high side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current using board thermal resistance is required. 2. Active clamp energy using single-pulse method (L = 2.0 mH, RL = 0 , VPWR = 14 V, TJ = 150 C initial). 3. ESD testing is performed in accordance with the Human Body Model (HBM) (C ZAP = 100 pF, RZAP = 1500 ), the Machine Model (MM) (CZAP = 200 pF, RZAP = 0 ), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). 4. Input / Output pins are: IN[0:1], CLOCK, RSTB, FSI, CSNS, SI, SCLK, CSB, SO, FSB
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- Ambient
- Junction (5) TA TJ - 40 to 125 - 40 to 150 Storage Temperature TSTG - 55 to 150 C THERMAL RESISTANCE Thermal Resistance
- Junction to Case
- Junction to Ambient(6) RJC RJA 4.0 C/ W Peak Pin Reflow Temperature During Solder Mounting(7) TSOLDER 260 C Notes 5. To achieve high reliability over 10 y ears of continuous operation, the device's continuous operating junction temperature should not exceed 125C. 6. Device mounted on a 2s2p test board per JEDEC JESD51-2. 20 °C/W of R θJA can be reached in a real application case (4 layers board). 7. Pin soldering temperature limit is for 40 seconds maximum dura tion. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device.
Table 2. Maximum Ratings (continued)
3.2 Static Electrical Characteristics
Table 3. Static Electrical Characteristics
- Fully Operational
- Extended mode(8) VPWR 6.0 4.0 V Battery Clamp Voltage(9) VPWR(CLAMP) 41 47 53 V VPWR Operating Supply Current
- Outputs commanded ON, HS[0 : 1] open, IN[0:1] > VIH IPWR(ON) –6 . 5 2 0 mA VPWR Supply Current
- Outputs commanded OFF, OFF Open-load Detection Disabled, HS[0 : 1] shorted to the ground with VDD = 5.5 V WAKE > VIH or RSTB > VIH and IN[0:1] < VIL IPWR(SBY) –6 . 5 7 . 5 mA Sleep State Supply Current VPWR = 12 V, RSTB = WAKE = CLOCK = IN[0:1] < VIL, HS[0 :1] shorted to ground
- T A = 25 °C
- T A = 85 °C IPWR(SLEEP) 1.0 5.0 VDD Supply Voltage VDD(ON) 3 . 0–5 . 5 V VDD Supply Current at VDD = 5.5 V
- No SPI Communication
- 8 . 0 MHz SPI Communication(10) IDD(ON) 1.6 5.0 2.2 mA VDD Sleep State Current at VDD = 5.5 V IDD(SLEEP) –– 5 . 0 A Overvoltage Shutdown Threshold VPWR(OV) 28 32 36 V Overvoltage Shutdown Hysteresis VPWR(OVHYS) 0.2 0.8 1.5 V Undervoltage Shutdown Threshold(11) VPWR(UV) 3.3 3.9 4.3 V VPWR and VDD Power on Reset Threshold VSUPPLY(POR) 0 . 5–0 . 9 V PWR(UV) Recovery Undervoltage Threshold VPWR(UV)_UP 3.4 4.1 4.5 V VDD Supply Failure Threshold (for VPWR > VPWR(UV)) VDD(FAIL) 2.2 2.5 2.8 V Notes 8. In extended mode, the functionality is guaranteed but not the electrical parameters. From 4.0 to 6.0 V voltage range, the device is only protected with the thermal shutdown detection. 9. Measured with the outputs open. 10. Typical value guaranteed per design. 11. Output will automatically recover with time limited auto-retry to instructed state when VPWR voltage is restored to normal as long as the VPWR degradation level did not go below the undervoltage power-ON reset threshold. This applies to all internal device logic that is supplied by VPWR and assumes that the external VDD supply is within specification.
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- V PWR = 4.5 V
- V PWR = 6.0 V
- V PWR = 10 V
- V PWR = 13 V RDS_01(ON) 25.2 11.2 7.0 7.0 HS[0,1] Output Drain-to-Source ON Resistance (I HS = 5.0 A, TA = 150 C)
- V PWR = 4.5 V
- V PWR = 6.0 V
- V PWR = 10 V
- V PWR = 13 V RDS_01(ON) 42.8 19.1 11.9 11.9 HS[0,1] Output Source-to-Drain ON Resistance (I HS = -5.0 A, VPWR= -18 V)(12)
- T A = 25 C
- T A = 150 C RSD_01(ON) 10.5 HS[0,1] Maximum Severe Short-circuit Impedance Detection(13) RSHORT_01 21 47 75 m HS[0,1] Output Overcurrent Detection Levels (6.0 V < VHS[0:1] < 20 V)
- 28W bit = 0
- 28W bit = 1 OCHI1_0 OCHI2_0 OC1_0 OC2_0 OC3_0 OC4_0 OCLO4_0 OCLO3_0 OCLO2_0 OCLO1_0 OCHI1_1 OCHI2_1 OC1_1 OC2_1 OC3_1 OC4_1 OCLO4_1 OCLO3_1 OCLO2_1 OCLO1_1 89.9 35.2 28.8 13.3 11.3 7.4 44.9 33.5 20.8 17.6 14.4 6.1 6.1 6.1 2.7 114.8 83.7 61.2 53.2 44.6 36.4 26.6 18.4 14.2 9.3 57.4 41.9 30.6 26.5 22.3 18.2 7.6 7.6 7.6 4.9 139.8 100.4 74.4 64.4 32.1 23.5 17.1 11.2 69.9 50.2 37.2 32.1 9.0 9.0 9.0 7.0 A Notes 12. Source-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VPWR. 13. Short-circuit impedance calcul ated from HS[0:1] to GND pins. Value guaranteed per design.
Table 3. Static Electrical Characteristics (continued)
- 28W bit = 0
- CSNS_ratio bit = 0
- CSNS_ratio bit = 1
- 28W bit = 1
- CSNS_ratio bit = 0
- CSNS_ratio bit = 1 CSR0_0 CSR1_0 CSR0_1 CSR1_1 HS[0,1] Current Sense Ratio (CSR0) Accuracy (6.0 V < VHS[0:1] < 20 V) with 28W bit = 0 25 and 125 C
- I HS[0:1] = 5.0 A
- I HS[0:1] = 3.0 A
- I HS[0:1] = 1.5 A -40 C
- I HS[0:1] = 5.0 A
- I HS[0:1] = 3.0 A
- I HS[0:1] = 1.5 A CSR0_0_ACC -15 -22 -27 -30 -20 -27 -30 -40 HS[0,1] Current Recopy Accuracy with one calibration point (6.0 V < VHS[0:1] < 20 V) with 28W bit = 0(15)
- I HS[0:1] = 5.0 A CSR0_0_ACC (CAL) -5.0 – 5.0 HS[0,1] Current Sense Ratio (CSR0) Accuracy (6.0 V < VHS[0:1] < 20 V) with 28W bit = 1 25 and 125 C
- I HS[0:1] = 3.0 A
- I HS[0:1] = 1.5 A -40 C
- I HS[0:1] = 3.0 A
- I HS[0:1] = 1.5 A CSR0_1_ACC -25 -30 -30 -40 HS[0,1] Current Recopy Accuracy with one calibration point (6.0 V < VHS[0:1] < 20 V) with 28W bit = 1(15)
- I HS[0:1] = 3.0 A CSR0_1_ACC (CAL) -5.0 – 5.0 HS[0,1] CSR0 Current Recopy Temperature Drift (6.0 V < VHS[0:1] < 20 V) with 28W bit = 0(16)
- I HS[0:1] = 5.0 A (CSR0_0)/(T) – – 0.04 %/C Notes 14. Current sense ratio = I CSNS / IHS[0:1] 15. Based on statistical analysis. It is not production tested. 16. Based on statistical data: delta(C SR0)/delta(T)={(measured ICSNS at T1 - measured ICSNS at T2) / measured ICSNS at room} / {T1-T2}. No production tested.
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- I HS[0:1] = 75 A -40 C
- I HS[0:1] = 75 A CSR1_0_ACC -20 -17 -28 -25 HS[0,1] Current Recopy Accuracy with one calibration point (6.0 V < VHS[0:1] < 20 V) with 28W bit = 0(17) CSR1_0_ACC (CAL) -5.0 – 5.0 HS[0,1] Current Sense Ratio (CSR1) Accuracy (6.0V < VHS[0:1] < 20V) with 28W bit = 1 25 and 125 C -40 C
- I HS[0:1] = 75 A CSR1_1_ACC -20 -17 -28 -25 HS[0,1] Current Recopy Accuracy with one calibration point (6.0 V < VHS[0:1] < 20 V) with 28W bit = 1(17) CSR1_1_ACC (CAL) -5.0 – 5.0 Current Sense Clamp Voltage
- CSNS Open; IHS[0:1] = 5.0 A with CSR0 ratio VCL(CSNS) VDD+0.25 – V DD+1.0 V OFF OpenLoad Detection Source Current(18) IOLD(OFF) 30 – 100 A OFF OpenLoad Fault Detection Voltage Threshold VOLD(THRES) 2.0 3.0 4.0 V ON OpenLoad Fault Detection Current Threshold IOLD(ON) 80 330 660 mA ON OpenLoad Fault Detection Current Threshold with LED
- V HS[0:1] = VPWR - 0.75 V IOLD(ON_LED) 2.5 5.0 10 mA Output Short to VPWR Detection Voltage Threshold
- Output programmed OFF VOSD(THRES) VPWR-1.2 VPWR-0.8 V PWR-0.4 V Output Negative Clamp Voltage
- 0 . 5 A < IHS[0:1] < 5.0 A, Output programmed OFF VCL - 22 – -16 V Output Overtemperature Shutdown for 4.5 V < VPWR < 28 V TSD 155 175 195 C Notes 17. Based on statistical analysis. It is not production tested. 18. Output OFF OpenLoad Detection Current is the current required to flow through the load for the purpose of detecting the existence of an open-load condition when the specific output is commanded OFF. Pull-up current is measured for VHS = VOLD(THRES)
- I CL(WAKE) < 2.5 mA VCL(WAKE) 18 25 32 V Wake Input Forward Voltage
- I CL(WAKE) = -2.5 mA VF(WAKE) - 2.0 – - 0.3 V SO High-state Output Voltage
- I OH = 1.0 mA VSOH VDD-0.4 – – V SO and FSB Low-state Output Voltage
- I OL = -1.0 mA VSOL – – 0.4 V SO, CSNS and FSB Tri-state Leakage Current
- CSB = VIH and 0 V < VSO < VDD, or FSB = 5.5 V, or CSNS = 0.0 V ISO(LEAK) - 2.0 0.0 2.0 FSI External Pull-down Resistance(24)
- Watchdog Disabled
- Watchdog Enabled RFS – 0.0 Infinite 1.0 Notes 19. Upper and lower logic threshold voltage range applies to SI, CSB, SCLK, FSB, IN[0:1], CLOCK and WAKE input signals. The WAKE and RSTB signals may be supplied by a derived voltage referenced to VPWR. 20. Input capacitance of SI, CSB, SCLK, RSTB, IN[0:1], CLOCK and W AKE. This parameter is guaranteed by process monitoring but is not production tested. 21. The current must be limited by a series resistance when using voltages > 7.0 V. 22. Pull-down current is with V SI > 1.0 V and VSCLK > 1.0 V. 23. Pull-up current is with V CSB < 2.0 V. CSB has an active internal pull-up to VDD. 24. In Fail-safe HS[0:1] depends respectively on IN [0:1]. FSI has an active internal pull-up to VREG ~ 3.0 V.
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3.3 Dynamic Electrical Characteristics
Table 4. Dynamic Electrical Characteristics
- V PWR = 14 V SRR_00 0.15 0.3 0.6 V/s Output Rising Slow Slew Rate (low speed slew rate / SR[1:0] = 01)(25)
- V PWR = 14 V SRR_01 0.07 0.15 0.3 V/s Output Falling Fast Slew Rate (high speed slew rate / SR[1:0] = 10)(25)
- V PWR = 14 V SRR_10 0.3 0.6 1.2 V/s Output Falling Medium Slew Rate (medium speed slew rate / SR[1:0] = 00)(25)
- V PWR = 14 V SRF_00 0.15 0.3 0.6 V/s Output Falling Slow Slew Rate (low speed slew rate / SR[1:0] = 01)(25)
- V PWR = 14 V SRF_01 0.07 0.15 0.3 V/s Output Rising Fast Slew Rate (high speed slew rate / SR[1:0] = 10)(25)
- V PWR = 14 V SRF_10 0.3 0.6 1.2 V/s HS[0:1] Outputs Turn-ON and OFF Delay Times(26)(27) VPWR = 14 V for medium speed slew rate (SR[1:0] = 00)
- t DLY(ON)
- t DLY(OFF) t DLY_12 130 180 140 Driver Output Matching Slew Rate (SRR /SRF)
- VPWR = 14 V @ 25 °C and for medium speed slew rate (SR[1:0] = 00) SR 0.8 1.0 1.2 HS[0:1] Driver Output Matching Time (t DLY(ON) - t DLY(OFF))
- V PWR = 14 V, f PWM = 240 Hz, PWM duty cycle = 50%, @ 25 °C for medium speed slew rate (SR[1:0] = 00) t RF_01 0 50 100 Notes 25. Rise and Fall Slew Rates measured across a 5.0 resistive load at high side output = 30% to 70% (see Figure 4, page 19). 26. Turn-ON delay time measured fr om rising edge of any signal (IN[0 : 1] and CSB) that would turn the output ON to VHS[0 : 1] = VPWR / 2 with RL = 5.0 resistive load. 27. Turn-OFF delay time measured from falling edge of any signal (IN[0 : 1] and CSB) that would turn the output OFF to VHS[0 : 1] = VPWR / 2 with RL = 5.0 resistive load.
- Time necessary to report the fault to FSB pin.
- Time necessary to switch-off the output in case of OT or OC or SC or UV fault detection (from negative edge of FSB pin to HS voltage =
- Time necessary for CSNS to be within ±5% of the targeted value (from HS voltage = 50% of V PWR to ±5% of the targeted CSNS value).
- For FSI open, the Watchdog time-out delay measured from the rising edge of RSTB, to HS[0,1] output state depend on the corresponding
Table 4. Dynamic Electrical Characteristics (continued)
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- Clock Fail detector available fo r PWM_en bit is set to logic [1] and CLOCK_sel is set to logic [0].
- The PWM ratio is measured at V HS = 50% of VPWR and for the default SR value. It is possible to put the device fully-on (PWM duty cycle
and the PWM on the output with RL = 5.0 resistive load.
- Typical value guaranteed per design.
- Value guaranteed per statistical analysis.
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- C L = 80 pF t RSO – – 13 ns SO Fall Time
- C L = 80 pF t FSO – – 13 ns SI, CSB, SCLK, Incoming Signal Rise Time(39) t RSI – – 13 ns SI, CSB, SCLK, Incoming Signal Fall Time(39) t FSI – – 13 ns Time from Falling Edge of CSB to SO Low-impedance(40) t SO(EN) – – 60 ns Time from Rising Edge of CSB to SO High-impedance(41) t SO(DIS) – – 60 ns Notes 36. Parameters guaranteed by design. 37. RSTB low duration measured with outputs enabled and going to OFF or disabled condition. 38. Maximum setup time required for the 07XSC200 is the minimum guaranteed time needed from the microcontroller. 39. Rise and Fall time of incoming SI, CSB, and SCLK signals sugges ted for design consideration to prevent the occurrence of double pulsing. 40. Time required for output status data to be available for use at SO. 1.0 kon pull-up on CSB. 41. Time required for output status data to be terminated at SO. 1.0 kon pull-up on CSB.
3.4 Timing Diagrams
Figure 4. Output Slew Rate and Time Delays Figure 5. Overcurrent Shutdown Protection
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Figure 6. Bulb Cooling Management Figure 7. Input Timing Switching Characteristics
0.7 VDD
0.2 VDD
Figure 8. SCLK Waveform and Valid SO Data Delay Time
Analog Integrated Circuit Device Data
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4 Functional Description
4.1 Introduction
The 07XSC200 is one in a family of devices designed for low-voltage lighting applications. Its two low RDS(ON) MOSFETs (dual 7.0 m) can control two separate 55 W / 28 W bulbs and/or Xenon modules. Programming, control and diagnostics are accomplished using a 16-bit SPI interface. Its output with selectable slew rate improves electromagnetic compatibility (EMC) behavior. Additionally, each output has its own parallel input or SPI control for pulse-width modulation (PWM) control if desired. The 07XSC200 allows the user to program via the SPI, the fault current trip levels and duration of acceptable lamp inrush. The device has fail-safe mode to provide fail-safe functionality of the outputs in case of MCU damaged.
4.2 Functional Pin Description
4.2.1 Output Current Monitoring (CSNS)
The Current Sense pin provides a current proportional to the designated HS0 : HS1 output or a voltage proportional to the temperature on the GND flag. That current is fed into a ground-referenced resistor (2.5 k typical) and its voltage is monitored by an MCU's A/D. The output type is selected via the SPI. This pin can be tri-stated through the SPI.
4.2.2 Direct Inputs (IN0, IN1)
Each IN input wakes the device. The IN0 : IN1 high side input pins are also used to directly control HS0 : HS1 high side output pins. If the outputs are controlled by PWM module, the external PWM clock is applied to IN0 pin. These pins are to be driven with CMOS levels, and they have a passive internal pull-down, RDWN.
4.2.3 Fault Status (FSB)
This pin is an open drain configured output requiring an external pull-up resistor to VDD for fault reporting. If a device fault condition is detected, this pin is active LOW. Specific device diagnostics and faults are reported via the SPI SO pin.
4.2.4 WAKE (WAKE)
The WAKE input wakes the device. An internal clamp protects this pin from high damaging voltages with a series resistor (10 k typ). This input has a passive internal pull-down, RDWN.
4.2.5 PWM Clock (CLOCK)
The clock input wakes the device. The PWM frequency and timing are generated from clock input by the PWM module. The clock input frequency is the selectable factor 2 7 = 128. This input has a passive internal pull-down, RDWN.
4.2.6 RESET (RSTB)
The RESET input wakes the device. This is used to initialize the device configuration and fault registers, as well as place the device in a low-current sleep mode. The pin also starts the watchdog timer when transitioning from logic [0] to logic [1]. This pin has a passive internal pull-down, RDWN.
Analog Integrated Circuit Device Data Freescale Semiconductor 23 07XSC200
4.2.7 Chip Select (CSB)
The CSB pin enables communication with the master microcontroller (MCU). When this pin is in a logic [0] state, the device is capable of transferring information to, and receiving information from, the MCU. The 07XSC200 latches in data from the Input Shift registers to the addressed registers on the rising edge of CSB. The device transfers status information from the power output to the Shift register on the falling edge of CSB. The SO output driver is enabled when CSB is logic [0]. CSB should transition from a logic [1] to a logic [0] state only when SCLK is a logic [0]. CSB has an active internal pull-up from VDD, IUP.
4.2.8 Serial Clock (SCLK)
The SCLK pin clocks the internal shift registers of the 07XSC200 device. The serial input (SI) pin accepts data into the input shift register on the falling edge of the SCLK signal while the serial output (SO) pin shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important the SCLK pin be in a logic low state whenever CSB makes any transition. For this reason, it is recommended the SCLK pin be in a logic [0] whenever the device is not accessed (CSB logic [1] state). SCLK has an active internal pull-down. When CSB is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high- impedance) (see Figure 10, page 26). SCLK input has an active internal pull-down, IDWN.
4.2.9 Serial Input (SI)
This is a serial interface (SI) command data input pin. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of serial data is required on the SI pin, starting with D15 (MSB) to D0 (LSB). The internal registers of the 07XSC200 are configured and controlled using a 5-bit addressing scheme described in Table 9, page 36. Register addressing and configuration are described in Tables 10, page 36. SI input has an active internal pull-down, IDWN.
4.2.10 Digital Drain Voltage (VDD)
This pin is an external voltage input pin used to supply power to the SPI circuit. In the event VDD is lost (VDD Failure), the device goes to Fail-safe mode.
4.2.11 Ground (GND)
These pins are the ground for the device.
4.2.12 Positive Power Supply (VPWR)
This pin connects to the positive power supply and is the source of operational power for the device. The VPWR contact is the backside surface mount tab of the package.
4.2.13 Serial Output (SO)
The SO data pin is a tri-stateable output from the shift register. The SO pin remains in a high impedance state until the CSB pin is put into a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, the state of the key inputs, etc. The SO pin changes state on the rising edge of SCLK and reads out on the falling edge of SCLK. SO reporting descriptions are provided in Table 22, page 42.
4.2.14 High Side Outputs (HS0, HS1)
Protected 7.0 m high side power outputs to the load.
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4.2.15 Fail-safe Input (FSI)
Failure condition, in case VDD failure detection is activated (VDD_FAIL_en bit sets to logic [1]).
4.3 Functional Internal Block Description
Figure 9. Functional Block Diagram
4.3.1 Power Supply
Fail-safe mode in case of failures on the SPI or/and on VDD voltage.
4.3.2 High Side Switches: HS0–HS1
and a short-circuit fault condition. The HS output is actively clamped during turn off of inductive loads and inductive battery line. the device in its Safe Operating Area.
Analog Integrated Circuit Device Data Freescale Semiconductor 25 07XSC200
4.3.3 MCU Interface and Output Control
In Normal mode, each bulb is controlled directly from the MCU through the SPI. A pulse width modulation control module allows improvement of lamp lifetime with bulb power regulation (PWM frequency range from 100 to 400 Hz) and addressing the dimming application (day running light). An analog feedback output provides a current proportional to the load current or the temperature of the board. The SPI is used to configure and to read the diagnostic status (faults) of high side outputs. The reported fault conditions are: OpenLoad, short-circuit to battery, short-circuit to ground (overcurrent and severe short-circuit), thermal shutdown, and under/overvoltage. In Fail-safe mode, each lamp is controlled with dedicated parallel input pins. The device is configured in default mode.
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5 Functional Device Operation
5.1 SPI Protocol Description
Serial Output (SO), Serial Clock (SCLK), and Chip Select (CSB). most significant bit (MSB) first. All inputs are compatible with 5.0 or 3.3 V CMOS logic levels. Figure 10. Single 16-Bit Word SPI Communication
5.2 Operational Modes
contained in succeeding paragraphs. The Figure 11 describes an internal signal called IN_ON[x] depending on IN[x] input. Figure 11. IN_ON[x] internal signal
- wake-up = RSTB or WAKE or IN_ON[0] or IN_ON[1] or CLOCK_ON,
- fail = (V DD Failure and VDD_FAIL_en) or (Watchdog time-out and FSI input not shorted to ground),
- fault = OC[0:1] or OT[0:1] or SC[0:1] or UV or (OV and OV_dis). CSCSB SI SCLK SO D15 D1 D2 D3 D4 D5 D6 D7 D8 D9 D14 D13 D12 D11 D10 OD12 OD13 OD14 OD15 OD6OD7OD8OD9OD10OD11 OD1 OD2 OD3 OD4OD5 1. RSTB is in a logic H state during the above operation. 2. DO, D1, D2, ... , and D15 relate to the most recent ordered entry of program data into the LUX IC NOTES: OD0 CSB device. 1. RSTB is a logic [1] state during the above operation. 2. D15:D0 relate to the most recent ordered entry of data into the device. 3. OD15:OD0 relate to the first 16 bits of ordered fault and status data out of the device. Notes IN_ON[x] IN[x] tIN
Figure 12. Operating Modes
5.2.1 Sleep Mode
- V PWR and VDD are within the normal voltage range,
- wake-up = 0,
- fail = X,
- f a u l t = X . This is the Default mode of the device after first applying battery voltage (VPWR) prior to any I/O transitions. This is also the state of the device when the WAKE and RSTB, CLOCK_ON and IN_ON[0:1] are logic [0]. In the Sleep mode, the output and all unused internal circuitry, such as the internal regulator, are off to minimize draw current. In addition, all SPI-configurable features of the device are as if set to logic [0]. In the event of an external VPWR supply disconnect, an unexpected current consumption may sink on the VDD supply pin (In Sleep state). This current leakage is about 70 mA instead of 5.0 µA and it may impact the device reliability. The device recovers its normal operational mode once VPWR is reconnected.
Table 5. 07XSC200 Operating Modes Sleep 0 x x Device is in Sleep mode. All outputs are OFF. watchdog time-out or VDD Failure conditions. circuitry is active to turn-on again the output(s).
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supply pin to switch the device to Sleep state.
5.2.2 Normal Mode
- V PWR and VDD are within the normal voltage range,
- wake-up = 1,
- fail = 0,
- f a u l t = 0 . In this mode, the NM bit is set to lfault_contrologic [1] and the outputs HS[0:1] are under control, as defined by the hson signal: hson[x] = (((IN[x] and DIR_dis[x]) or On bit[x]) and PWM_en) or (On bit [x] and Duty_cycle[x] and PWM_en). In this mode and also in Fail-safe, the fault condition reset depends on fault_control signal, as defined below: fault_control[x] = ((IN_ON[x] and DIR_dis[x]) and PWM_en) or (On bit [x]).
5.2.2.1 Programmable PWM Module
The outputs HS[0:1] are controlled by the programmable PWM module if PWM_en and On bits are set to logic [1]. (Table 6). The state of other IN pin is ignored. behavior of the light module (Table 7). Table 6. Output PWM Resolution
0 X OFF
Table 7. Output PWM Switching Delay
Analog Integrated Circuit Device Data Freescale Semiconductor 29 07XSC200 The clock frequency from CLOCK is permanently monitored in order to report a clock failure in case the frequency is out a specified frequency range (from fCLOCK(LOW) to fCLOCK(HIGH)). In case of clock failure, no PWM feature is provided, the On bit defines the outputs state and the CLOCK_fail bit reports [1].
5.2.2.2 Calibratable Internal Clock
The internal clock can vary as much as 30 percent corresponding to typical fPWM(0) output switching period. Using the existing SPI inputs and the precision timing reference already available to the MCU, the 07XSC200 allows clock period setting within 10 percent of accuracy. Calibrating the internal clock is initiated by defined word to CALR register. The calibration pulse is provided by the MCU. The pulse is sent on the CSB pin after the SPI word is launched. At the moment, the CSB pin transitions from logic [1] to [0] until from logic [0] to [1] determines the period of internal clock with a multiplicative factor of 128. In case a negative CSB pulse is outside a predefined time range (from t CSB(MIN) to t CSB(MAX)), the calibration event will be ignored and the internal clock will be unaltered or reset to the default value (fPWM(0)), if this was not calibrated before. The calibratable clock is used, instead of the clock from CLOCK input, when CLOCK_sel is set to [1].
5.2.3 Fail-safe Mode
The 07XSC200 is in Fail-safe mode when:
- V PWR is within the normal voltage range,
- wake-up = 1,
- fail = 1,
- f a u l t = 0 .
5.2.3.1 Watchdog
If the FSI input is not grounded, the watchdog time-out detection is active when either the WAKE or IN_ON[0:1] or RSTB input pin transitions from logic [0] to logic [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting resistance limiting the internal clamp current according to the specification. The watchdog time-out is a multiple of an internal oscillator. As long as the WD bit (D15) of an incoming SPI message is toggled within the minimum watchdog time-out period (WDTO), the device will operate normally.
5.2.3.2 Fail-safe Conditions
If an internal watchdog time-out occurs before the WD bit for FSI open (Table 8) or in case of VDD failure condition (VDD< VDD(FAIL))) for VDD_FAIL_en bit is set to logic [1], the device will revert to a Fail-safe mode until the WD bit is written to logic [1] (see fail-safe to normal mode transition paragraph) and VDD is within the normal voltage range. CS SI CALR SI command ignored Internal clock duration
30 Freescale Semiconductor
value (except POR bit) and fault protections are fully operational. The Fail-safe mode can be detected by monitoring the NM bit is set to [0].
5.2.4 Normal & Fail-safe Mode Transitions
Moreover, the device can be brought out of the Fail-safe mode due to watchdog time-out issue by forcing the FSI pin to logic [0]. Fail-safe mode (auto-retry included).
5.2.5 Fault Mode
- V PWR and VDD are within the normal voltage range,
- wake-up = 1,
- fail = X,
- f a u l t = 1 . This device indicates the faults below as they occur by driving the FSB pin to logic [0] for RSTB input is pulled up:
- Overtemperature fault,
- Overcurrent fault,
- Severe short-circuit fault,
- Output(s) shorted to V PWR fault in OFF state,
- OpenLoad fault in OFF state,
- Overvoltage fault (enabled by default),
- Undervoltage fault. The FSB pin will automatically return to logic [1] when the fault condition is removed, except for overcurrent, severe short-circuit, overtemperature and undervoltage which will be reset by a new turn-on command (each fault_control signal to be toggled). Fault information is retained in the SPI fault register and is available (and reset) via the SO pin during the first valid SPI communication. The OpenLoad fault in ON state is only reported through SPI register without effect on the corresponding output state (HS[x]) and the FS pin.
5.2.6 Start-up Sequence
- VPWR and VDD power supplies must be above their undervoltage thresholds,
- generate wake-up event (wake-up=1) from 0 to 1 on RSTB. The device switches to normal mode with SPI register content is reset (as defined in Table 10 and Table 22). All features of the 07XSC200 will be available after 50 s typical, and all SPI registers are set to default values (set to logic [0]).
- toggle WD bit from 0 to 1. And, in case the PWM module is used (PWM_en bit is set to logic [1]) with an external reference clock:
Table 8. SPI Watchdog Activation
Analog Integrated Circuit Device Data Freescale Semiconductor 31 07XSC200
- apply PWM clock on CLOCK input pin after maximum 200 s (min. 50s). If the correct start-up sequence is not provided, the PWM function is not guaranteed.
5.3 Protection and Diagnostic Features
5.3.1 Protections
The 07XSC200 incorporates over-temperature detection and shutdown circuitry for each output structure. Two cases need to be considered when the output temperature is higher than TSD:
- If the output command is ON: the correspondi ng output is latched OFF. FSB will be also latched to logic [0]. To delatch the fault and be able to turn ON again the outputs, the failure condition must disappear and the auto-retry circuitry must be active, or the corresponding output must be commanded OFF and then ON (toggling fault_control signal of corresponding output) or the VSUPPLY(POR) condition, if VDD = 0.
- If the output command is OFF: FSB will go to logic [0 ] till the corresponding output temperature are below TSD. For both cases, the fault register OT[0:1] bit into the status register will be set to [1]. The fault bits will be cleared in the status register after a SPI read command.
5.3.1.1 Overcurrent Fault
The 07XSC200 incorporates output shutdown in order to protect each output structure against resistive short-circuit condition. This protection is composed by eight predefined current levels (time dependent) to fit Xenon-HID manners by default or, 55 W or 28 W bulb profiles, selectable separately by Xenon bit and 28W bits (as illustrated Figure 14, page 39). In the first turn-on, the lamp filament is cold and the current will be huge. fault_control signal transition from logic [0] to [1] or an auto-retry define this event. In this case, the overcurrent protection will be fitted to inrush current, as shown in Figure 5. This overcurrent protection is programmable: OC[1:0] bits select overcurrent slope speed and OCHI1 current step can be removed in case the OCHI bit is set to [1]. In Steady state, the wire harness will be protected by OCLO2 current level by default. Three other DC overcurrent levels are available: OCLO1 or OCLO3 or OCLO4 based on the state of the OCLO[1,0] bits. If the load current level ever reaches the overcurrent detection level, the corresponding output will latch the output OFF and FSB will be also latched to logic [0]. To delatch the fault and be able to turn ON again the corresponding output, the failure condition must disappear and the auto-retry circuitry must be active or the corresponding output must be commanded OFF and then ON (toggling fault_control signal of corresponding output) or VSUPPLY(POR) condition if VDD = 0. The SPI fault report (OC[0:1] bits) is removed after a read operation. In Normal mode using internal PWM module, the 07XSC200 incorporates also a cooling bulb filament management if OC_mode and Xenon are set to logic [1]. In this case, the firstt step of multi-step overcurrent protection will depend to the previous OFF duration, as illustrated in Figure 6. The following figure illustrates the current level will be used in function to the duration of previous OFF state (toff). The slope of cooling bulb emulator is configurable with OCOFFCB[1:0] bits. hson signal Over-current thresholds PWM fault_control hson
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5.3.1.2 Severe Short-circuit Fault
The 07XSC200 provides output shutdown to protect each output in case of a severe short-circuit during of the output switching. If the short-circuit impedance is below RSHORT, the device will latch the output OFF, FSB will go to logic [0] and the fault register SC[0:1] bit will be set to [1]. To delatch the fault and be able to turn ON again the outputs, the failure condition must disappear and the corresponding output must be commanded OFF and then ON (toggling fault_control signal of corresponding output) or VSUPPLY(POR) condition if VDD = 0. The SPI fault report (SC[0:1] bits) is removed after a read operation.
5.3.1.3 Overvoltage Fault (Enabled by Default)
By default, the overvoltage protection is enabled. The 07XSC200 shuts down all outputs and FSB will go to logic [0] during an overvoltage fault condition on the VPWR pin (VPWR > VPWR(OV)). The outputs remain in the OFF state until the overvoltage condition is removed (VPWR < VPWR(OV) - VPWR(OVHYS)). When experiencing this fault, the OVF fault bit is set to logic [1] and cleared after either a valid SPI read. The overvoltage protection can be disabled through the SPI (OV_dis bit is disabled set to logic [1]). The fault register reflects any overvoltage condition (VPWR > VPWR(OV)). This overvoltage diagnosis, as a warning, is removed after a read operation, if the fault condition disappears. The HS[0:1] outputs are not commanded in RDS(ON) above the OV threshold.
5.3.1.4 Undervoltage Fault
The output(s) will latch off at some battery voltage below VPWR(UV). As long as the VDD level stays within the normal specified range, the internal logic states within the device will remain (configuration and reporting). In the case where battery voltage drops below the undervoltage threshold (VPWR < VPWR(UV)), the outputs will turn off, FSB will go to logic [0], and the fault register UV bit will be set to [1]. Two cases need to be considered when the battery level recovers (VPWR > VPWR(UV)_UP):
- If outputs command are low, FSB will go to logic [1] but the UV bit will remain set to 1 until the next read operation (warning report).
- If the output command is ON, FSB will remain at logic [0]. To delatch the fault and be able to turn ON again the outputs, the failure condition must disappear and the auto-retry circuitry must be active or the corresponding output must be commanded OFF and then ON (toggling fault_control signal of corresponding output) or VSUPPLY(POR) condition if VDD = 0. In extended mode, the output is protected by overtemperature shutdown circuitry. All previous latched faults, occurred when VPWR was within the normal voltage range, are guaranteed if VDD is within the operational voltage range or until VSUPPLY(POR) if VDD = 0. Any new OT fault is detected (VDD failure included) and reported through SPI above VPWR(UV). The output state is not changed as long as the VPWR voltage does not drop any lower than 3.5 V typical. All latched faults (overtemperature, overcurrent, severe short-circuit, over and undervoltage) are reset if:
- V DD < VDD(FAIL) with VPWR in nominal voltage range,
- V DD and VPWR supplies is below VSUPPLY(POR) voltage value. Over-current thresholds toff depending to toff Cooling PWM hson signalfault_control hson Depending on toff
Figure 13. Auto-retry State Machine
5.3.2 Auto-retry
failure conditions to provide a high availability of the load. retry[x] = OC[x] or OT[x] or UV. transitions. At each auto-retry, the overcurrent detection will be set to default values in order to sustain the inrush current. The Figure 13 describes the auto-retry state machine.
5.3.3 Diagnostic
to VPWR fault is removed, the status register will be cleared after reading the register. The open output shorted to VPWR protection can be disabled through SPI (OS_DIS[0:1] bit). The 07XSC200 incorporates three dedicated OpenLoad detection circuitries on the output to detect in OFF and in ON state.
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5.3.3.1 OpenLoad Detection in Off State
The OFF output OpenLoad fault is detected when the output voltage is higher than VOLD(THRES) pulled up with internal current source (IOLD(OFF)) and reported as a fault condition when the output is disabled (OFF). The OFF Output OpenLoad fault is latched into the status register or when the internal gate voltage is pulled low enough to turn OFF the output. The OL_OFF[0:1] fault bit is set in the status register. If the OpenLoad fault is removed (FSB output pin goes to high), the status register will be cleared after reading the register. The OFF output OpenLoad protection can be disabled through SPI (OLOFF_DIS[0:1] bit).
5.3.3.2 OpenLoad Detection in On State
The ON output OpenLoad current thresholds can be chosen by the SPI to detect a standard bulbs or LEDs (OLLED[0:1] bit set to logic [1]). In the case where load current drops below the defined current threshold OLON bit is set to logic [1], the output stays ON and FSB is not disturbed.
5.3.3.3 OpenLoad Detectio n in On State For Led
OpenLoad for LEDs only (OLLED[0:1] set to logic [1]) is detected periodically each t OLLED (fully-on, D[6:0]=7F). To detect OLLED in fully-on state, the output must be ON at least t OLLED. To delatch the diagnosis, the condition should be removed and the SPI read operation is needed (OL_ON[0:1] bit). The ON output open-load protection can be disabled through the SPI (OLON_DIS[0:1] bit).
5.3.3.4 Analog Current Recopy and Temperature Feedbacks
The CSNS pin is an analog output reporting a current proportional to the designed output current or a voltage proportional to the temperature of the GND flag (pin #14). The routing is SPI programmable (TEMP_en, CSNS_en, CSNS_s[1,0] and CSNS_ratio_s bits). In case the current recopy is active, the CSNS output delivers current only during ON time of the output switch without overshoot. The maximum current is 2.0 mA, typical. The typical value of external CSNS resistor connected to the ground is 2.5 k. The current recopy is not active in Fail-safe mode.
5.3.3.5 Temperature Prewarning Detection
In Normal mode, the 07XSC200 provides a temperature prewarning reported via the SPI, in case the temperature of the GND flag is higher than TOTWAR. This diagnosis (OTW bit set to [1]) is latched in the SPI DIAGR0 register. To delatch, a read SPI command is needed.
5.3.4 Active Clamp ON VPWR
The device provides an active gate clamp circuit in order to limit the maximum transient VPWR voltage at VPWR(CLAMP). In case of an overload on an output, the corresponding output is turned off, which leads to high voltage at VPWR with an inductive VPWR line. When the VPWR voltage exceeds VPWR(CLAMP) threshold, the turn-off on the corresponding output is deactivated and all HS[0:1] outputs are switched ON automatically to demagnetize the inductive battery line.
5.3.5 Reverse Battery on VPWR
The output survives the application of reverse voltage as low as -18 V. Under these conditions, the ON resistance of the output is two times higher than a typical ohmic value in forward mode. No additional passive components are required except on the VDD current path.
Analog Integrated Circuit Device Data Freescale Semiconductor 35 07XSC200
5.3.6 Ground Disconnect Protection
In the event the 07XSC200 ground is disconnected from load ground, the device protects itself and safely turns OFF the output, regardless of the state of the output at the time of disconnection (maximum VPWR = 16 V). A 10 k resistor needs to be added between the MCU and each digital input pin to ensure the device turns off, during a ground disconnect and to prevent this pin from exceeding maximum ratings.
5.3.7 Loss of Supply Lines
5.3.7.1 Loss of V DD
If the external VDD supply is disconnected (or not within specification: VDD < VDD(FAIL), with the VDD_FAIL_en bit set to logic [1]), all SPI register content is reset. The outputs can still be driven by the direct inputs IN[0 : 1] if VPWR is within specified voltage range. The 07XSC200 uses the battery input to power the output MOSFET-related current sense circuitry and any other internal logic providing Fail-safe device operation with no VDD supplied. In this state, the overtemperature, overcurrent, severe short-circuit, short to VPWR and OFF OpenLoad circuitry are fully operational, with default values corresponding to all SPI bits are set to logic [0]. No current is conducted from VPWR to VDD.
5.3.7.2 Loss of V PWR
If the external VPWR supply is disconnected (or not within specification), the SPI configuration, reporting, and daisy chain features are provided for RSTB to set to logic [1] under VDD in nominal conditions. This fault condition can be diagnosed with UV fault in SPI STATR_s registers. The SPI pull-up and pull-down current sources are not operational. The previous device configuration is maintained. No current is conducted from VDD to VPWR.
5.3.7.3 Loss of V PWR and VDD
If the external VPWR and VDD supplies are disconnected (or not within specification: (VDD and VPWR) < VSUPPLY(POR)), all SPI register contents are reset, with default values corresponding to all SPI bits set to logic [0] and all latched faults reset.
5.3.8 EMC Performances
All following tests are performed on the Freescale evaluation board in accordance with the typical application schematic. The device is protected in the event of positive and negative transients on the VPWR line (per ISO 7637-2). The 07XSC200 successfully meets the Class 5 of the CISPR25 emission standard and 200 V/m or BCI 200 mA injection level for immunity tests.
5.4 Logic Commands and Registers
5.4.1 Serial Input Communication
SPI communication is accomplished using 16-bit messages. A message is transmitted by the MCU starting with the MSB D15 and ending with the LSB, D0 (Table 9). Each incoming command message on the SI pin can be interpreted using the following bit assignments: the MSB, D15, is the watchdog bit (WDIN). In some cases, output selection is done with bit D13. The next four bits, D14 -D12: D10, are used to select the command register. The remaining nine bits, D8 : D0, are used to configure and control the outputs and their protection features. Multiple messages can be transmitted in succession to accommodate those applications where daisy-chaining is desirable, or to confirm transmitted data, as long as the messages are all multiples of 16 bits. Any attempt made to latch in a message that is not 16 bits will be ignored. The 07XSC200 has defined registers, which are used to configure the device and to control the state of the outputs. Table 10 summarizes the SI registers.
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Table 9. SI Message Bit Assignment MSB D15 Watchdog in: toggled to satisfy watchdog requirements. D13 Register address bit used in some cases for output selection (Table 11). D14, D12 : D10 Register address bits. D9 Not used (set to logic [0]). LSB D8:D0 Used to configure the inputs, outputs, and the device protection features and SO status content. Table 10. Serial Input Address and Configuration Bit Map
0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 A 1 0 0 0 Xenon
s = Output selection with the bit A as defined in Table 11.
5.4.2 Device Register Addressing
The following section describes the possible register addresses (D[14:10]) and their impact on device operation.
5.4.2.1 Address XX000 — Status Register (STATR_s)
and CALR registers (Refer to Serial Output Communication (Device Status Return Data).
5.4.2.2 Address A 1A0001— Output PWM Control Register (PWMR_s)
independently selected for configuration based on the state of the D13 bit (Table 11). inrush and cooling responses are dedicated to 28 W lamps for HS[0,1] outputs. pulled down). Bits D6:D0 set the output PWM duty cycle to one of 128 levels for PWM_en is set to logic [1], as shown Table 6.
5.4.2.3 Address A 1A0010— Output Configuration Register (CONFR0_S)
independently selected for configuration based on the state of the D14 : D13 bits (Table 11). the output from direct control (in this case, the output is only controlled by the On bit). value [00] corresponds to the medium speed slew rate (Table 12). shown Table 7, (only available for PWM_en bit is set to logic [1]).
5.4.2.4 Address A 1A0011 — Output Configuration Register (CONFR1_s)
is independently selected for configuration based on the state of the D14 : D13 bits (Table 11). corresponds to enable auto-retry feature with time limitation. Table 11. Output Selection
0 HS0 (default)
Table 12. Slew Rate Speed Selection
11 N o t u s e d
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corresponds to enable this feature. corresponds to enable this feature (Table 13). corresponds to enable this feature. [0] corresponds to ON output OpenLoad detection is set for bulbs (Table 13).
5.4.2.5 Address A 1A0100 — Output Overcurrent Register (OCR)
is independently selected for configuration based on the state of the D14 : D13 bits (Table 11). A logic [1] on bit D8 (Xenon_s) disables enables the Xenon 55 W or 28 W bulb overcurrent profile, as described Figure 14. Table 13. ON OpenLoad Selection
1 X disable
Table 14. Current Sense Ratio Selection
0 CRS0 (default)
1 CRS1
Figure 14. Overcurrent Profile Depending on Xenon bit A logic [1] on bit D3 (OCHI_s bit) the OCHI1 level is replaced by OCHI2 during tOC1, as shown Figure 15. Table 15. Cooling Curve Selection Table 16. Inrush Curve Selection
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Figure 15. Overcurrent Profile with OCHI bit set to ‘1’ The wire harness is protected by one of four possible current levels in steady state, as defined in Table 17. Bit D0 (OC_mode_sel) allows to select the overcurrent mode, as described Table 18. The GCR register allows the MCU to configure the device through the SPI. HS[0:1] with PWMR register device in Fail-safe mode in case of VDD < VDD(FAIL). with PWMR register (the direct input states are ignored). Bit D6 (CLOCK_sel) allows to select the clock used as reference by PWM module, as described in the following Table 19. Bits D5:D4 allow the MCU to select one of two analog feedback on CSNS output pin, as shown in Table 20. Table 17. Output Steady State Selection
01 O C L O 3
10 O C L O 4
11 O C L O 1
Table 18. Overcurrent Mode Selection
0 X PWM module disabled (default)
The GCR register disables the overvoltage protection (D0). When this bits is [0], the overvoltage is enabled (default value).
5.4.2.6 Address 00111 — Calibration Register (CALR)
The CALR register allows the MCU to calibrate internal clock, as explained in Figure 13.
5.4.3 Serial Output Communicatio n (Device Status Return Data)
dependent upon the previously written SPI word. status register is now able to accept new fault status information. registers which are output specific; viz., Fault, PWMR, CONFR0, CONFR1, and OCR registers. write until changed with an updated STATR write.
- The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid SPI communication never occurred
- T h e VPWR voltage is below 4.0 V, the status must be ignored by the MCU
5.4.4 Serial Output Bit Assignment
summarizes SO returned data for bits OD15 : OD0.
- Bit OD15 is the MSB; it reflects the state of the watchdog bit from the previously clocked-in message
- Bits OD14:OD10 reflect the state of the bits SOA4 : SOA0 from the previously clocked in message
- Bit OD9 is set to logi c [1] in Normal mode (NM)
- The contents of bits OD8 : OD0 depend on bits D4 : D0 from the most recent STATR command SOA4 : SOA0 as explained in the paragraphs following Table 22
Table 20. CSNS Reporting Selection Table 21. Output Current Recopy Selection
10 H S 0
11 H S 1
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5.4.4.1 Previous Address SOA4 : SOA0 = 1A000 (STATR_s)
- OC_s: overcurrent fault detec tion for a selected output,
- SC_s: severe short-circuit fault detection for a selected output,
- OS_s: output shorted to VPWR fa ult detection for a selected output,
- OLOFF_s: OpenLoad in OFF state fault detection for a selected output,
Table 22. Serial Output Bit Map Description
- OLON_s: OpenLoad in ON state fault detection (depending on cu rrent level threshold: bulb or LED) for a selected output,
- OV: overvoltage fault detection,
- UV: undervoltage fault detection
- POR: power on reset detection. The FSB pin reports all faults. For latched faults, this pin is reset by a new Switch OFF command (toggling fault_control signal).
5.4.4.2 Previous Address SOA4 : SOA0 = 1A001 (Pwmr_s)
The returned data contains the programmed values in the PWMR register for the output selected with A.
5.4.4.3 Previous Address SOA4 : SOA0 = 1A010 (confr0_s)
The returned data contains the programmed values in the CONFR0 register for the output selected with A.
5.4.4.4 Previous Address SOA4 : SOA0 = 1A011 (confr1_s)
The returned data contains the programmed values in the CONFR1 register for the output selected with A.
5.4.4.5 Previous Address SOA4 : SOA0 = 1A100 (ocr_s)
The returned data contains the programmed values in the OCR register for the output selected with A.
5.4.4.6 Previous Address SOA4 : SOA0 = 00101 (gcr)
The returned data contains the programmed values in the GCR register.
5.4.4.7 Previous Address SOA4 : SOA0 = 00111 (diagr0)
The returned data OD2 reports logic [1] in case of PWM clock on CLOCK pin is out of specified frequency range. The returned data OD1 reports logic [1] in case of calibration failure. The returned data OD0 reports logic [1] in case of overtemperature prewarning (temperature of GND flag is above TOTWAR).
5.4.4.8 Previous Address SOA4 : SOA0 = 01111 (diagr1)
The returned data OD4: OD3 report in real time the state of the direct input IN[1:0]. of Fail-safe state due to watchdog time-out as explained in the following Table 23.
5.4.4.9 Previous Address SOA4 : SOA0 = 10111 (diagr2)
The returned data is the product ID. Bits OD2:OD0 are set to 010 for Protected Dual 7.0 m high side Switches. Table 23. Watchdog activation report
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5.4.4.10 Default Device Configuration
The default device configuration is explained by the following:
- HS output is commanded by the corresponding IN input or On bit through the SPI. The medium slew-rate is used,
- HS output is fully protected by the Xenon overcurrent profile by default, the severe short-circuit protection, the undervoltage and the overtemperature protection. The auto-retry feature is enabled,
- OpenLoad in ON and OFF state and HS shorted to V PWR detections are available,
- No current recopy and no anal og temperature feedback active,
- Overvoltage protection is enabled,
- SO reporting fault status must be ignored,
- V DD failure detection is disabled.
Analog Integrated Circuit Device Data Freescale Semiconductor 45 07XSC200
6 Typical Applications
The following figure shows a typical lighting application (only one vehicle corner) using an external PWM clock from the main MCU. A redundancy circuitry has been implemented to substitute light control (from MCU to watchdog) in case of a Fail-safe condition. It is recommended to locate a 22 nF decoupling capacitor to the module connector. SPDL07 SOIC I/O VDD VDD VPWR GND MCU Voltage regulator VPWR HS0 HS1 VDD WAKE FSB CLOCK IN1 SCLK CSB SI SO FSI RSTB IN0 100 nF I/O I/O SCLK CSB SI SO 10 k 10 k 10 k 10 k 10 k 10 k 2.5 k 10 k LOAD 0 LOAD 1 CSNSA/D VDD VDD VPWRVDD 22 nF 22 nF 22 nF 10 k Watchdog direct light commands (pedal, comodo,...) VPWR ignition switch 100 nF 10 µF100 nF10 µF100 nF 100 nFVPWR
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7 Packaging
7.1 Soldering Information
The 07XSC200 is packaged in a surface mount power package intended to be soldered directly on the printed circuit board. The 07XSC200 was qualified in accordance with JEDEC standards J-STD-020C Pb-Free reflow profile. The maximum peak temperature during the soldering process should not exceed 260 °C for 40 seconds maximum duration.
Analog Integrated Circuit Device Data Freescale Semiconductor 47 07XSC200
7.2 Package Dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.freescale.com and perform a keyword search for the drawing’s document number. Package Suffix Package Outline Drawing Number 32-Pin SOICW EK 98ASA00368D EK SUFFIX 32-PIN SOICW 98ASA00368D REV. 0
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REV. 0
Analog Integrated Circuit Device Data Freescale Semiconductor 49 07XSC200 EK SUFFIX 32-PIN SOICW 98ASA00368D REV. 0
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8 Revision History
Revision Date Description of Changes 1.0 8/2013 • Initial release based on MC07XS3200 data sheet. 2.0 9/2013 • Added the note “To achieve high reliability over 10 years of continuous operation, the device's continuous operating junction temperature should not exceed 125C.” to Operating Temperature
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