06XSD200

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Technical content

Features

• Normal operating range: 8.0 - 36 V, extended range: 6.0 - 58 V, 3.3 V and 5.0 V compatible 16-bit SPI port for device control, configuration, and diagnostics at rates up to 8.0 MHz
• Two fully-protected 6.0 m (@ 25 °C) high side switches
• U p t o 9 . 0 A steady-state current per channel
• Separate bulb and DC motor latched overcurrent handling
• Parallel output operating m ode with improved switching synchronization
• Individually programmable internal/external PWM clock signals (switching frequency, duty cycle, slew rate, switch-on time-shift)
• Overcurrent, short-circuit, and overtemperature protection with programmable auto-retry functions
• Accurate temperature and current sensing (high/low sensing ratios/offset compensation)
• OpenLoad detection (channel in OFF and ON state), also for LED applications (7.0 mA typ.)

Figure 1. Simplified Application Diagram

23 PIN PQFN (12 X12 mm)

ORDERING INFORMATION

Range (TA) Package MC06XSD200FK - 40 to 125 °C 23 PQFN HIGH SIDE SWITCH MCU VDD CLOCK FSB SCLK CSB SO RSTB SI IN0 IN1 CSNS GND VDD VPWR HS0 HS1 LOAD I/O SCLK CSB SI I/O SO I/O I/O A/DGND LOADM CONF0 CONF1 FSOBI/O A/D SYNC I/O 06XSD200 VDD VPWR

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Figure 2. Internal Block Diagram

Analog Integrated Circuit Device Data Freescale Semiconductor 3 06XSD200 TABLE OF CONTENTS TABLE OF CONTENTS

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Figure 3. Device Pin Assignments Table 1. 06XSD200 Pin Assignments

1 CSNS Output Output Current/

down resistor must be connected between CSNS and GND.

4 FSOB Output Fail-safe Output

7 FSB Output Fault Status

8 CLOCK Input PWM Clock The clock input gives the time-base when the device is operated in external

This pin has an internal pull-down current source. 9 RSTB Input Reset This input pin is used to initialize the device’s configuration - and fault registers. internal pull-down resistor.

10 CSB Input Chip Select

controller. CSB is internally pulled up to VDD by a current source IUP.

12 SI Input Serial Input This input pin receives the SPI input data from an external device

(microcontroller or another extreme switch device in case of daisy-chaining). 13 VDD Power Digital Drain Voltage This is the positive supply pin of the SPI interface.

16 SO Output Serial Output This output pin transmits SPI data to an external device (external

microcontroller or the SI pin of the next SPI device in case of daisy-chaining). circuitry. It is recommended to also connect these pins on the PCB. connected to them. Pin 15 is the device’s primary thermal pad. Output Power Switch Outputs Output pins of the switches, to be connected to the load.

23 SYNC Output Output Current

Table 1. 06XSD200 Pin Assignments (continued)

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ELECTRICAL CHARACTERISTICS

Table 2. Maximum Ratings All voltages are relative to ground unless mentioned otherwise. Exceeding these ratings may cause permanent damage.

1. Concerned Input pins are: CONF[0:1], RSTB, SI, SCLK, Clock, and CSB.
2. Concerned Output pins are: CSNS, SYNC, and FSB.
3. Output current rating valid as long as ma ximum junction temperature is not exceeded. For computation of the maximum allowable output
4. Single pulse Energy dissipation, Single-pulse short-circuit method (LL = 2.0 mH, R = 30 mVPWR = 28 V, TJ = 150 C initial).
5. Dissipation during repetitive cycl es: switch off upon short-circuit (LL = 20 µH, R = 200 mVPWR = 28 V, TJ = 125 C initial, fS<2.0 Hz).
6. Dissipation during repetitive cycle s: switch off upon short-circuit (LL = 40 µH, R = 400 mVPWR = 28 V, TJ = 125 C initial, fS<2.0 Hz).
7. ESD testing is performed in accordance with the Human Body Model (HBM) (C ZAP = 100 pF, RZAP = 1500 ), and the Charge Device

Model (CDM), Robotic (CZAP = 4.0 pF).

Analog Integrated Circuit Device Data Freescale Semiconductor 7 06XSD200 Operating Temperature (8) Ambient Junction TA TJ - 40 to 125 - 40 to 150 Storage Temperature TSTG - 55 to 150 C Thermal Resistance / Junction to Case RJC <1.0 C/ W Reflow Peak Temperature on device pins during soldering(9), (10) TSOLDER 260 C Notes: 8. To achieve high reliability ov er 10 years of continuous operation, the device's continuous operating junction temperature should not exceed 125 C. 9. 10 seconds maximum duration. Not designed for immersion solder ing. Exceeding these limits may cause malfunction or permanent damage to the device. MSL level is specified later. 10. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. Table 2. Maximum Ratings (continued) All voltages are relative to ground unless mentioned otherwise. Exceeding these ratings may cause permanent damage.

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STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics average values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.

8.0 MHz SPI Communication(12)

1. In extended mode, availability of several device functions (channel control, value of RDS(ON), overtemperature protection) is guaranteed,

shutdown). Above VPWR(OV), the channels can only be turned ON when the overvoltage detection function has been disabled.

1. Typical value guaranteed per design.
2. When the device recovers from undervoltage and returns to normal mode (6.0 V < VPWR < 58 V) before the end of the auto-retry period

(Latchable Fault) and EMC Performances).

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STATIC ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS OF THE OUTPUT STAGE (HS0 AND HS1) ON-Resistance, Drain-to-Source (IHS = 3.0 A, TJ = 25 °C) CSNS_ratio = 0 VPWR = 8.0 V VPWR = 28 V VPWR = 36 V RDS(ON)25 6.0 6.0 6.0 ON-Resistance, Drain-to-Source (IHS = 3.0 A,TJ = 150 °C) CSNS_ratio = 0 VPWR = 8.0 V VPWR = 28 V VPWR = 36 V RDS(ON)150 ON-Resistance, Drain-to-Source difference from one channel to the other in parallel mode (IHS = 1.0 A,TJ = 150 °C) CSNS_ratio = X RDS(ON)150 -0.7 – +0.7 m ON-Resistance, Source-Drain (IHS = -3.0 A, TJ = 150 °C, VPWR = -24 V) RSD(ON)150 – – 12 m Max. detectable wiring length (2.5 mm²) for severe short-circuit detection (see Severe Short-circuit Fault (latchable fault)): High slew rate selected Medium slew rate selected: Low slew rate selected: LSHORT 100 200 170 340 cm Overcurrent Detection thresholds with CSNS_ratio bit = 0 (CSR0) I_OCH1_0 I_OCH2_0 I_OCM1_0 I_OCM2_0 I_OCL1_0 I_OCL2_0 I_OCL3_0 90.0 58.3 36.1 22.2 15.0 10.0 5.0 110.0 70.0 43.3 26.7 18.0 12.0 6.0 128.3 81.7 50.6 31.1 21.0 14.0 7.0 A Overcurrent Detection thresholds with CSNS_ratio bit = 1(CSR1) I_OCH1_1 I_OCH2_1 I_OCM1_1 I_OCM2_1 I_OCL1_1 I_OCL2_1 I_OCL3_1 30.6 19.4 12.0 7.4 5.0 3.3 1.6 36.7 23.3 14.4 8.9 6.0 4.0 2.0 42.8 27.2 16.9 10.4 7.0 4.7 2.4 A Output (HS[x]) leakage Current in sleep state (positive value = outgoing) VHS,OFF = 0 V (VHS,OFF = output voltage in OFF state) VHS,OFF = VPWR, device in sleep state (VPWR = 24 V) IOUT_LEAK -40.0 +16 +5.0 µA Switch Turn-on threshold for supply overvoltage (VPWR -GND) VD_GND(CLAMP) 58 – 66 V Switch turn-on threshold for drain-source overvoltage (@ IHS = 100 mA) VDS(CLAMP) 58 – 66 V Switch turn-on threshold for Drain-Source overvoltage difference from one channel to the other in parallel mode (@ IHS = 100 mA) VDS(CLAMP) -2.0 – +2.0 V Table 3. Static Electrical Characteristics (continued) average values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.

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STATIC ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS OF THE OUTPUT STAGE (HS0 AND HS1) (CONTINUED) Current Sensing Ratio(14) CSNS_ratio bit = 0 (high-current mode) CSNS_ratio bit = 1 (low-current mode) CSR0 CSR1 1/1666.6 Minimum measurable load current with compensated error(15) < 35% I_LOAD_MIN – – 175 mA CSNS leakage current in OFF state (CSNSx_en = 0, CSNS_ratio bit_x = 0) ICSR_LEAK -4.0 – +4.0 µA Systematic offset error (see Current Sense Errors) I_LOAD_ERR_SYS – 15 – mA Random offset error I_LOAD_ERR_RAND -360 – 360 mA CSNS pin current sourcing capability, absolute upper limit ICSNS,MAX 5.15 – – mA ESR0 Output Current Sensing Error (%, uncompensated(16)) at output Current level (Sense ratio CSR0 selected): TJ=-40 C 9.0 A 4.5 A 2.25 A 1.13 A TJ=125C 9.0 A 4.5 A 2.25 A 1.13 A TJ=25 to 125C 9.0 A 4.5 A 2.25 A 1.13 A ESR0_ERR -13 -12 -17 -31 -10 -9.0 -12 -19 -10 -9.0 -12 -22 9.0 9.0 Notes: 14. Current Sense Ratio C SRx = ICSNS / (IHS[x] +I_LOAD_ERR_SYS) 15. See note (16), but with ICSNS_MEAS obtained after compensation of I_LOAD_ERR_RAND (see Activation and Use of Offset Compensation). Further accuracy improvements can be obtained by performing a 1 or 2 point calibration 16. E SRx_ERR=(ICSNS_MEAS / ICSNS_MODEL) -1, with ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRx , (I_LOAD_ERR_SYS defined above, see section Current Sense Error Model). With this model, load current becomes: I(HS[x]) = ICSNS / CSRx - I_LOAD_ERR_SYS average values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 06XSD200 STATIC ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS OF THE OUTPUT STAGE (HS0 AND HS1) (CONTINUED) ESR0 Output Current Sensing Error (%, after offset compensation(17)) at output Current level (Sense ratio CSR0 selected): TJ=-40 C 9.0 A 4.5 A 2.25 A 1.13 A TJ=125C 9.0 A 4.5 A 2.25 A 1.13 A TJ=25 to 125C 9.0 A 4.5 A 2.25 A 1.13 A ESR0_ERR(Comp) -10 -10 -10 -10 -9.0 -8.0 -9.0 -9.0 -9.0 -8.0 -9.0 -9.0 9.0 8.0 9.0 9.0 9.0 8.0 9.0 9.0 ESR1 Output Current Sensing Error (%, uncompensated (18)) at output Current level (Sense ratio CSR1 selected): TJ=-40 C 2.25 A TJ=125C 2.25 A TJ=25 to 125C 2.25 A ESR1_ERR -16 -12 -12 Notes: 17. See note (16), but with ICSNS_MEAS obtained after compensation of I_LOAD_ERR_RAND (see Activation and Use of Offset Compensation). Further accuracy improvements can be obtained by performing a 1 or 2 point calibration 18. E SRx_ERR=(ICSNS_MEAS / ICSNS_MODEL) -1, with ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRx , (I_LOAD_ERR_SYS defined above, see section Current Sense Error Model). With this model, load current becomes: I(HS[x]) = ICSNS / CSRx - I_LOAD_ERR_SYS average values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.

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STATIC ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS OF THE OUTPUT STAGE (HS0 AND HS1) (CONTINUED) ESR1 Output Current Sensing Error (% after offset compensation(19)) at output Current level (Sense ratio CSR1 selected): TJ=-40 C 2.25 A 0.75 A 0.375 A 0.225 A TJ=125C 2.25 A 0.75 A 0.375 A 0.225 A TJ=25 to 125C 2.25 A 0.75 A 0.375 A 0.225 A ESR1_ERR(Comp) -10 -11 -18 -29 -8.0 -10 -12 -16 -8.0 -10 -13 -21 8.0 8.0 ESR0 Output Current Sensing Error in parallel mode  (%, uncompensated(20)) at outputs Current level (Sense ratio CSR0 selected): TJ=-40 C

9.0 A (per channel)

4.5 A (per channel)

TJ=125C TJ=25 to 125C ESR0_ERR_PAR -10 -11 -8.0 -8.0 -8.0 -8.0 8.0 8.0 8.0 8.0 Notes: 19. See note (20), but with ICSNS_MEAS obtained after compensation of I_LOAD_ERR_RAND (see Activation and Use of Offset Compensation). Further accuracy improvements can be obtained by performing a 1 or 2 point calibration. 20. E SRx_ERR=(ICSNS_MEAS / ICSNS_MODEL) -1, with ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRx , (I_LOAD_ERR_SYS defined above, see section Current Sense Error Model). With this model, load current becomes: I(HS[x]) = ICSNS / CSRx - I_LOAD_ERR_SYS average values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.

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STATIC ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS OF THE OUTPUT STAGE (HS0 AND HS1) (CONTINUED) Current Sense Clamping Voltage (condition: R(CSNS) > 10 kOhm) VCL(CSNS) 5.5 – 7.5 V OpenLoad detection Current threshold in OFF state (21) IOLD(OFF) 30 – 100 A OpenLoad Fault Detection Voltage Threshold (21) VOLD(THRES) 4.0 – 5.5 V OpenLoad detection Current threshold in ON state (see OpenLoad Detection In On State (OL_ON)): CSNS_ratio bit = 0 CSNS_ratio bit = 1 (fast slew rate SR[1:0] = 10 mandatory for this function) IOLD(ON) 135 5.0 500.0 7.0 999.9 mA Time period of the periodically activated OpenLoad in ON state detection for CSNS_ratio bit = 1 tOLLED 105 150 195 ms Output Shorted-to-VPWR Detection Voltage Threshold (channel in OFF state) VOSD(THRES) VPWR-1.2 VPWR-0.8 VPWR-0.4 V Switch turn-on threshold for Negative Output Voltages (protects against negative transients) - (measured at I OUT = 100 mA, Channel in OFF state) VCL -35 – -24 V Switch turn-on threshold for Negative Output Voltages difference from one channel to the other in parallel mode - (measured at I OUT = 100 mA, Channel in OFF state) VCL -2.0 – +2.0 V Switching State (On/Off) discrimination thresholds VHS_TH 0.45*VPWR 0.5*VPWR 0.55*VPWR V Shutdown temperature (Power MOSFET junction; 6.0 V < VPWR < 58 V) TSD 160 175 190 C Notes: 21. Minimum required value of OpenLoad impedance for detection of OpenLoad in OFF-state: 200 k.(VOLD(THRES) = VHS @ IOLD(OFF)) average values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.

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STATIC ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS OF THE CONTROL INTERFACE PINS Logic Input Voltage, High(22) VIH 2.0 – 5.5 V Logic Input Voltage, Low(22) VIL -0.3 – 0.8 V Wake-up Threshold Voltage (IN[0:1] and RSTB)(23) VWAKE 1.0 – 2.2 V Internal Pull-down Current Source (on Inputs: CLOCK, SCLK and SI)(24) IDWN 5.0 – 20 A Internal Pull-up Current Source (input CSB)(25) IUP_CSB 5.0 – 20 A Internal Pull-up Current Source (input CONF[0:1])(26) IUP_CONF 25 – 100 A Capacitance of SO, FSB and FSOB pins in Tri-state CSO – – 20 pF Internal Pull-down Resistance (RSTB and IN[0:1]) RDWN 125 250 500 k Input Capacitance(27) CIN – 4.0 12 pF ELECTRICAL CHARACTERISTICS OF THE CONTROL INTERFACE PINS (CONTINUED) SO High-state Output Voltage (IOH = 1.0 mA) VSOH VDD-0.4 – – V SYNC, SO, FSOB and FSB Low-state Output Voltage (IOL = -1.0 mA) VSOL – – 0.4 V SYNC, SO, CSNS, FSOB and FSB Tri-state Leakage Current: (0 V < V(SO) < VDD, or V(FS) or V(SYNC) = 5.5 V, or V(FSO) = 36 V or V(CSNS) = 0 V) ISO(LEAK) - 2.0 0 2.0 CONF[0:1]: Required values of the External Pull-down Resistor Lighting applications DC motor applications RCONF 1.0 Infinite Notes 22. High and low voltage ranges apply to SI, CSB, SCLK, RSTB, IN [0:1] and CLOCK input signals. The IN[0:1] signals may be derived from VPWR and can tolerate voltages up to 58 V. 23. Voltage above which the device wakes up 25. Valid for V CSB < 2.0 V. CSB has an internal pull-up current source derived from VDD 26. Pins CONF[0:1] are connected to an internal current source, derived from an internal voltage regulator (VREG ~ 3.0 V). 27. Input capacitance of SI, CSB, SCLK, RSTB, IN[0:1], CONF[0:1 ], and CLOCK pins. This parameter is guaranteed by the manufacturing process but is not tested in production. average values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.

Analog Integrated Circuit Device Data Freescale Semiconductor 15 06XSD200 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics average values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.

16 V < VPWR < 36 V

1. Rising and Falling edge slew rates specified for a 20% to 80% voltage variation on a 10.0 resistive load (see Figure 4).
2. Turn-on delay time measured as delay between a rising edge of the channel control signal (IN[0 : 1] = 1) and the associated rising edge

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DYNAMIC ELECTRICAL CHARACTERISTICS SWITCHING CHARACTERISTICS (CONTINUED) Delay time difference from one channel to the other in parallel mode(30) SR[1:0] = 00 SR[1:0] = 01 SR[1:0] = 10 t(DLY) -25 -50 -12 0.0 0.0 0.0 Fault Detection Delay Time(31) tFAULT – 5.0 8.0 s Output Shutdown Delay Time(32) tDETECT – 12.0 17 s Current sense output settling Time for SR[1:0] = 00 (medium slew rate) VPWR = 28 V (33)

16 V < VPWR < 36 V (34)

t CSNSVAL_00 0.0 104 250 Current sense output settling Time for SR[1:0] = 01(low slew rate) VPWR = 28 V (33) t CSNSVAL_01 0.0 167 355 Current sense output settling Time for SR[1:0] = 10 (high slew rate) VPWR = 28 V (33) t CSNSVAL_10 0.0 210 SYNC output signal delay for SR[1:0] = 00 (medium SR) (34) t SYNCVAL_00 50 - 160 s SYNC output signal delay for SR[1:0] = 01 (low SR)(34) t SYNCVAL_01 80 - 320 s SYNC output signal delay for SR[1:0] = 10 (high SR) (34) t SYNCVAL_10 22 - 80 s Recommended sync_to_read delay SR[1:0] = 00 (medium slew rate) (34) t SYNREAD_00 0.0 - 200 µs Recommended sync_to_read delay SR[1:0] = 01 (low slew rate) (34) t SYNREAD_01 0.0 - 300 µs Recommended sync_to_read delay SR[1:0] = 10 (high slew rate) (34) t SYNREAD_10 0.0 - 200 µs Upper overcurrent threshold duration tOCH1 tOCH2 6.0 12.0 8.6 17.2 11.2 22.4 ms Medium overcurrent threshold duration (CONF = 0; Lighting Profile) tOCM1_L tOCM2_L 137 178 ms Medium overcurrent threshold duration (CONF = 1; DC motor Profile) tOCM1_M tOCM2_M 150 301 214 429 278 557 ms FREQUENCY & PWM DUTY CYCLE RANGES (35)(protections fully operational, see Protective Functions) Switching Frequency range - Direct Inputs fCONTROL 0.0 – 1000 Hz Switching Frequency range - External clock with internal PWM (recommended) fPWM_EXT 20 – 1000 Hz Notes: 30. Rising and Falling edge slew rates specified for a 20% to 80% voltage variation on a 10.0 resistive load (see Figure 4). 31. Time required to detect and report the fault to the FSB pin. 32. Time required to switch off the channel after detection of over temperature (OT), overcurrent (OC), SC or UV error (time measured between start of the negative edge on the FSB pin and the falling edge on the output voltage until V(HS[0:1)) = 50% of VPWR 33. Typical value given for a 70  resistive load for CSNS_RATIO_s = 1 34. Settling time ( = t CSNSVAL_XX), SYNC output signal delay ( = t SYNCVAL_XX) and Read-out delay ( = t SYNREAD_XX) are defined for a stepped load current using a 10  resistive load for CSNS_RATIO_s = 0. (see Figure 9 and Output Current Monitoring (CSNS)). 35. In Direct Input mode, the lower frequency limit is 0 Hz with RSTB=5.0 V and 4.0 Hz with RSTB=0V. Duty-cycle applies to instants at which VHS = 50 % VPWR. For low duty-cycle values, the effective value also depends on the value of the selected slew rate. Table 4. Dynamic Electrical Characteristics (continued) average values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.

Analog Integrated Circuit Device Data Freescale Semiconductor 17 06XSD200 DYNAMIC ELECTRICAL CHARACTERISTICS FREQUENCY & PWM DUTY CYCLE RANGES (CONTINUED) (36)(protections fully operational, see Protective Functions) Switching Frequency range - Internal clock with internal PWM (recommended) fPWM_INT 60 – 1000 Hz Duty Cycle range RCONTROL 0.0 – 100 % AVAILABILITY DIAGNOSTIC FUNCTIONS OVER DUTY-CYCLE AND SWITCHING FREQUENCY (PROTECTIONS & DIAGNOSTICS BOTH FULLY OPERATIONAL, SEE DIAGNOSTIC FEATURES FOR THE EXACT BOUNDARY VALUES) Available Duty Cycle Range, fPWM = 1.0 kHz high slew rate, PWM mode(37) OL_OFF OL_ON OS RPWM_1K_H 0.0 0.0 100 Available Duty Cycle Range, fPWM = 400 Hz, medium slew rate, PWM mode(37) OL_OFF OL_ON OS RPWM_400_M 0.0 0.0 100 Available Duty Cycle Range, fPWM = 400 Hz, high slew rate, PWM mode(37) OL_OFF OL_ON OS RPWM_400_H 0.0 0.0 100 Available Duty Cycle Range, fPWM = 200 Hz, low slew rate mode, PWM mode(37) OL_OFF OL_ON OS RPWM_200_L 0.0 0.0 100 Available Duty Cycle Range, fPWM = 200 Hz, medium slew rate, PWM mode(37) OL_OFF OL_ON OS RPWM_200_M 0.0 0.0 100 Available Duty Cycle Range, fPWM = 100 Hz in low slew rate, PWM mode(37) OL_OFF OL_ON OS RPWM_100_L 0.0 8.0 0.0 100 Deviation of the internal clock PWM frequency after Calibration(38) AFPWM(CAL) -10 – +10 % Default output frequency when using an uncalibrated oscillator fPWM(0) 280 400 520 Hz Minimal required Low Time during Calibration of the Internal Clock through CSB t CSB(MIN) 1.0 1.5 2.0 s Maximal allowed Low Time during Calibration of the Internal Clock through CSB t CSB(MAX) 70 100 130 s Recommended external Clock Frequency Range (external clock/PWM Module) fCLOCK 15 – 512 kHz Upper detection threshold for external clock frequency monitoring f CLOCK(MAX) 512 730 930 kHz Lower detection threshold for external clock frequency monitoring f CLOCK(MIN) 5.0 7.0 10 kHz Notes 36. In Direct Input mode, the lower frequency limit is 0 Hz with RSTB=5.0 V and 4.0 Hz with RSTB=0V. Duty-cycle applies to instants at which VHS = 50 % VPWR. For low duty-cycle values, the effective value also depends on the value of the selected slew rate. 37. Actually, the device can be operated outsi de the specified duty cycle and frequency ranges (basic protective functions OC, SC, UV, OV, OT remain active) but the availability of the diagnostic functions OL_ON, OL_OFF, OS is affected. 38. Values guaranteed from 60 Hz to 1.0 kHz (recommended switching frequency range for internal clock operation). average values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.

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DYNAMIC ELECTRICAL CHARACTERISTICS TIMING: SPI PORT, IN[0]/ IN[1] SIGNALS & AUTORETRY Required Low time allowing delatching or triggering sleep mode (direct input mode) tIN 175 250 325 ms Watchdog Timeout for entering Fail-safe Mode due to loss of SPI contact(39) t WDTO 217 310 400 ms Auto-Retry Repetition Period (when activated): Auto_period bits = 00 Auto_period bits = 01 Auto_period bits = 10 Auto_period bits = 11 tAUTO_00 tAUTO_01 tAUTO_10 tAUTO_11 105 52.5 26.2 13.1 150 37.5 17.7 195 97.5 47.8 24.4 ms GND PIN TEMPERATURE SENSING FUNCTION Thermal Prewarning Detection Threshold(40) TOTWAR 110 125 140 °C Temperature Sensing output voltage @ TA = 25 °C (470  < RCSNS < 10 k TFEED 918 1078 1238 mV Gain Temperature Sensing output @ TA = 25 °C (470  < RCSNS < 10 k(40) DTFEED 10.7 11.1 11.5 mV/°C Temperature Sensing Error, range [-40 °C, 150 °C], default(40) TFEED_ERROR -15 – +15 °C Temperature Sensing Error, [-40 °C, 150 °C] after 1 point calibration @ 25 °C(40) TFEED_ERROR_ CAL -5.0 – +5.0 °C Notes 39. Only when the WD_dis bit set to logic [0] (default). Watc hdog timeout defined from the rising edge on RST to rising edge HS[0,1] 40. Values were obtained by lab characterization. average values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.

Analog Integrated Circuit Device Data Freescale Semiconductor 19 06XSD200 DYNAMIC ELECTRICAL CHARACTERISTICS SPI INTERFACE ELECTRICAL CHARACTERISTICS(41) Maximum Operating Frequency of the Serial Peripheral Interface (SPI)(42) f SPI – – 8.0 MHz Required Low-state Duration for reset RSTB(43) t WRSTB 10 – – s Required duration from the Rising to the Falling Edge of CSB (Required Setup Time)(44) t CSB 1.0 – – s Rising Edge of RSTB to Falling Edge of CSB (Required Setup Time)(44) t ENBL 5.0 – – s Falling Edge of CSB to Rising Edge of SCLK (Required Setup Time)(44) t LEAD 500 – – ns Falling Edge of SCLK to Rising Edge of CSB (Required Setup lag Time)(44) t LAG 60 – – ns Required High State Duration of SCLK (Required Setup Time)(44) t WSCLKh 50 – – ns Required Low State Duration of SCLK (Required Setup Time)(44) t WSCLKl 50 – – ns SI to Falling Edge of SCLK (Required Setup Time)(45) t SI (SU) 15 – – ns Falling Edge of SCLK to SI (Required hold Time of the SI signal)(45) t SI (H) 30 – – ns SO Rise Time CL = 80 pF t RSO – – 20 ns SO Fall Time CL = 80 pF t FSO – – 20 ns SI, CSB, SCLK, Max. Rise Time allowing operation at fSPI = 8.0 MHz(45) t RSI – – 11 ns SI, CSB, SCLK, Max. Fall Time allowing operation at fSPI = 8.0 MHz(45) t FSI – – 11 ns Time from Rising Edge of SCLK to reach a valid level at the SO pin(46) tVALID – – 44 ns Time from Falling Edge of CSB to reach low-impedance on SO (access time)(47) t SOEN – – 30 ns Time from Rising Edge of CSB to reach high-impedance on SO pin (turn off time) t SODIS 30 ns Notes: 41. Parameters guaranteed by design. It is recommended to tie unused SPI-pins to GND by resistors 1.0 k <R <10 k 42. For clock frequencies > 4.0 MHz, series resistors on the SPI pins should preferably be removed. Otherwise, 470 pF (VMAX. > 40 V) ceramic speed-up capacitors in parallel with the >8.0 k input resistors are required on pins SCLK, SI, SO, CS 43. RSTB low duration is defined as the minimum time required to switch off the channel when previously put ON in SPI mode (direct inputs inactive). 44. Minimum setup time required for the device is the minimum requi red time that the microcontroller must wait or remain in a given state. 45. Rise and Fall time of incoming SI, CSB, and SCLK signals. 46. Time required for output data to be avail able for use at SO, measured with a 80 pF capacitive load. 47. Time required for output data to be terminat ed at SO measured without a series resistorconnected CSB. average values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.

Analog Integrated Circuit Device Data

20 Freescale Semiconductor

Figure 4. Output Voltage Slew Rate and Delay Figure 5. Overcurrent Protection Profile for Bulb Applications Bulb profile: CONFs = 0 (V (pin 5/6) <0.8 V). Static Overcurrent protection profile activated once per turn-on.

Analog Integrated Circuit Device Data

22 Freescale Semiconductor

Figure 8. Timing Diagram for Serial Output (SO) Data Communication Figure 9. Synchronous & Track-and-Hold Current Sensing Modes: Associated Delay & Settling Times

Analog Integrated Circuit Device Data Freescale Semiconductor 23 06XSD200 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 06XSD200 is a two-channel, high side switch that can sustain up to 36 V, with integrated control and diagnostics designed for industrial applications. The device provides a high number of protective functions. Both low RDS(ON) channels (<6.0 m) can independently drive various load types like light bulbs, solenoid actuators, or DC motors. Device control and diagnostics are configured through a 16-bit SPI port with daisy chain capability. Independently programmable output voltage slew rates allow satisfying electromagnetic compatibility (EMC) requirements. Both channels can independently be operated in several different switching modes: internal clock, internal PWM mode (fully autonomous operation), external clock, and direct control switching mode. Current sensing with an adjustable ratio is available on both channels, allowing both high current (bulbs) and low current (LED) monitoring. By activating the Track & Hold mode, current monitoring can be performed during the switch-Off phase. This allows random access to the current sense functionality. A patented offset compensation technique further enhances current sense accuracy. To avoid turning off during inrush current, while being able to monitor it, the device features a dynamic overcurrent threshold profile. For bulbs, this profile is a stair function with stages of which the height and width are programmable through the SPI port. DC motors can be protected from overheating by activating a specific window-shaped overcurrent profile that allows stall currents of limited duration. Whenever communication with the external micro- controller is lost, the device enters Fail-safe Operation mode, but remains operational, controllable and protected. PIN ASSIGNMENT AND FUNCTIONS Functions and register bits that are implemented independently for both channels have extension “_s”. Max. ratings of the pins are given in Table 2. OUTPUT CURRENT MONITORING (CSNS) The CSNS pin allows independent current monitoring of channel 0 or channel 1 up to the steady-state overcurrent threshold. It can also be used to sense the device temperature. The different functions are selected by setting bits CSNS1_en and CSNS0_en to the appropriate value Table 11). When the CSNS pin is sensed during switch-off in the (optional) track & hold mode, it outputs the scaled value of the load current as it was just before turn-Off. When several devices share the same pull-down resistor, the CSNS pins of unused devices must be tri-stated. This is accomplished by setting CSNS0_en = 0 and CSNS1_en = 0 in the GCR register. Settling time (tCSNSVAL_XX) is defined as the time between the instant at the middle of the output voltage’s rising edge (HS[0:1] = 50% of VPWR), and the instant at which the voltage on the CSNS-pin has settled to ±5.0% of its final value. Anytime an overcurrent window is active, the CSNS pin is disabled (see Overcurrent Detection on Resistive and Inductive Loads). The current and temperature sensing functions are unavailable in Fail-safe mode and in Normal mode when operating without the VDD supply voltage. In order to generate a voltage output, a pull- down resistor is required (R(CSNS)=1.0 k typ. and 470 < R(CSNS) < 10 k). When the current sense resistor connected to the CSNS pin is disconnected, the CSNS voltage is clamped to VCL(CSNS). The CSNS pin can source currents up to about 5.6 mA. CURRENT SENSE SYNCHRONIZATION (SYNC) To synchronize current sensing with an external process, the SYNC signal can be connected to a digital input of an external MCU. SYNC is asserted logic low when the current sense signal is accurate and ready to be read. The current sense signal on the CSNS pin has the specified accuracy t SYNREAD_XX seconds after the falling edge on the SYNC pin (Figure 9) and remains valid until a rising edge is generated. The rising edge that is generated by the SYNC pin at the turn- OFF instant (internal or external) may also be used to implement synchronization with the external MCU. Parameter t SYNCVAL_XX is defined as the time between the instant at the middle of the output-voltage rising edge (HS[0:1] = 50% of VPWR), and the instant at which the voltage on the SYNC-pin drops below 0.4 V (VSOL). The SYNC pins of different devices can be connected together to save micro- controller input channels. However, in this configuration, the CSNS function of only one device should be active at a time. Otherwise, the MCU does not determine the origin of the SYNC signal. The SYNC pin is open drain and requires an external pull-up resistor to V DD. DIRECT CONTROL INPUTS (IN0 AND IN1) The IN[0:1] pins allow direct control of both channels. A logic [0] level turns off the channel and a logic[1] level turns it on (Channel Control in Normal Mode). When the device is in Sleep mode, a transition from logic 0 to logic 1 on any of these pins wake it up (Sleep Mode). If it is desired to automatically turn on the channels after a transition to Fail- safe mode, inputs IN[0] and IN[1] must be externally connected to the VPWR pin by a pull-up resistor (e.g. 10 k typ. However, this prevents the device from going into Sleep

24 Freescale Semiconductor

regulator of 3.3 V by an internal pull-up current source IUP. given in the table Overcurrent Profile Selection. (CLOCK_fail), overvoltage (OV), and undervoltage (UV). accessed through the SPI port. internally pulled-down to GND by resistor RDWN. state only when SCLK is at logic [0] (Figure 7 and Figure 8). CSB is internally pulled up to VDD through IUP. ignored and the SO output is tri-stated (high-impedance). Table 10. Register addresses and internally connected to a pull-down current source, IDWN. µF in parallel with this 100 nF capacitor.

Analog Integrated Circuit Device Data Freescale Semiconductor 25 06XSD200 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION before the SO registers can be read. The SO register assignment is described in Table 12. POWER SWITCH OUTPUT PINS (HS0 AND HS1) HS0 and HS1 are the output pins of the power switches, to be connected to the loads. A ceramic capacitor (<= 22 nF (+/ - 20%) is recommended between these pins and GND for optimal EMC performances. FAIL-SAFE OUTPUT (FSOB) This pin (active low) is used to indicate loss of SPI communication or loss of SPI supply voltage, VDD. This open- drain output requires an external pull-up resistor to VPWR. FUNCTIONAL INTERNAL BLOCK DESCRIPTION POWER SUPPLY The device operates with supply voltages from 6.0 to 58 V (VPWR), but is full spec. compliant between 8.0 and 36 V. The VPWR pin supplies power to the internal regulator, analog, and logic circuit blocks. The VDD pin (5.0 V typ.) supplies the output register of the Serial Peripheral Interface (SPI). Consequently, the SPI registers cannot be read without presence of VDD. The employed IC architecture guarantees a low quiescent current in Sleep mode. SWITCH OUTPUT PINS HS0 & HS1 HS0 and HS1 are the output pins of the power switches. Both channels are protected against various kinds of short- circuits and have active clamp circuitry that may be activated when switching off inductive loads. Many protective and diagnostic functions are available. For large inductive loads, it is recommended to use a freewheeling diode. The device can be configured to control the output switches in parallel, which guarantees good switching synchronization. COMMUNICATION INTERFACE AND DEVICE CONTROL In Normal mode the output channels can either be controlled by the direct inputs or by the internal PWM module, which is configured by the SPI register settings. For bidirectional SPI communication, VDD has to be in the authorized range. Failure diagnostics and configuration are also performed through the SPI port. The reported failure types are: OpenLoad, short-circuit to supply, severe short- circuit to ground, overcurrent, overtemperature, clock-fail, undervoltage, and overvoltage. The SPI port can be supplied either by a 5.0 V or by a 3.3 V voltage supply. For direct input control, VDD is not required. A Pulse Width Modulation (PWM) circuit allows driving loads at frequencies up to 1.0 kHz from an external or an internal clock. SPI communication is required to set these options. POWER SUPPLY MCU INTERFACE and OUTPUT CONTROL SPI INTERFACE PARALLEL CONTROL INPUTS PWM CONTROLLER SELF- PROTECTED HIGH SIDE SWITCHES HS0-HS1 MCU INTERFACE internal regulator

Analog Integrated Circuit Device Data

26 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES The device possesses two high side switches (channels) each of which can be controlled independently. The device has four fundamental operating modes: Sleep, Normal, Fail- safe, and Fault mode, as shown in Table 5. Each channel can be controlled in three different ways in Normal mode: by a signal on the Direct Input pin, by an internal clock signal (autonomous operation) or by an external clock signal. For bidirectional SPI communication, a second supply voltage is required (V DD = 5.0 V or 3.3 V). When only the direct inputs IN[x] are used, VDD isn’t required. DEVICE START-UP SEQUENCE To put the device in a known configuration and guarantee predictable behavior, the device must undergo a wake-up sequence. However, it should not be woken up earlier than the moment at which V PWR has exceeded its undervoltage threshold, VPWR(UV), and VDD has exceeded its supply failure threshold, VDD(FAIL). In applications using the SPI port, the device is typically put in wake mode by setting RSTB=1. Wake-up of applications with direct input control can be achieved by having signals IN_ON[0] = 1 or IN_ON[1 ]= 1 (see Figure 10). After wake-up, all SPI register contents are reset (as defined in Table 11 and Table 12) and Normal mode is entered. All the device functions are available 50 µs later (typically). If the start-up sequence is not performed at device start- up, its configuration may be undetermined and correct operation is not guaranteed. In situations where the above described start-up sequence can not be performed, it is recommended to generate a wake-up event after the moment V PWR has reached the undervoltage threshold. CHANNEL CONFIGURATION THROUGH THE SPI Setting the Channel Configuration The channel configuration is determined by the contents of the pulse-width (PWMR_s), the configuration (CONFR_s) and the overcurrent (OCR_s) registers. They allow setting, among others, the following parameters: duty-cycle, delay, Slew Rate, PWM enable (PWM_en), clock selection (CLOCK_sel), prescaler (PR), and direct_input disable (DIR_dis). Extension “_s” means that these registers exist for each of both channels. Function assignment is described in detail in the section SI Register Addressing. Reading Back the Channel’s Status and Settings The channel’s global switching and operating states (On/ Off, normal/fault) are all contained in the SO-STATR register (see Table 12). The precise fault type can be found by reading out the FAULTR_s and STATR registers. The current channel settings (channel configuration) can be known by reading the PWMR, CONF, OCR, RETRYR, GCR, and DIAG registers (see section Serial Output Register Assignment and further). NORMAL MODE Normal mode (bit NM = 1) can be entered in two ways: either by driving the device through the direct inputs (IN[x]) or by establishing SPI communication (requires RSTB =high). Bidirectional SPI communication additionally requires the presence of VDD. To maintain the device in Normal mode, communication must take place regularly (see Entering and Maintaining Normal Mode). The device is in Normal mode (NM) when:

• V PWR (and VDD) are within the normal range and
• wake-up = 1, and
• fail-safe = 0, and
• fault = 0. Channel Control in Normal Mode In direct input mode, the channel’s switching state (On/Off) is controlled by the logic state of the direct input signal with the default values (00) of turn-on delay and slew rate, specified in Table 4. In internal clock mode, the switching state is controlled by an internal clock signal (Internal Clock & Internal PWM (Clock_int_s bit = 1)). Frequency, slew rate, duty-cycle, and turn-on delay are programmable independently for both channels. In external clock mode, the frequency of the external clock controls the output's PWM frequency, but slew rate, duty cycle, and turn-on delay are still programmable. Factors Determining the Channel’s Switching State The switching state of a channel is defined by the instantaneous value of the output voltage. It is defined as “On” when the output voltage V(HS[x]) > VPWR /2 and “Off” when V(HS[x]) < VPWR /2. The channel’s switching state should not be confused with the device’s internal channel control state hson[x] (= High Side On). Signal hson[x] defines the targeted switching state of the channel (On/Off). It is either controlled by the value of the direct input signal or by that of the internal/external clock signals combined with the SPI register settings. The value of hson[x] is given by the following boolean expression: hson[x] = [(IN[x] and DIR_dis[x]) or (On bit [x] and Duty_cycle[x] and PWM_en[x] = 1) or (On bit [x] and PWM_en[x] = 0)]. In this expression Duty_cycle[x] represents the value of the duty cycle, set by bits D7…D0 of the PWMR register (Table 6). The channel’s actual switching state may differ from the control signal’s state in the following cases:
• short circuits to GND, before automatic turn-Off (t < tFAULT)

• short circuits to V PWR when the channel is set to Off
• V PWR < 13 V when OpenLoad-in-Off-state detection is selected and the load is actually lost
• during the turn-on transition as long as V(HS[x])< Vpwr/2
• during the turn-off transition as long as V(HS[x]) > Vpwr/2 Entering and Maintaining Normal Mode A 0-to-1 transition on RSTB, (when both VPWR and VDD are present) or on any of both direct inputs IN[x] (when only supplied by VPWR) puts the device in Normal mode. If desired, the device can be operated in Normal mode without VDD, but this requires that at least one of both direct inputs be regularly turned on (Operation and Operating Modes). To maintain the device in Normal mode (NM), communication must take place on a regular basis. For SPI communication, the state of the WDIN bit must be alternated at least every 310 ms (typ.) (tWDTO), unless the WD_disable bit is set to 1. For direct input control, the timing requirements are shown in Figure 10. A signal called IN_ON[x] is not directly accessible to the user but is used by the internal logic circuitry to determine the device state. When no activity is detected on a direct input pin (IN[x]) for a time longer than t IN = 250 ms (typ.), timeout is detected and IN_ON[x] goes low. When this occurs on both channels, Sleep mode is entered (Sleep Mode), provided reset = RSTB = 0 It enters Fail-safe mode in case of a timeout on SPI communication or when VDD is lost after having been initially present (if this function was previously enabled by setting: V DD_FAIL_EN bit = [1]). Setting watchdog disabled (WD_dis = 1, D4 of the GCR register) avoids entering Fail- safe mode after watchdog timeout. Device behavior upon fault occurrence is explained in the paragraph on Faults Fault Mode).

Figure 10. Relation Between Signals IN(x) and IN_ON[x] channels are merely controlled by the direct input pins IN[x]. Hz, reset should be set to RSTB = 1.

• wake-up = RSTB or IN_ON[0] or IN_ON[1]
• fail-safe = (VDD Failure and VDD_FAIL_en) or (SPI watchdog timeout (tWDTO) and WD_dis = 0)
• fault = OC[0:1] or OT[0:1] or SC[0:1] or UV or (OV and OV_dis) IN_ON[x] IN[x] tIN

Table 5. Device Operating Modes Sleep 0 x x All channels are OFF. Fault 1 X 1 The channels are OFF, see page 29.

28 Freescale Semiconductor

Figure 11. Device Operating Modes turned off to minimize current consumption.

• V PWR (and VDD) are within the normal range, and
• wake-up = 0 (wake-up = RSTB or IN_ON[0] or IN_ON[1])
• and
• fail-safe = X and
• f a u l t = X When employed, VDD must be kept in the normal range. Sleep mode is the default mode after the first application of the supply voltage (V PWR), prior to any I/O communication (RSTB and the internal states IN_ON[0:1] are still at logic [0]). All SPI register contents remain in their default state during sleep mode. FAIL-SAFE MODE Entering Fail-safe Mode Fail-safe mode is entered either upon loss of SPI communication or after loss of optional SPI supply voltage VDD (VDD Out of Range). The FSOB pin goes low and the channels are only controlled by the direct inputs (IN[0:1]). All protective functions remain fully operational. Previously latched faults are delatched and SPI register contents is reset (except bits POR & PARALLEL). The SPI registers can not be accessed. These conditions are also described by the following expressions:
• V PWR is within the normal voltage range, and
• wake-up = 1, fault = 0, and
• fail-safe = 1 ((VDD Failure and VDD_FAIL_en=1 before) or (t(SPI)> tWDTO and WD_dis = 0). The last condition describes the loss of SPI communication which is detailed in the next section. Watchdog on SPI Communication and Fail-safe Mode When VDD is present, the SPI watchdog timer is started upon a rising edge on the RSTB pin. Thereafter the device monitors the state of the first bit (WDIN) of all received SPI words. When the state of this bit is not alternated at least once within a data stream of duration t WDTO = 310 ms typ., the device considers that SPI communication has been lost and enters Fail-safe mode. This behavior can be disabled by setting the bit WD_DIS = 1. The value of watchdog timeout is derived from an internal oscillator. Returning from Fail-safe to Normal mode To exit Fail-safe mode and return to normal mode again, first a SPI data word with its WDIN bit = 1 (D15) must be received by the device (regardless the register it is contained Sleep (fail-safe = 0) and (wake-up = 1) and (fault = 0) (wake-up = 0) Fail-safe Normal (wake-up = 0) (fail-safe = 1) and (wake-up = 1) and (fault = 0) (fail-safe = 0) and (wake-up = 1) and (fault = 0) (wake-up = 1) and (fail-safe = 1) and (fault = 0) Fault (wake-up = 0) (wake-up = 1) and (fault = 1) (fail-safe = 0) and (wake-up = 1) and (fault = 1) (fail-safe = 1) and (wake-up = 1) and (fault = 1) (fail-safe = 0) and (wake- up = 1) and (fault = 0) (fail safe = 1) and (wake-up = 1) and (fault = 0)

Analog Integrated Circuit Device Data Freescale Semiconductor 29 06XSD200 FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES in and regardless the values of the other bits in this register). Next, a second data word must be received within the timeout period (t WDTO = 310 ms typ.) to be able to change any SPI register contents. Upon entering Normal mode, the FSOB pin returns to logic high and previously set faults and SPI registers are reset, except bits POR, PARALLEL and fault bits of latchable faults that had actually been latched. FAULT MODE The device enters Fault mode when any of the following faults occurs in Normal or Fail-safe mode:

• Overtemperature fault, (latchable fault)
• Overcurrent fault, (latchable fault)
• Severe short-circuit fault, (latchable fault)
• Output shorted to V PWR in OFF state (default: disabled)
• OpenLoad fault in OFF st ate (default: disabled)
• OpenLoad fault in ON st ate (default: disabled)
• External Clock Failure (default: enabled)
• Overvoltage fault (enabled by default)
• Undervoltage fault, (latchable fault) The Fault Status pin (FSB) asserts a fault occurrence on any channel in real time (active low). Additionally, the assigned fault bit in the STATR_s or FAULTR_s register is set to one. Conversely to the FSB pin, a fault bit remains set until the corresponding register is read, even if the fault has disappeared. These bits can be read via the SO pin. Fault occurrence also results in a turn-off of the incurred channel, except for the following faults: OpenLoad (On and Off state), External Clock Failure and Output(s) shorted to V PWR. Under and Overvoltage occurrence causes simultaneous turn-off of both channels. Details on the device’s behavior after the occurrence of one of the above faults can be found in Protection and Diagnostic Features. Fault mode (Operation and Operating Modes) is entered when:
• V PWR (+VDD) were within the normal voltage range, and
• wake-up = 1, and
• fail-safe = X, and
• f a u l t = 1 (see Going from Normal to Fail-safe, Fault or Sleep Mode) Resetting FAULT bits Registers STATR_s and FAULTR_s contain global and channel-specific fault information. Reading the register where the fault bit is contained clears it, provided failure cause disappearance was detected and the fault wasn’t latched. Entering Fault Mode from Fail-safe Mode When a Fault occurs in Fail-safe mode, the device is in Fault/Fail-safe mode and behaves according to the description of fault mode. However, SPI registers remain reset and can not be accessed. Only the Direct Inputs control the channels. Returning from Fault Mode to Fail-safe Mode When disappearance of the fault previously produced in Fail-safe mode has been detected, the device returns to Fail- safe mode and behaves accordingly. FSB goes high, but the auto-retry counter is not reset. Latched faults are not delatched. SPI registers remain reset. LATCHABLE FAULTS An auto-retry function (see Auto-retry) controls how the device responds to the so-called latchable faults. Latchable faults are: overcurrent (OC), severe short-circuit (SC), overtemperature (OT), and undervoltage (UV). If a latchable fault occurs, the channel is turned off, the FSB terminal goes low, and the assigned fault bit is set. These bits can not be reset before the next turn-on event is generated by auto-retry. Next, the channel automatically turns on at a programmable interval (provided auto-retry was enabled and the channel wasn’t latched). If the failure disappears prior to the expiration of the available amount of auto-retries, the FSB pin automatically returns to logic [1], but the fault bit remains set. It can then still be reset by reading the SPI register it is contained in. However, the fault actually gets latched if the failure cause hasn’t disappeared at the first turn-on event following expiration of the available amount of auto-retries (see Auto- retry). In that case, the channel gets latched and the FSB terminal remains low. The fault bit can not be reset by reading out the associated SPI register prior to performing a delatch sequence ( Fault Delatching). Fault Delatching To delatch a latched channel and be able to turn it on again, a delatch sequence must be executed after disappearance of the failure cause. Delatching also resets the fault bit of latched faults (see Resetting FAULT bits). To reset the FSB pin, both channels must be delatched. Delatching is achieved either by alternating the state of the channels’ fault control signal fc[x] (generating a 1_0_1 sequence), or by resetting the auto-retry counter (provided retry is enabled). See Reset of the Auto-retry Counter. Delatching then actually occurs at the rising edge of the turn- on event. Signal fc[x] is an internal signal used by the device’s internal logic circuitry to control the diagnostic functions. The value of fc[x] depends on the state of the variables IN_ON[x], DIR_dis[x] and ON[x] and is expressed as follows: fc[x] = ((IN_ON[x] and DIR_dis[x] = 0) or ON[x] = 1) Alternating the fc[x] signal is achieved differently according to the way the user controls the device.
• In direct-input controlled mode (DIR_dis_s = 0), the IN[x] pin must be set low, remain low for at least tIN seconds, and set high again (be switched On). This might happen automatically when operating at frequencies f<4.0 Hz.
• In SPI-controlled mode, the ON_bit state (D8 of the PWMR_s reg.) must be alternated (‘toggled’). No minimum OFF state duration is required in this case.

30 Freescale Semiconductor

also delatched and faults are reset. device is then in a combined Fail-safe/Fault mode. 256 or 512 in external clock mode. Figure 12. Internal and External Clock Operation PWM_en_0=1 synchronizes the channels. Table 6. PWM Duty Cycle Value Assignment

0 X OFF

Table 7. Switch-on Delay in PWM Mode

Analog Integrated Circuit Device Data Freescale Semiconductor 31 06XSD200 FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES of the internal clock period accordingly. The actual value of the channel’s switching period is obtained by multiplying the internal clock period by 256. When the duration of the negative CSB pulse is outside a predefined time slot (from t CSB(MIN) to t CSB(MAX)), the calibration event is ignored and the internal clock frequency remains unchanged. If the value (fPWM(0)) has not been previously calibrated, it remains at its default level. Synchronization of both Channels When internal clock signals are used to drive the PWM modules, perfect synchronization over a long time can not be achieved since both clock signals are independent. However, when the channels are driven by an external clock, perfect synchronization can be achieved by simultaneously setting PWM_en_1=1 and PWM_en_0=1. The best way to optimize EMC is to use an external clock with a staggered switch on delay (see Table 7). PARALLEL OPERATION The channels can be paralleled to drive higher currents. Setting the PARALLEL bit in the GCR register to logic [1] is mandatory in this case. The improved synchronization of both transistors allows an equal current distribution between both channels. In parallel mode, both output pins (HS[x]) must be connected (as well as both IN[x] pins in case of external control). CONF0 and CONF1 must be set to equal values. 1- Device Configuration in Parallel mode: There are two ways to configure the On/Off control: SPI- configured PWM control and Direct Input Control.

• SPI configured Parallel mode: The switching configuration is solely defined by the (SI) PWMR_0, CONFR_0, OCR_0, and RETRY_0 registers. As soon as PARALLEL=1, the contents of the corresponding registers in bank 1 are replaced by that of bank 0, except bits D6-D8 of the CONFR_1 register (configuration of the Open load/Output short-circuited diagnostics). After setting PARALLEL=1, contents of SO registers in bank 0 are copied to registers of bank 1 only when new information is written in them. Bits OD3, OD4, and OD5 of both FAULTR_s registers (OLON, OLOFF, OS) are always reported independently.
• Direct Input controlled Parallel mode: The IN0 and IN1 pins must be connected externally. 2- Diagnostics in Parallel Mode: The Diagnostics in Parallel mode operate as follows:
• OpenLoad in OFF state and - OpenLoad in ON state: The OL_ON and OL_OFF bits of both FAULTR registers independently reports failures of the channels according to the settings of bits D7 and D6 of the CONFR_s register.
• Current sensing: Refer to the Table 22 for a description of the various current sensing modes. Only the Current sense ratio of bank 0 (D5 of the OCR_0 register) is considered. The corresponding bit in the OCR_1 register is copied from that of the OCR_0 register.
• output shorted to supply: The OS-bit (OD3) of each of both FAULT registers independently report this fault, according to the settings of bit D8 of the CONFR_s reg. 3- Protections in Parallel Mode:
• Overcurrent: -Only the Configuration of overcurrent thresholds & blanking windows of channel 0 are considered. -In case overcurrent (OC) occurs on any channel, both channels are turned-off. Regardless the order of occurrence of overcurrent (OC), both OC-bits (OD0) in the FAULT registers are simultaneously set to logic 1.
• severe short-circuit: In case of SC detection on any channel, both channels are turned-off and the SC bits (OD1) in both FAULT registers are simultaneously set to logic 1.
• overtemperature: In case of OT detection on any channel, both channels are turned-off and both OT bits in the FAULT registers (OD2) are simultaneously set to logic 1.
• auto-retry: Only one 4-bit auto-retry counter specifies the number of successive turn-on events on paralleled channels (RETRYR_0). The counter value in register RETRYR_1 (OD4…OD7) is copied from that in RETRYR_0. To delatch the channels, only channel 0 needs to be delatched. CSB SI CALR_s SI command ignored Internal clock period of channel s tCSB tCSB

32 Freescale Semiconductor

The channels have individual overtemperature detection. both channels has dropped below the threshold: TJ<TSD.

• If the channel is ON, the associated output is switched OFF, the OT bit is set, and FSB = 0.
• If the channel is OFF: FSB goes to logic [0] and remain low until the temperature of both channels is below TSD and any of the channels is turned on again. The auto-retry function (if activated) automatically turns on the channel when the junction temperature has dropped below TSD. The OT fault bit can only be reset by reading out the FAULTR register, provided that TJ<TSD and FSB = 1 again. Overcurrent Fault (latchable fault) When an overcurrent (OC) is detected, the channel is immediately turned Off (after t FAULT seconds). The OC-bit is set to 1 and FSB becomes low [0]. Overcurrent is detected anytime the load current crosses an overcurrent threshold or exceeds the window width of the selected overcurrent protection profile. This profile is a stair function with windows the height and width of which are preselected through the SPI port. The maximum allowable value of the load current at a particular moment in time is defined by levels I_OCH and I_OCM and windows tOCM_x and tOCH (programmable by SPI bits). The steady-state overcurrent protection level I_OCL is defined by the settings of the OCL and HOCR bits. Anytime an overcurrent window is active, current sensing is blanked and SYNC becomes 1. Overcurrent Duration Counter The load current can spend only a defined amount of time in a particular window of the overcurrent profile. If the time in the window exceeds the selected window width (tOCX) or the overcurrent threshold is crossed, the channel is turned off (OC fault), followed by auto-retry (if enabled). An internal overcurrent duration counter is employed for this function. Overcurrent Detection on Resistive and Inductive Loads According to the load type (resistive or inductive), one of two different overcurrent profiles should be selected. This is done by connecting a resistor with the appropriate value between the CONF[0:1] pins and GND (Table 8). When overcurrent windows are active, current sensing is disabled and the SYNCB pin remains high. This is illustrated by

Figure 13. After turn on, the output voltage (second Figure 13. Current Sense Blanking during Overcurrent second window is either tOCM1_L or tOCM2_L (see Table 17). Table 8. Overcurrent Profile Selection

34 Freescale Semiconductor

setting OV_dis = 1 in the GCR register).

• V DD < VDD(FAIL) with VPWR in the normal voltage range
• V DD and VPWR are below the VSUPPLY(POR) voltage threshold
• The corresponding SPI regi ster is read after the disappearance of the failure cause (and delatching) Drain/source Overvoltage protection The device tries to limit the Drain-to-Source voltage by turning on the channel whenever VDS exceeds VDS(CLAMP). When a fault occurs (SC, OC, OT, UV), the device is rapidly switched Off (in t < tFAULT seconds), regardless the value of the selected slew rate. This may induce voltage surges on VPWR and/or the output pin (HS[x]) when connected to an inductive line/load. Turning on the device also dissipates the energy stored in the inductive supply line. This function monitors overvoltage for V PWR > 30 V. For supply voltages VPWR < 30 V, the device is protected from negative output voltages by automatically turning on the channel. The feature remains functional after device ground loss. Supply Overvoltage Protection In order to protect the device from excessive voltages on the supply lines, the voltage between the device’s supply pins (VPWR and the GND) is monitored. When the VPWR-to-GND voltage exceeds the threshold VD_GND(CLAMP), the channel is automatically turned on. The feature is not operational in cases of ground loss. Negative Output Voltage Protection The device tries to limit the undervoltage on the output pins HS[x] when turning off inductive loads. When the output voltage drops below V CL, the channel is switched on automatically. This feature is not guaranteed after a device ground loss. The energy dissipation capabilities of the circuit are defined by the ECL [0:1] parameters. For inductive loads larger than 20 µH, it is recommended to employ a freewheeling diode. The three different overvoltage protection circuits are symbolically represented in Figure 15. The values of the clamping diodes are those specified in Table 3. Coupling factor k represents the current ratio between the current in the supply voltage measurement diode (zener) and the current injected into the MOSFET’s gate to turn it on.

Figure 15. Supply and Output Voltage Protections a system GND loss, the channels are turned off. and be turned on when the IN[x] input(s) are tied to VPWR.

• all unused pins are tied to the overall system’s GND connection by resistors > 8.0 k. IMEG GND Loa d HS[ x] DC VDS(CLAMP)-Vth VD_GND(Clam p) VCL-Vth K.Iz Vth

Analog Integrated Circuit Device Data Freescale Semiconductor 35 06XSD200 FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES

• any device pin connected to external system components has a series resistors > 8.0 k (except pins VPWR, VDD, HS[0], HS[1] and R(CSNS)>2.0 k)
• pins FSB, FSOB and SYNC are in the logic high state when they are shared with other devices. This means that none of the other devices is in Fault or Fail-safe mode, nor should current sensing be performed on any one of them when GND is lost When no series resistors are employed, the channel state after GND loss is determined by the voltage on pins IN[0:1] and the voltage shift of the device GND. Device GND shift is determined by the lowest value of the external voltage applied to either pin of the following list: CLOCK, FSB, IN[0:1], FSOB, SCLK, CS,SI, SO, RSTB, CONF[0:1], SYNC, CSNS. When the device GND voltage becomes logic low (V(GND)< V IL), the SPI port continues to operate and the device operates normally. When the GND voltage becomes logic high (V(GND)> VIH), SPI communication is lost and Fail- safe mode is entered. When the voltage applied to the IN[0:1] input is VPWR, the channel is turned on when it is VDD, the channel is turned off if (VDD - V(GND)) < VIH. SUPPLY VOLTAGES OUT OF RANGE VDD Out of Range If the external VDD supply voltage is lost (or falls outside the authorized range: VDD<VDD(FAIL)), the device enters Fail- safe mode, provided the VDD_FAIL_en bit had been set. Consequently, the contents of all SPI registers are reset. The channels are then controlled by the direct inputs IN[0 :1] (if VPWR is within the normal range). Since the VPWR pin supplies the circuitry of the SPI, current sense and most of the protective functions (overtemperature, overcurrent, severe short-circuit, short to VPWR, and OpenLoad detection circuitry), these faults are still detected and reported at the FSB pin. However, without VDD, the SO pin is no longer functional. The SPI registers can no longer be read and detailed fault information is unavailable. Current sensing also becomes unavailable. If VDD_FAIL_EN wasn’t set before VDD was lost, the device remains SPI-controlled, even though the SPI registers can’t be read. No current flows from the VPWR to the VDD pin. VPWR Supply Voltage Out of Range In case VPWR is below the undervoltage threshold VPWR(UV), it is still possible to address the device by the SPI port, provided VDD is within the normal range. It does not prevent other devices from operating when a device is part of a daisy-chain. To accomplish this, RSTB must be kept at logic [1]. When the device operates at supply voltages above the maximum supply voltage (VPWR=36 V), SPI communication is not affected (see Overvoltage Detection (enabled by default)). The internal pull-up and pull-down current sources on the SPI pins are not operational. Executing a Power-on-Reset (POR) sequence is recommended when V PWR re-enters its authorized range. No current flows from the VDD to the VPWR pin. Loss of VPWR, Loss of VDD and Power-on-Reset (POR) In typical applications (Figure 21 and Figure 22), an external voltage regulator may be used to derive VDD from VPWR. In wake mode, a Power-on-Reset (POR) sequence executes and the POR bit (OD6 of the STATR register) is set if: 1. V PWR > VPWR (POR), after a period VPWR < VPWR (POR) (and VDD < VDD (POR) before and after) 2. V DD > VDD (POR) after a period with VDD < VDD (POR) (VPWR < VPWR (POR) before and after) POR is also set at the transition to wake-up (by setting RSTB=1 or IN[x]=1) when VPWR > VPWR (POR) (before and after)  or VDD >VDD(POR) (before and after). POR is not performed when VPWR > VPWR (POR) after a period VPWR < VPWR (POR) (and VDD > VDD (POR) permanently).

36 Freescale Semiconductor

Figure 16. State Machine: Fault Occurrence and Auto-retry Retry[x] = OC[x] or SC[x] or OT[x] or UV. RETRY_s register) has to be set to the appropriate value. (Retry[x]=1, see Auto-retry). automatically switches on again after the auto-retry period. (bits D2 and D3 of the RETRY_s register, see Table 21). Table 9. Auto-Retry Activation for Lamps (CONF=0) and

Analog Integrated Circuit Device Data Freescale Semiconductor 37 06XSD200 FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES Amount Of Auto-retries In case the device is configured for an unlimited amount of auto-retries (Retry_unlimited_s = 1), auto-retry continues as long as the device remains powered. The channel never be latches off. In case a limited amount of retries is selected (Retry- unlimited_s = 0), auto-retry continues as long as the value of the 4-bit auto-retry counter does not exceed 15 (bits OD4...OD7 of the RETRY_s register). After 15 retries, the Rfull bit of the STATR (OD4 for channel 0, OD5 for channel 1) register is set to logic high. The amount of available auto- retries is then reduced to one. If the fault still hasn’t disappeared at the next retry, the corresponding channel switches off definitively and the fault is latched (FSB = 0, see Protection and Diagnostic Features and Fault Delatching). Any channel can be turned on at any moment during the auto-retry cycle by performing a delatch sequence. However, this does not reset the retry counter. The value of the auto-retry counter can be read back in Normal mode only (SO-RETRYR register bits OD7-OD4). Reset of the Auto-retry Counter Any one of the below events reset the retry counter:

• Fail-safe is entered ( Fail-safe Mode)
• Sleep mode is left ( Sleep Mode)
• POR occurs ( Supply Voltages Out of Range)
• the retry function is set to unlimited (bit Retry- unlimited_s = 1 (D1 = 1))
• the retry function is disabled (retry_s bit= D0 of the RETRY_s register under goes a 1-0 transition for CONF = 1 and a 0-1 transition for CONF = 0). If the channel is latched at the moment the auto-retry counter was reset (case 4), the channel is delatched, and be turned on after one retry period (if retry was enabled). Auto-retry and Overcurrent Duration During the on-period following an auto-retry, the load current profile is compared to the length and height of the selected overcurrent threshold profile, as described in the section on overcurrent protection (See Overcurrent Fault (latchable fault)). When the lighting profile is activated, the overcurrent duration counter is reset at each auto-retry (to allow sustaining new inrush currents). For DC motor mode however, it is only reset at the turn-off event of the first PWM period without any overcurrent (see Reset of the Duration Counter). Figure 16 gives a description of the retry state machine with the various transitions between operating modes. DIAGNOSTIC FEATURES Diagnostic functions OpenLoad-in-On state (OLON), OpenLoad-in-Off-state (OLOFF) and output short-circuited to VPWR (OS) are operational over the frequency and duty cycle ranges specified in Table 4. Occurrence of an OLON, OLOFF, or OS fault sets the associated bit in the FAULTR_s register but does not trigger automatic turn-off. Any of these diagnostic functions can be disabled by setting OLON_dis_s=1, OLOFF_dis_s=1, or The functions are guaranteed over the specified ranges for output capacitor values up to 22 nF (+/-20%). Output shorted-to-VPWR Fault The device detects short-circuits between the output and VPWR. The detection is performed during the Off-state. The output-shorted-to-VPWR fault-bit (OS_s) is set whenever the output voltage rises above VOSD(THRES). The fault is reported in real time on the FSB pin and saved by the OS_s bit. Occurrence of this fault does not trigger automatic turn-off. Even if the short-circuit disappears, the OS_s bit does not clear until the FAULTR register is read. The function may be disabled by setting OS_dis_s=1. The function operates over the duty cycle ranges specified in Diagnostic Features. This type of event shall be limited to 1000 min during its lifetime. In case of permanent output shorted to the power supply condition, it is needed to turn-on the corresponding channel. OpenLoad Detection In Off State OpenLoad-in-OFF-state detection (OL_OFF) is performed continuously during each OFF-state (both for CSR0 and CSR1). This function is implemented by injecting a small current into the load (I OLD(OFF)). When the load is disconnected, the output voltage rises above VOLD(THRES). OL_OFF is then detected and the OL_OFF bit in the FAULTR register is set. If disappearance of the open load fault is detected, the FSB output pin returns to a high immediately, but the OL_OFF bit in the fault register remains set until it is cleared by a read out of the FAULTR register. The function may be disabled by setting OLOFF_dis_s=1. The function operates over the duty cycle ranges specified in section Diagnostic Features. OpenLoad Detection In On State (OL_ON) OpenLoad-in-ON state detection (OLON) is performed continuously during the On-state for CSR0 over the ranges specified in section Diagnostic Features. An OpenLoad in On state fault is detected when the load current is lower than the OpenLoad current threshold IOLD(ON). This happens at IOLD(ON) = 500 mA (typ.) for high current sense mode (CSR0), and at 7.0 mA (typ.) for low current mode. FSB is asserted low and the OLON bit in the fault register is set to 1 but the channel remains On. FSB goes high as soon as disappearance of the failure cause is detected, but the OL_ON bit remains set. In high current mode (CSR0), OpenLoad in On state detection is done continuously during the On-state and the OLON-bit remains set even if the fault disappears. In high current mode, the OLON-bit is cleared when the FAULTR register is read during the Off state, even if the fault

38 Freescale Semiconductor

failure cause (load disconnected) has disappeared. internal or external clock (case 1), the period is 150 ms (typ.).

1. In internal PWM (int./ext. clock), low current mode

frequency of about 7.0 Hz (each tOLLED =150 ms typ.). The function is available for a duty cycle of 100%. OL_ON detection event (before OS and OL_OFF).

1. In direct input, low current mode (CSR1), OL_ON is

instant) but the duty cycle is restricted to the values. pin can be used to identify the turn-off instant. and the SYNCB pin remains high. Monitoring (CSNS)) and is therefore synchronous with it. Figure 18. The amount of current the CSNS currents up to the lower overcurrent threshold (OCLx A). current cannot be monitored.

again to allow current monitoring of the other channel. Figure 17. Current Sensing Ratio Versus Output Current “random” component (I_LOAD_ERR_SYS, I_LOAD_ERR_RAND). compensation technique greatly minimizes this error. illustrated in the next sections. CSRx have the nominal values, specified in ESR0_ERR.

40 Freescale Semiconductor

random offset errors have been compensated. current with an opposite value of the OFP bit. close enough to be sure that the offset value wasn’t changed. sufficient resolution to avoid introducing additional errors. before and after offset compensation, is shown in Figure 18. Figure 18. Current Sense Accuracy versus Output Figure 19. Track and Hold Current Sense Accuracy read after the moment that temperature T °C < TOTWAR. real time by bits OUT[x] in the STATR register (bit OD0/OD1). Determining the Channel’s Switching State). dependent and applies to a typical application (Figure 21).

ratings on VDD and SPI pins (Table 2) aren’t exceeded. Figure 20. 16-Bit SPI Interface Timing Diagram transmitted data) by keeping the CSB pin at logic 0. registers containing the fault/device status and settings. implemented independently for each of both channels. data integrity verification. updated with the latest fault status information. kept low until the SPI message has arrived at its destination. device, it can be executed by setting CSB=1.

1. RST must be in a logic [1] state during data transfer.
2. Data enter the SI pin starting with D15 (MSB) and ending with bit D0.
3. Data are available on the SO pin starting with bit 0D15 (MSB) and ending with bit 0(OD0).

Notes 1. RSTB must be in a logic [1] state during data transfer.

1. Data enter the SI pin starting with D15 (MSB) and ending with bit D0.
2. Data are available on the SO pin starting with bit 0D15 (MSB) and ending with bit 0(OD0).

Analog Integrated Circuit Device Data

42 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND SPI REGISTERS Table 10. SI Message Bit Assignment D14 Parity (P) check. P-bit must be set to 0 for an even number of 1-bits and to 1 for an odd number. D13 Selection between SI registers from bank 0 (0= channel 0) and bank 1 (Table ). D12 : D10 Register address bits. D9:D0 Used to configure the device and the protective functions and to address the SO registers. Table 11. Serial Input register Addresses and Function Assignment

10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

contents

reset*

0 X 0 X X X 0 0 0 0** 0 0 0 0 0 0

• = RSTB = 0 or VDD(FAIL) after VDD = 5.0 V or POR ** = except bit D6 (PARALLEL) of the GCR register that is saved when VDD(FAIL) occurs, provided VDD = 5.0 V and VDD_FAIL_EN = 1 before X = register address, P = parity bit

RETRY_s, GCR, and DIAGR (Table 12). Table 12. Serial Output Register Bit Assignment Table 13. Value of bit A0 Required for Addressing

44 Freescale Semiconductor

(both in the GCR register) must be set to 1. VPWR pin. The default value [0] enables the feature. default value [0] enables this feature (Table 14). enables the feature, see Table 14. determined by the settings of the internal PWM functions. Table 7. Refer to the section Programmable PWM module. of overcurrent, current sensing, and PWM related functions. thresholds (I_OCH and I_OCL). used to create the PWM frequency from the external clock.

1. When PR_s = 0, the divider is 256.

PWM module to use an external clock signal. the “high-current” sensing ratio CSR0 (Table 16). depends on the load type configuration as shown in Table 17. (CONF[x]=0: bulb, CONF[x]=1: DC motor). which is compatible with typical bulb inrush current profiles. Table 14. Selection of OpenLoad Detection Features Table 15. Slew Rate Selection Table 16. Current Sense Ratio Selection

0 CRS0 (default)

1 CRS1

Figure 6. In this case, the maximum overcurrent duration is overcurrent threshold, as shown in Table 20. compensation feature of the current sense function. amount of auto retries to 16 (see Amount Of Auto-retries). accordingly to setting of the CONF pin. auto-retry. The default value [0] disables it. diagnostic functions Table 11. Table 17. Dynamic Overcurrent Threshold Activation Table 18. OCH Upper Current Threshold Selection

0 I_OCH1_s (default)

1 I_OCH2_s

Table 19. OCM Current Threshold Selection

0 I_OCM1_s (default)

1 I_OCM2_s

Table 20. OCL Current Threshold Selection Table 21. Auto-Retry Period

46 Freescale Semiconductor

Operation should be followed. this setting (see Parallel Operation). channel’s load current is kept available after turn-off. function. A logic [0] enables the SPI watchdog. safe mode after VDD < VDD(FAIL). outputs scaled values of a single channel’s load current. next cycle after register addressing.

• Bit OD15 (MSB) reports t he state of the watchdog bit from the previously clocked-in SPI message.
• Bit OD14 (PF, active 1) repo rts an eventual parity error on the previously transferred SI register contents.
• Bits OD13:OD10 echo the state of bits D13, D2, D1, and D0 (SOA3: SOA0) of the previously received SI word.
• Bit OD9: Normal mode (NM) reports the device state. In Normal Mode, NM = 1.
• Bits OD8 : OD0 are the contents of the selected SO register (addressed by bit D13 and bits D2 : D0 of the previous SI STATR register). PREVIOUS ADDRESS SOA3 : SOA0 = 0000 (STATR) When bits SOA3…SOA0 of the previously received SI STATR_s register = 0000, the SO STATR register is addressed. Bits OD8: OD0 contain the relevant channel information: Faults, channel state, and supply voltage errors.
• B i t s O D 8 : OD6 report failures common to both channels
• B i t O D 8 = OV = 1: overvoltage fault
• B i t O D 7 = UV = 1: undervoltage fault
• B i t O D 6 = POR = 1: power-on reset (POR) has occurred Power-ON-Reset occurs when VPWR<VSUPPLY(POR). The OV, UV, and POR bits can be reset by reading the STATR register. Bits OD5: OD4 (Rfull) of the STATR register are set to logic [1] when the auto-retry counter of the corresponding channel is full. These bits are automatically cleared by resetting the corresponding auto-retry counter (see Reset of the Auto-retry Counter)

Table 22. Current Sense Pin Functionality Selection

Analog Integrated Circuit Device Data Freescale Semiconductor 47 06XSD200 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND SPI REGISTERS Bits OD3 (FAULT1) and OD2 (FAULT0) are set to logic [1] when channel-specific (non-generic) faults are detected: FAULTs = OC_s + SC_s + OT_s + OS_s + OLOFF_s + OLON_s. The FAULTs bit can be reset by reading out the common STATR register or the individual FAULTR_s register (provided the fault has disappeared). Bits OD1: OD0 (OUT1 and OUT0) report the channel’s switching state (On/Off) in real time, based on VHS_TH measurements. PREVIOUS ADDRESS SOA3 : SOA0 = A0001 (FAULTR_S) Bit OD8 of both Fault registers (FAULTR_s) is set simultaneously when the overtemperature prewarning (OTW) condition occurs, but the channels are not switched off (temperature of the common GND pin (#14)> TOTWAR). Reading either FAULT register clears both OTW bits. Bits OD5: OD0 of the Fault register (FAULTR_s) report the faults that occurred on the channel previously selected by bit SOA3 = A0 (Table 13).

• b i t O D 0 = OC_s: overcurrent fault on channel s,
• b i t O D 1 = SC_s: severe short-circuit on channel s,
• b i t O D 3 = OS_s: output shorted to VPWR on channel s,
• b i t O D 4 = OLOFF_s: open load in OFF state on channel s,
• b i t O D 5 = OLON_s: open load in ON state on channel s. (The threshold value above which this fault is triggered depends on the selected current sense ratio; for CSR0 @ 500 mA typ. and for CSR1 @ 7.0 mA typ.). The Fault Status pin (FS) is set to 0 (active Low) upon occurrence of any of the above mentioned faults. Latched faults can only be delatched by the procedure described in Fault Delatching. The FAULTR_s register is reset when it is read out, provided that the failure cause has disappeared and latched faults have been delatched. PREVIOUS ADDRESS SOA3 : SOA0 = A0010 (PWMR_S) The device outputs the contents of the addressed PWMR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1). PREVIOUS ADDRESS SOA3 : SOA0 = A0011 (CONFR_S) The device outputs the contents of the addressed CONFR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1). PREVIOUS ADDRESS SOA3 : SOA0 = A0100 (OCR_S) The device outputs the contents of the addressed OCR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1). PREVIOUS ADDRESS SOA3 : SOA0 = A0101 (RETRYR_S) The device outputs the contents of the addressed RETRYR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1). Bit OD8 contains the value of the OFP bit (offset positive), used for current sense offset compensation. Bits OD7: OD4 contain the real time value of the auto-retry counter. When these bits contain [0000], either auto-retry has not been enabled or Auto-retry did not occur. PREVIOUS ADDRESS SOA3 : SOA0 = 0110 (GCR) The device outputs the contents of the General Configuration Register (GCR) common to both channels. PREVIOUS ADDRESS SOA3 : SOA0 = 0111 (DIAGR_S) Bit OD8 ( Ch. 1 = CONF1) and bit OD7 ( Ch. 0 = CONF0) of the DIAGR_s register contain the values of the channels’ configuration bits (0 = bulb, 1 = DC motor) Bits OD6:OD5 contain the Product Identification (ID) number, equal to 10 for the present dual 6.0 m product. Bits OD4:OD3 report the logic state of the direct inputs IN[1:0] in real time (1 = On, 0 = OFF), OD4 = Ch. 1, OD3 = Ch. 0. Bit OD2 reports a logic [1] in case an external clock error occurred (if an external clock was selected by Clock_int = 0) Bit OD1:OD0 report logic [1] in case a calibration failure occurred during calibration of a channel’s internal clock period.

48 Freescale Semiconductor

control in case Fail-safe mode is activated (FSOB goes low). Figure 21. Typical Application with Two Different Load Types

Figure 22. Two Channels in Parallel / Recommended External Current Sense Circuit

Analog Integrated Circuit Device Data

50 Freescale Semiconductor

The 06XSD200 is packaged in a surface mount power package (PQFN), intended to be soldered directly on the printed circuit board. The maximum peak temperature during the soldering process should not exceed 260 °C for 10 seconds maximum duration. The AN2467 provides guidelines for Printed Circuit Board design and assembly. MARKING INFORMATION The device is identified by the part number: 06XSD200. Device markings indicate information on the week and year of manufacturing. The date is coded with the last four characters of the nine character build information code (e.g. “CTKAH0929”). The date is coded as four numerical digits where the first two digits indicate the year and the last two digits indicate the week. For instance, the date code “0929” indicates the 29 th week of the year 2009. PACKAGE MECHANICAL DIMENSIONS Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.freescale.com and perform a keyword search for the drawing’s document number. Package Suffix Package Outline Drawing Number 23-Pin PQFN FK 98ASA00428D

Analog Integrated Circuit Device Data Freescale Semiconductor 51 06XSD200 PACKAGING PACKAGE MECHANICAL DIMENSIONS FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE B

Analog Integrated Circuit Device Data

52 Freescale Semiconductor

PACKAGE MECHANICAL DIMENSIONS FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE B

Analog Integrated Circuit Device Data Freescale Semiconductor 53 06XSD200 PACKAGING PACKAGE MECHANICAL DIMENSIONS FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE B

Analog Integrated Circuit Device Data

54 Freescale Semiconductor

PACKAGE MECHANICAL DIMENSIONS FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE B

Analog Integrated Circuit Device Data Freescale Semiconductor 55 06XSD200 PACKAGING PACKAGE MECHANICAL DIMENSIONS FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE B

Analog Integrated Circuit Device Data

56 Freescale Semiconductor

PACKAGE MECHANICAL DIMENSIONS FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE B

Analog Integrated Circuit Device Data Freescale Semiconductor 57 06XSD200 PACKAGING PACKAGE MECHANICAL DIMENSIONS FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE B

Analog Integrated Circuit Device Data

58 Freescale Semiconductor

PACKAGE MECHANICAL DIMENSIONS FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE B

Analog Integrated Circuit Device Data Freescale Semiconductor 59 06XSD200

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 1.0 7/2013 • Initial Release based on the MC06XS4200 data sheet 2.0 9/2013 • Added note for Operating Temperature (8)

Document Number: MC06XSD200 Rev. 2.0 Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support