06XS3517_V3

06XS3517_V3 FREESCALE | Alldatasheet

Document overview

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• PDF pages: 42

Technical content

Features

• Three 6.0 mΩ and Two 17 mΩ protected high side switches
• Optional sixth channel with an external SMART MOSFET
• 16-bit SPI communication interface with daisy chain capability
• Accurate temperature & current sensing
• Fail-safe mode including autorestart
• PWM with programmable switch-on delay and frequency prescaler
• Over-voltage, under-voltage, ov er-current, over-temperature, and reverse battery protections
• Dedicated bulb over-current pr otection with inrush current handling
• Sleep mode with low current consumption
• Normal operating range 7.0 V to 20 V, extended operating range

6.0 V - 28 V

Figure 1. 06XS3517 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MC06XS3517AFK -40 °C to 125 °C 24 PQFN Bottom View VBAT CP OUT1 OUT2 OUT3 OUT4 OUT5 FETIN FETOUT VCC LIMP FLASHER IGN RSTB CLOCK CSB FOG SO SI SCLK CSNS GND 06XS3517 MCU Watchdog Smart Switch 12 V12 V 5.0 V

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Figure 2. 06XS3517 Simplified Internal Block Diagram

Figure 3. 06XS3517 Pin Connections Table 1. 06XS3517 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on Page 17. 1 FETIN Input External FET Input This pin receives the current sense signal of the external SMART MOSFET.

2 IGN Input Ignition Input

mode activation. This pin has an internal pull-down resistor. and fault registers through SPI. This digital pin has a passive internal pull-down.

4 FLASHER Input Flasher Input

pin has an internal pull-down resistor. 5 CLOCK Input/Output Clock Input This pin state depends on RSTB logic level. digital clock input by the PWM module. This pin has a passive internal pull-down.

6 LIMP Input Limp Home Input

7 FOG Input FOG Input (Active

This input wakes the device. This pin has a passive internal pull-down.

8 CSB Input Chip Select

signal returns high. This pin has a passive internal pull-up resistance.

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10 SI Input Master-Out Slave-

passive internal pull-down resistance. 11 VCC Power Logic Supply SPI logic power supply.

12 SO Output Master-In Slave-

negative edge of SCLK and when CSB is high, this pin is high-impedance. MOSFET. This output is also called OUT6. 14,17,23 GND Ground Ground This pin is the ground for the logic and analog circuitry of the device. 15 VBAT Power Battery Input Power supply pin. 16 CP Output Charge Pump This pin is the connection for an external tank capacitor (for internal use only). Protected 17 mΩ high side switch output terminals.

24 CSNS Output Current Sense

voltage proportional to the temperature on the GND flag.

1. The pins 14, 17, and 23 must be shorted on the board.

Table 1. 06XS3517 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on Page 17.

Analog Integrated Circuit Device Data Freescale Semiconductor 5 06XS3517

ELECTRICAL CHARACTERISTICS

Table 2. Maximum Ratings

2.0 Min @ 25°C

1. ESD testing is performed in accordance with the Human Body Model (HBM) (C ZAP = 100 pF, RZAP = 1500 Ω) and the Charge Device

Analog Integrated Circuit Device Data

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• 40 to 125 - 40 to 150 Peak Package Reflow Temperature During Reflow(3) TPPRT 260 °C Storage Temperature TSTG - 55 to 150 °C THERMAL RESISTANCE Thermal Resistance, Junction to Case(4) RθJC 1.0 °K/W Notes 3. Pin soldering temperature limit is for 40 seconds maximum dura tion. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 4. Typical value guaranteed per design.

Table 2. Maximum Ratings (continued)

Analog Integrated Circuit Device Data Freescale Semiconductor 7 06XS3517 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics

3.0 MHz SPI communication

1. In extended mode, the functionality is guar anteed but not the electrical parameters.
2. Outputs shorted to ground, I OUT = + 500 mA and IOUT = OCHI (guaranteed by design).
3. Valid for RST, SI, SCLK, CS, CLOCK, IGN, FLASHER, FOG, and LIMP pins.
4. Valid for the following input voltage range: -0.3 V to VCC +0.3 V.

Analog Integrated Circuit Device Data

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STATIC ELECTRICAL CHARACTERISTICS LOGIC INPUT/OUTPUT (IGN, CS, CSNS, SI, SCLK, CLOCK, SO, FLASHER, RST, LIMP, FOG) (CONTINUED) SO High-state Output Voltage IOH = 1.0 mA VSOH 0.8 0.95 – VCC SO Low-state Output Voltage IOL = -1.6 mA VSOL – 0.2 0.4 V CLOCK Output Voltage Reporting Wake-up Event (ICLOCK=1.0mA) VCLOCKH 0.8 0.95 – VCC SO and CSNS Tri-state Leakage Current ISOLEAK - 1.0 0.0 1.0 μA Current Sense Output Clamp Voltage CSNS open and IOUT[1:5] = IFSR VCSNS 5.0 6.0 7.0 V OUTPUTS (OUT 1-5) Output Negative Clamp Voltage IOUT = - 500 mA, Outputs OFF VOUT - 22.0 – -16.0 V Output Leakage Current in OFF State Sleep mode, outputs grounded, TA = 25 °C Sleep mode, outputs grounded, TA = 125 °C Normal mode, outputs grounded ILEAK(OFF) 0.0 0.0 2.0 3.0 µA Current Sense Error(9) over the Full Voltage and Temperature Range %Full Scale Range (FSR), LED Control bit = 0, Channels 1,5 (17 mΩ) point @ 0.75 FSR point @ 0.50 FSR point @ 0.25 FSR point @ 0.1 FS point @ 0.05FSR % Full-Scale Range (FSR), LED Control bit =0, Channels 2,3,4 (6.0 mΩ) point @ 0.75 FSR point @ 0.50 FSR point @ 0.25 FSR point @ 0.1 FSR ΔICS / ICS -14 -15 -17 -25 -40 -14 -15 -17 -34 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 Current Sense error with one calibration point (50% FSR, VBAT = 13.5 at 25 °C(10) -6.0 – 6.0 % Current Sense error with one calibration point (50% FSRLED, VBAT = 13.5 at 25 °C(10) -6.0 – 6.0 % Temperature Drift of Current Sense Output(11) VBAT = 13.5 V, IOUT1,5 = 2.8 A, IOUT2-4 = 5.5 A, reference taken at TA=25 °C Δ ICS /ΔT – ±280 ± 400 ppm/°C Over-temperature Shutdown TOTS 155 175 195 °C Notes 9. 10 V < VBAT < 16 V. ΔICS / ICS = (measured ICS - targeted ICS)/ targeted ICS with targeted ICS = 5.0 mA. Test conditions of accuracy measurement of point I(HS[1]) @ 0.05*FSR: I(HS[5]) = 0, I(HS[2]) = I(HS[3]) = I(HS[4]) =8.0 A 10. Based on statistical analysis covering 99.74% of parts, except 10% of FSR. Refer to Current Sense section for more details. 11. Based on statistical data. Not production tested. Δ ICS /ΔT=[(measured ICS at T1 - measured ICS at T2) / measured ICS at room] / (T1 -T2) Table 3. Static Electrical Characteristics (continued)

Analog Integrated Circuit Device Data Freescale Semiconductor 9 06XS3517 STATIC ELECTRICAL CHARACTERISTICS OUTPUTS (OUT 1-5) (CONTINUED) Thermal Prewarning(12) TOTSWARN 110 125 140 °C Output Voltage Threshold VOUT_TH 0.475 0.5 0.525 VBAT CHANNEL 1 - PARKING LIGHT (17 mΩ CHANNEL) Output Drain-to-Source ON Resistance (IOUT = 2.8 A, TA = 25 °C) VBAT = 13.5 V VBAT = 7.0 V RDS(ON)25 26.7 mΩ Output Drain-to-Source ON Resistance (IOUT = 2.8 A, VBAT = 13.5 V, TA = 150 °C)(12) RDS(ON)150 – – 28.9 mΩ Reverse Output ON Resistance (IOUT = -2.8 A, TA = 25 °C)(13) VBAT = -12 V RSD(ON) – – 34 mΩ High Over-current Shutdown Threshold 1, VBAT = 16 V IOCHI1 48 56.2 72 A High Over-current Shutdown Threshold 2 IOCHI2 21.0 25.8 30.5 A Low Over-current Shutdown Threshold IOCLO 9.0 11.5 14 A Open Load-current Threshold in ON State(14) IOL 0.08 0.3 0.77 A Open Load-current Threshold in ON State with LED(15) VOUT = VBAT - 0.8 V IOLLED 4.0 10.0 20.0 mA Current Sense Full-scale Range(16) ICS FSR – 9.5 – A Severe Short-circuit Impedance Range(17) RSC1(OUT1) 225 – – mΩ CHANNEL 2 - LOW BEAM (6.0 mΩ CHANNEL) Output Drain-to-Source ON Resistance (IOUT = 5.5 A, TA = 25 °C) VBAT = 13.5 V VBAT = 7.0 V RDS(ON)25 6.0 9.0 mΩ Output Drain-to-Source ON Resistance (IOUT = 5.5 A, VBAT = 13.5 V, TA = 150 °C)(17) RDS(ON)150 – – 10.2 mΩ Reverse Source-to-Drain ON Resistance (IOUT = -5.5 A, TA = 25 °C)(18) VBAT = -12 V RSD(ON) – – 12.0 mΩ High Over-current Shutdown Threshold 1, VBAT = 16 V IOCHI1 96 123 150 A High Over-current Shutdown Threshold 2 IOCHI2 40 50.5 61 A Notes 12. Parameter guaranteed by design, however, it is not production tested. 13. Source-to-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VBAT. 14. OLLED1, bit D0 in SI data is set to [0]. 15. OLLED1, bit D0 in SI data is set to [1]. 16. For typical value of I CS FSR, ICSNS = 5.0 mA. 17. Parameter guaranteed by design; however, it is not production tested. 18. Source-to-Drain ON resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VBAT.

Analog Integrated Circuit Device Data

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STATIC ELECTRICAL CHARACTERISTICS CHANNEL 2 - LOW BEAM (6.0 mΩ CHANNEL) (CONTINUED) Low Over-current Shutdown Threshold Optional Xenon lamp Optional H7 bulb IOCLO 22.5 A Open Load Current Threshold in ON State(19) IOL 0.15 0.62 1.55 A Open Load Current Threshold in ON State with LED(20) VOL = VBAT - 0.8 V IOLLED 4.0 10.0 20.0 mA Current Sense Full-scale Range(21) Optional Xenon bulb Optional H7 bulb ICS FSR A Severe Short-circuit Impedance Range(22) RSC1(OUT2) 65 – – mΩ CHANNEL 3- HIGH BEAM (6.0 mΩ CHANNEL) Output Drain-to-Source ON Resistance (IOUT = 5.5 A, TA = 25 °C) VBAT = 13.5 V VBAT = 7.0 V RDS(ON)25 6.0 9.0 mΩ Output Drain-to-Source ON Resistance (IOUT = 5.5 A, VBAT = 13.5 V, TA = 150 °C)(22) RDS(ON)150 – – 10.2 mΩ Reverse Source-to-Drain ON Resistance (IOUT = -5.5 A, TA = 25 °C)(23) VBAT = -12 V RSD(ON)25 – – 12 mΩ High Over-current Shutdown Threshold 1, VBAT = 16 V IOCHI1 96 123 150 A High Over-current Shutdown Threshold 2 IOCHI2 40 50.5 61 A Low Over-current Shutdown Threshold H7 Bulb IOCLO 17 22.5 28 A Open Load Current Threshold in ON State(24) IOL 0.15 0.62 1.55 A Open Load Current Threshold in ON State with LED(25) VOL = VBAT - 0.8 V IOLLED 4.0 10.0 20.0 mA Current Sense Full-scale Range (21) ICS FSR – 19 – A Severe Short-circuit Impedance Range(22) RSC1(OUT3) 65 – – mΩ Notes 19. OLLED2, bit D1 in SI data is set to [0]. 20. OLLED2, bit D1 in SI data is set to [1]. 21. For typical value of I CS FSR, ICSNS = 5.0mA. 22. Parameter guaranteed by design; however, it is not production tested. 23. Source-to-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VBAT. 24. OLLED3, bit D2 in SI data is set to [0]. 25. OLLED3, bit D2 in SI data is set to [1].

Analog Integrated Circuit Device Data Freescale Semiconductor 11 06XS3517 STATIC ELECTRICAL CHARACTERISTICS CHANNEL 4 - FOG LIGHT(6.0 mΩ CHANNEL) Output Drain-to-Source ON Resistance (IOUT = 5.5 A, TA = 25 °C) VBAT = 13.5 V VBAT = 7.0 V RDS(ON)25 6.0 9.0 mΩ Output Drain-to-Source ON Resistance (IOUT = 5.5 A, VBAT = 13.5 V, TA = 150 °C)(26) RDS(ON)150 – – 10.2 mΩ Reverse Source-to-Drain ON Resistance (IOUT = -5.5 A, TA = 25 °C)(27) VBAT = -12 V RSD(ON)25 – – 12 mΩ High Over-current Shutdown Threshold 1, VBAT = 16 V IOCHI1 96 123 150 A High Over-current Shutdown Threshold 2 IOCHI2 40 50.5 61 A Low Over-current Shutdown Threshold H7 Bulb IOCLO 17 22.5 28 A Open Load Current Threshold in ON State(28) IOL 0.15 0.62 1.5 A Open Load Current Threshold in ON State with LED(29) VOL = VBAT - 0.8 V IOLLED 4.0 10.0 20.0 mA Current Sense Full Scale Range(30) ICS FSR – 19 – A Severe Short-circuit Impedance Range(26) RSC1(OUT4) 65 – – mΩ CHANNEL 5 - FLASHER (17 mΩ CHANNEL) Output Drain-to-Source ON Resistance (IOUT = 2.8 A, TA = 25 °C) VBAT = 13.5 V VBAT = 7.0 V RDS(ON)25 26.7 mΩ Output Drain-to-Source ON Resistance (IOUT = 2.8 A, VBAT = 13.5 V, TA = 150 °C)(31) RDS(ON)150 – – 18.9 mΩ Reverse Source-to-Drain ON Resistance (IOUT = -2.8A, TJ = 25°C)(32) VBAT = -12V RSD(ON)25 – – 34 mΩ High Over-current Shutdown Threshold 1, IOCHI1 48 56.2 72 A High Over-current Shutdown Threshold 2 IOCHI2 21.0 25.8 30.5 A Low Over-current Shutdown Threshold IOCLO 9.0 11.5 14 A Notes 26. Parameter guaranteed by design; however, it is not production tested. 27. Source-to-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VBAT. 28. OLLED4, bit D3 in SI data is set to [0]. 29. OLLED4, bit D3 in SI data is set to [1]. 30. For typical value of I CS FSR, ICSNS = 5.0 mA. 31. Parameter guaranteed by design; however, it is not production tested. 32. Source-to-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VBAT.

Analog Integrated Circuit Device Data

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STATIC ELECTRICAL CHARACTERISTICS CHANNEL 5 - FLASHER (17 mΩ CHANNEL) (CONTINUED) Open Load Current Threshold in ON State(33) IOL 0.08 0.3 0.77 A Open Load Current Threshold in ON State with LED(34) VOL = VBAT - 0.8 V IOLLED 4.0 10.0 20.0 mA Current Sense Full Scale Range(35) ICS FSR – 8.8 – A Severe Short-circuit Impedance Range(36) RSC1(OUT5) 225 – – mΩ SPARE FETOUT(OUT6) / FETIN (OUT1) FETOUT Output High Level @ I = 1.0 mA VH MAX 0.8 – – VCC FETOUT Output Low Level @ I = -1.0 mA VH MIN – 0.2 0.4 V FETIN Input Full Scale Range Current IFET IN – 5.0 – mA FETIN Input Clamp Voltage IFET IN = 5.0 mA, CSNS open VCLIN 5.3 – 13 V Drop Voltage on FETIN (FETIN - CSNS) IFET IN = 5.0 mA, 5.5 V > CSNS > 3.0 V VDRIN 0.0 – 0.4 V FETIN Leakage Current When External Current Switch Sense Is Enabled 5.5 V > VFET IN > 0.0 V, CSNS open IFETINLEAK - 1.0 – 6.0 μA TEMPERATURE OF GND FLAG Analog Temperature Feedback Range TFEED_RANGE -40 – 150 °C Analog Temperature Feedback at TA = 25 °C with 5.0 kΩ > RCSNS > 500 Ω VT_FEED 925 1000 1075 mV Analog Temperature Feedback Derating with 5.0 kΩ > RCSNS > 500 Ω (36) VDT_FEED 10.9 11.3 11.7 mV/°C Analog Temperature Feedback Precision (36) VDT_ACC -15 – 15 °C Analog Temperature Feedback Precision with calibration point at 25 °C (36) VDT_ACC_CAL -5.0 – 5.0 °C Notes 33. OLLED5, bit D4 in SI data is set to [0]. 34. OLLED5, bit D4 in SI data is set to [1]. 35. For typical value of I CS FSR, ICSNS = 5.0 mA. 36. Parameter guaranteed by design; however, it is not production tested.

Analog Integrated Circuit Device Data Freescale Semiconductor 13 06XS3517 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics

1. Not production tested. See Figure 7, Current Sensing Time Delays.

Analog Integrated Circuit Device Data

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DYNAMIC ELECTRICAL CHARACTERISTICS POWER OUTPUTS TIMING (OUT1 TO OUT5) (CONTINUED) Driver Output Matching Time (t DLY(ON) - t DLY(OFF)) @ Output = 50% VBAT with VBAT = 14 V, f PWM = 240 Hz, δPWM = 50%, @25 °C SR bit = 0: IOUT = 2.8 A for OUT1 and OUT5 and IOUT = 5.5 A for OUT2/3/4 SR bit = 1: IOUT = 0.7 A for OUT1 and OUT5 and IOUT = 1.4 A for OUT2/3/4 Δ t RF 5.0 200 μs PWM MODULE PWM Frequency Range f PWM 60.0 – 400 Hz Clock Input Frequency Range f CLK 7.68 – 51.2 kHz Output PWM Duty Cycle maximum range for 11 V<VBAT<18 V(38), (39) PWM_MAX 4.0 – 96 % Output PWM Duty Cycle linear range for 11 V<VBAT<18 V(40) PWM_LIN 5.5 – 96 % WATCHDOG TIMING Watchdog Timeout (SPI Failure) t WDTO 50 75 100 ms I/O PLAUSIBILITY CHECK TIMING Fault Shutdown Delay Time (from Over-temperature or OCHI1 or OCHI2 or OCLO or UV Fault Detection to Output = 50% VBAT without round shaping feature for turn off) t SD – 7.0 30 μs High Over-current Threshold Time 1 for OUT1 and OUT5 for OUT2, OUT3, and OUT4 t 1 7.0 13.5 ms High Over-current Threshold Time 2 for OUT1 and OUT5 for OUT2, OUT3, and OUT4 t 2 52.5 105 150 97.5 195 ms Autorestart Period for OUT1 and OUT5 for OUT2, OUT3, and OUT4 tAUTORST 52.5 105 150 97.5 195 ms Autorestart Over-current Shutdown Delay Time for OUT1 and OUT5 for OUT2, OUT3, and OUT4 t OCHI_AUTO 3.5 7.0 5.0 10.0 6.5 13.0 ms Limp Home Input pin Deglicher Time t LIMP 7.0 10.0 13.0 ms Cyclic Open Load Detection Timing with LED(41) t OLLED 105 150 195 ms Flasher Toggle Timeout t FLASHER 1.4 2.3 3.0 s Fog Toggle Timeout t FOG 1.4 2.3 3.0 s Notes 38. Not production tested. See Figure 7, Current Sensing Time Delays. 39. The PWM ratio is measured at V OUT = 50% of VBAT in nominal range of PWM frequency (from 60 Hz to 400 Hz). It is possible to put the device fully on (PWM duty cycle = 100%) and fully off (PWM duty cycle = 0%). Between 4%-96%, OCHI1,2, OCLO and open load are available in ON state. See Figure 6, Output Slew Rate and Time Delays. 40. Linear range is defined by output duty c ycle to SPI duty cycle configuration +/-1 LSB. For values outside linear duty cycle range, a calibration curve is available. 41. IOLLEDn bit (where “n” corresponds to respective outputs 1 through 5) in SI data is set to logic [1]. Refer to Table 8, Serial Input Address and Configuration Bit Map, page 25.

Analog Integrated Circuit Device Data Freescale Semiconductor 15 06XS3517 DYNAMIC ELECTRICAL CHARACTERISTICS I/O PLAUSIBILITY CHECK TIMING (CONTINUED) Ignition Toggle Timeout t IGNITION 1.4 2.3 3.0 s Clock Input Low Frequency Detection Range f LCLK DET 1.0 2.0 4.0 kHz Clock Input High Frequency Detection Range f HCLK DET 100 200 400 kHz SPI INTERFACE CHARACTERISTICS Maximum Frequency of SPI Operation f SPI – – 3.0 MHz Rising Edge of CSB to Falling Edge of CSB (Required Setup Time)(42) t CSB – – 1.0 us Falling Edge of CSB to Rising Edge of SCLK (Required Setup Time)(42) t LEAD – – 500 ns Required High State Duration of SCLK (Required Setup Time)(42) t WSCLKH – – 167 ns Required Low State Duration of SCLK (Required Setup Time)(42) t WSCLKL – – 167 ns Falling Edge of SCLK to Rising Edge of CSB (Required Setup Time)(42) t LAG – 50 167 ns SI to Falling Edge of SCLK (Required Setup Time)(43) t SI(SU – 25 83 ns Falling Edge of SCLK to SI (Required Setup Time)(43) t SI HOLD – 25 83 ns SO Rise Time CL = 80 pF t RSO – 25 50 ns SO Fall Time CL = 80 pF t FSO – 25 50 ns SI, CSB, SCLK Incoming Signal Rise Time(43) t RSI – – 50 ns SI, CSB, SCLK Incoming Signal Fall Time(43) t FSI – – 50 ns Time from Falling Edge of SCLK to SO Low-impedance(44) t SO(EN) – – 145 ns Time from Rising Edge of SCLK to SO High-impedance(45) t SO(DIS) – 65 145 ns Notes 42. Maximum setup time required for the 06XS3517 is the minimum guaranteed time needed from the microcontroller. 43. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. 44. Time required for output status data to be available for use at SO. 1.0 kΩ on pull-up on CSB. 45. Time required for output status data to be terminated at SO. 1.0 kΩ on pull-up on CSB.

Analog Integrated Circuit Device Data

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Figure 4. Input Timing Switching Characteristics Figure 5. SCLK Waveform and Valid SO Data Delay Time

0.7 VDD

0.2 VDD

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from the switching MOSFETs to the printed circuit board. This pin is the ground of the device. frequency per output, depending PR bit value. with a resolution of 7 bits of the duty cycle (bits D[6:0]). Figure 5 describes the PWM resolution. behavior of the light module. following pictures illustrate this behavior.

• With the following SPI configuration: D7:D0=FF.
• In case of clock input signal failure (out of f PWM), the outputs state depends of D7 bit value (D7=1=ON) in Normal mode. In Fail mode, the ouputs state depend on IGN, FLASHER, and FOG pins. If RSTB=0, this pin reports the wake-up event for wake=1 when VBAT and VCC are in operational voltage range. LIMP HOME INPUT (LIMP) The Fail mode of the component can be activated by this digital input port. The signal is “high active”, meaning the Fail mode can be activated by a logic high signal at the input. IGNITION INPUT (IGN) The ignition input wakes the device. It also controls the Fail mode activation. The signal is “high active”, meaning the component is active in case of a logic high at the input.

Table 5. PWM Resolution

0 X OFF

Analog Integrated Circuit Device Data Freescale Semiconductor 19 06XS3517 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION FLASHER INPUT (FLASHER) The flasher input wakes the device. It also controls the Fail Mode activation. The signal is “high active”, meaning the component is active in case of a logic high at the input. FOG INPUT (FOG) The fog input wakes the device. It also controls the Fail Mode activation. The signal is “high active”, meaning the component is active in case of a logic high at the input. RESET INPUT (RSTB) This input wakes the device when the RSTB pin is at logic [1]. It is also used to initialize the device configuration and the SPI faults registers when the signal is low. All SI/SO registers described Table 8 and Table are reset. The fault management is not affected by RSTB (see Figure 2). CURRENT SENSE OUTPUT (CSNS) The current sense output pin is an analog current output or a voltage proportional to the temperature on the GND flag. The routing to the external resistor is SPI programmable. This current sense monitoring may be synchronized in case of the OUT6 is not used. The CSNS output is valid after a rising edge on the FETOUT pin (after tsync(val) s.) if the CSNS sync SPI bit was set to logic [0] and remains valid till a falling edge is generated. Connection of the FETOUT pin to a MCU input pin allows the MCU to sample the CSNS pin during a valid time slot. Since this falling edge is generated at the end of this time slot, upon a switch-off command, this feature may be used to implement maximum current control. CHARGE PUMP (CP) An external capacitor must be connected between the CP and the VBAT pin. It is used as a tank for the internal charge pump. Its value is 100 nF ± 20%, 25 V maximum. FET OUT OUTPUT (FETOUT) This output pin can be used to control an external SMART MOSFET (OUT6) at a logic level (1=ON, 0=OFF). The high level of the FETOUT Output is VCC, if VBAT and VCC are available, in case FETOUT is a controlled ON. FETOUT is not protected if there is a short-circuit or under- voltage on VBAT. In case of a reverse battery, OUT6 is OFF. FET IN INPUT (FETIN) This input pin receives the current recopy from an external SMART MOSFET. It can be routed on CSNS output by a SPI command. SPI PROTOCOL DESCRIPTION The SPI interface has a full-duplex, three-wire, synchronous data transfer with four I/O lines associated with it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO), and Chip Select (CSB). The SI/SO pins of the 06XS3517 device follow a first-in, first-out (D15 to D0) protocol, with both input and output words transferring the most significant bit (MSB) first. All inputs are compatible with 3.3 V and 5.0 V CMOS logic levels, supplied by VCC. The SPI lines perform the following functions: SERIAL CLOCK (SCLK) The SCLK pin clocks the internal shift registers of the 06XS3517 device. The SI pin accepts data into the input shift register on the falling edge of the SCLK signal, while the SO pin shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important that the SCLK pin be in a logic low state whenever CSB makes any transition. For this reason, it is recommended the SCLK pin be in a logic [0] whenever the device is not accessed (CSB logic [1] state). SCLK has a passive pull-down, RDWN. When CSB is logic [1], signals at the SCLK and SI pins are ignored, and SO is tri-stated (high-impedance) (see Figure 8).

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Figure 8. Single 16-Bit Word SPI Communication The SI pin is a serial interface command data input pin. D15 to D0. SI has a passive pull-down, RDOWN.

1. RSTB is in a logic H state during the above operation.
2. DO, D1, D2, ... , and D15 relate to the most recent ordered entry of program data into the LUX IC
3. OD0, OD1, OD2, ..., and OD15 relate to the first 16 bits of ordered fault and status data out of the LUX IC
4. D15 : D0 relate to the most recent ordered entry of data into the device.
5. OD15 : OD0 relate to the first 16 bits of ordered fault and status data out of the device.

The Sleep mode is the default mode of the 06XS3517. addition, all SPI-configurable features of the device are reset. depending on wake and fail signals (see Fig13).

• Wake = IGN or IGN_ON or FLASHER or FLASHER_ON or RSTB or FOG or FOG_ON
• Fail = VCC fail or SPI fail or External limp NORMAL MODE The 06XS3517 is in Normal mode when:
• Wake = 1
• Fail = 0 In Normal operating mode the power outputs are under full control of the SPI as follows:
• The outputs 1 to 6, including multiphase timing and selectable slew-rate, are controlled by the programmable PWM module.
• The outputs 1 to 5 are switched OFF in case of an under-voltage on VBAT.
• The outputs 1 to 5 are protec ted by the selectable over- current double window and over-temperature shutdown circuit.
• The digital diagnosis featur e transfers status of the smart outputs via SPI.
• The analog current sense output (current recopy feature) can be routed by SPI.
• The outputs 1 and 5 can be configured to control LED loads.
• The SPI reports NM=1 in this mode. The figure below describes the PWM, outputs and over- current behavior in Normal mode. FAIL MODE The 06XS3517 is in Fail mode when:
• Wake = 1
• Fail = 1. In Fail mode:
• The outputs are under control of external pins (see Table 6)
• The outputs are fully protect ed in case of an overload, over-temperature and under-voltage (on VBAT or on VCC).
• The SPI reports continuously the content of address 11 (Initialization register), regardless previously requested output data word.
• Analog current sense is not available.
• Output 2 is configured in Xenon mode.
• In case of an overload (OCHI2 or OCLO) conditions or under-voltage on VBAT, the outputs are under control of autorestart feature.
• In case of serious overload condition (OCHI1 or OT) the corresponding output is latched OFF until a new wake- up event (wake=0 then 1).

Table 6. Output States During Limp Home

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condition on VBAT (see Figure 12). The autorestart periodically switches ON the outputs. tochi_Auto, then after the output is protected by OCLO. Figure 9. Over-current window in case of Autorestart only after the autorestart period (tAUTORST-T1 or tAUTORST-T2). The Autorestart is not limited in time. transition into Normal mode.

• VBAT and VCC power supplie s must be above their under-voltage thresholds (Sleep mode).
• generate wake up event (wake=1) from 0 to 1 on RSTB . The device switches to Normal mode.
• apply PWM clock after maximum 200 μs (min 50 μs).
• send SPI command to the Device status register to clear the clock fail flag to enable the PWM module to start. Figure 10 describes the wake-up block diagram. POWER OFF MODE The 06XS3517 is in Power OFF mode when the battery voltage is below VBATPOR[1,2] thresholds. For more details, refer to Loss of VBAT. Output current OCHI1 OCLO time tochi_auto Auto period OCLO or UV fault

Figure 10. Operating Modes State Machine

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Figure 11. Wake-up Block Diagram

to latch in a message that is not 16 bits will be ignored. equal 0 or fail mode (Fail=1). section. Table 8 summarizes the SI registers. Table 7. SI Message Bit Assignment MSB D15 : D11 Register address bits. protection features, and SO status content. Table 8. Serial Input Address and Configuration Bit Map

1 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Note: testmode address used only by FSL is D[15:11]=01111 with RSTB pin voltage higher than 8.0 V typ.

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synchronize the switching phases between different devices. and to active the LED Control. Two configuration registers are available at this address. Configuration SR when D9 bit is set to logic [1]. divided by 2) is activated for the dedicated output. current sense analog feedback. synchronization signal is reported on FETOUT output pin. of under-voltage fault detection. Table 9. Initialization Register Table 10. Switching Phases

duty cycle resolution is given by bits D6 : D0. D7 = 1, D6 : D0 = 7F output continuous ON (no PWM). SPI during normal operation. and SOA0 defined in the last SPI initialization word). feature is useful for daisy chaining devices. accept new fault status information.

• The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid SPI communication never occurred.
• Battery transients below 6.0 V, resulting in an under- voltage shutdown of the outputs, may result in incorrect data loaded into the status register. SERIAL OUTPUT BIT ASSIGNMENT The contents of bits OD15 : OD0 depend on bits D1: D0 from the most recent initialization command SOA[1:0] (refer to Table 8), and as explained in the paragraphs that follow. The register bits are reset by a read operation and also if the fault is removed. Table 11 summarizes the SO register content. Bit OD10 reflects Normal mode (NM).

Table 11. Serial Output Bit Map Description

4 OD13 OD12 OD11 OD1

0 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0

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If the previous two LSBs are 01, bits OD15 :O D0 reflect the temperature status (Table 13). If the previous two LSBs are 10, bits OD15 : OD0 reflect the status of the 06XS3517 (Table 14). Table 12. Fault Status Flag at Outputs 5 through 1, respectively. A logic [1] at bits OD9:OD0 indicates a fault. If there is no fault, bits OD9:OD0 are logic [0]. Table 13. Overload Status A logic [1] at bits OD9:OD0 indicates a fault. If there is no fault, bits OD9:OD0 are logic [0]. Table 14. Device Status content of this bit is reset by read operation.

status of the 06XS3517 (Table 14).

• Protection against transients on V BAT supply line (per ISO 7637)
• Active clamp, including protection against negative transients on output line
• Over-temperature
• Severe and resistive over-current
• Open Load during ON state These protections are provided for each output (OUT1:5). Over-temperature Detection The 06XS3517 provides over-temperature shutdown for each output (OUT1:OUT5 ). It can occur when the output pin is in the ON or OFF state. An over-temperature fault condition results in turning OFF the corresponding output. The fault is latched and reported via SPI. To delatch the fault and be able to turn ON again the outputs, the failure condition must be removed (T< 175 °C, typically) and:
• if the device was in Normal mode, the output corresponding register (bit D7) must be rewritten. during t2) depends on toggling or not toggling the D7 bit.
• if the device was in Fail mode, the corresponding output is locked until restart of the device: wake-up from Sleep mode or VBATPOR1. The corresponding SPI fault report (OTS bit) is removed after a read operation. Over-current Detections The 06XS3517 provides a dynamic over-current shutdown protection (see Figure 12) in order to protect the internal power transistors and the harness in the event of overload (fuse characteristic).

Figure 12. Two-segment Over-current Window in was actually in the ON state. Table 15. Output Status

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• if the device was in Normal mode: the channel’s associated on/off bit (bit D7) must be rewritten D7=1. Application of complete OCHI window depends on toggling or not toggling D7 bit.
• if the device was in Fail mode, the failure is locked until restart of the device: wake-up from Sleep mode or VBATPOR1. For OCHI2 and OCLO:
• if the device was in Normal mode: channel’s associated on/off bit (bit D7) must be rewritten D7=1. Application of complete OCHI window depends on toggling or not toggling D7 bit.
• if the device was in Fail mode, Autorestart is activated. The device Autorestart feature opens a fixed window width and restarts at a fixed period with OCHI1 window. Autorestart feature resets OCHI2 or OCLO fault after corresponding Autorestart period. The SPI fault reports are removed together after a read operation: - OC bit=(OCHI1) or (OCHI2) fault - OVL bit=(OCHI1) or (OCHI2) or (OCLO) fault Over-voltage detection and active clamp The 06XS3517 possesses an active gate clamp circuit in order to limit the maximum drain to source voltage. In case of overload on an output the corresponding switch (OUT[1 to 5]) is turned off which leads to high-voltage at VBAT with an inductive VBAT line. The maximum VBAT voltage is limited at V BATCLAMP by automatically turning on the channel. In case of open load condition, the positive transient pulses (ISO 7637 pulse 2 and inductive battery line) shall also be handled by the application. Figures 13 and 14 describe the faults management in Normal mode and Fail mode.

Figure 13. Faults Management in Normal Mode (for OUT[1:5] Only) Note: t1 and t2 refer to Figure 12.

Figure 14. Faults Management in Fail Mode (for OUT[1:5] Only) output (OUT1:OUT5 ) when the output pin is in the ON state. Power on Reset on VBAT, the fault will be reset. output switch without overshoot (aperiodic settling). The current recopy is not active in Fail mode. range (10 V to 16 V) and temperature range (-40 to 125 °C). Note: * See Autorestart strategy chapter.

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Figure 15. Temperature sensing voltage Figure 16. Analog Temperature Precision with needed. In case of a Power on Reset, the fault will be reset. and IGN pins via the SPI in real time and in Normal mode. failures inside the component or the light module.

• Reverse Polarity
• Loss of Supply Lines
• Fatal Mistreatment of Logic I/O Pins REVERSE POLARITY PROTECTION ON VBAT In case of a permanently reverse voltage operation, the channels are turned ON (RSD Ohm) in order to prevent thermal overloads. No protections are available. An external diode on VCC is necessary in order to protect the 06XS3517 in cases from reverse polarity. In case of negative transients on the VBAT line (per ISO 7637), the VCC supplied functions are still available operating, while the VBAT line is negative. Without loads on OUT1:5 pin, an external clamp between VBAT and GND is mandatory to avoid exceeding maximum ratings. The maximum external clamp voltage shall be between the reverse battery condition and -20 V. Therefore, the device is protected against latch-up with or without load on OUT outputs. LOSS OF SUPPLY LINES The 06XS3517 is protected against the loss of any supply line. The detection of the supply line failure is provided inside the device itself. LOSS OF VBAT During an under-voltage of VBAT (VBATPOR1 < VBAT < VBATUV), the outputs [1-5] are switched off immediately. No current path from VBAT to VCC exists. The external MOSFET (OUT6) can be controlled in Normal mode by the SPI if VCC is above VCCUV. The fault is reported to the UVF bit (OD13). To delatch the fault, the under-voltage condition should be removed and:
• To turn-on the output, the corresponding D7 bit must be rewritten to logic [1] in Normal mode. Application of the OCHI window depends on toggling or not toggling the D7 bit.
• If the device was in Fail mode, the fault will be delatched by the Autorestart feature periodically. 0.5 1.5 2.5 -40 -20 0 20 40 60 80 100 120 140 160 180 Board temperature (°C) CSNS feedback (V) typ min max 0.5 1.5 2.5 -40 -20 0 20 40 60 80 100 120 140 160 180 Board temperature (°C) CSNS feedback (V) typ min max

• all latched faults are reset if VCC < V CCUV,
• all latched faults are maintained under V CC in nominal conditions. In case VBAT is disconnected, OUT[1:5] outputs are OFF. OUT6 output state depends on the previous SPI configuration. The SPI configuration, reporting, and daisy-chain features are provided for RST is set to logic [1]. The SPI pull-up and pull-down current resistors are available. This fault condition can be diagnosed with UVF fault in OD13 reporting bit. The previous device configuration is maintained. No current is conducted from V CC to VBAT. LOSS OF VCC (DIGITAL LOGIC SUPPLY LINE) During loss of VCC (VCC < VCCUV ) and with wake=1, the 06XS3517 is switched automatically into Fail mode. The external SMART MOSFET is turned OFF. All SPI registers are reset and must be reprogrammed when VCC goes above VCCUV. The device will transit in OFF mode if VBAT < VBATPOR2. LOSS OF VCC AND VBAT If the external VBAT and VCC supplies are disconnected (or not within specification: (VCC and VBAT) < VBATPOR1), all SPI register contents are reset with default values corresponding to all SPI bits are set to logic [0] and all latched faults are also reset. LOSS OF GROUND (GND) During loss of ground, the 06XS3517 cannot drive the loads (the outputs (1:5) are switched OFF), but is not destroyed by the operating condition. Current limit resistors in the digital input lines protect the digital supply against excessive current (1.0 kOhm typical). The state of the external smart power switch controlled by FETOUT is not guaranteed, and the state of external smart MOS is defined with an external termination resistor. FATAL MISTREATMENT OF LOGIC I / O PINS The digital I / Os are protected against fatal mistreatment by signal plausibility check according to Table 16. In case the LIMP input is set to logic [1] for a delay longer than 10 ms typical, the 06XS3517 is switched into Fail mode. In case of a (PWM) Clock failure, no PWM feature is provided and the bit D7 defines the outputs state. In case of SPI failure, the 06XS3517 is switched into Fail mode (see Figure 17)

Figure 17. Watchdog window Table 16. Logic I / O Plausibility Check

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light substitution mode, and Fail mode. Figure 18. 06XS3517 Typical Application Standby mode with 22 nF decoupling capacitor on OUT[1:5].

Analog Integrated Circuit Device Data Freescale Semiconductor 35 06XS3517 PACKAGING PACKAGING DIMENSIONS PACKAGING PACKAGING DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. FK SUFFIX 24-PIN PQFN 98ART10511D ISSUE 0

Analog Integrated Circuit Device Data

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Analog Integrated Circuit Device Data Freescale Semiconductor 37 06XS3517 PACKAGING PACKAGING DIMENSIONS FK SUFFIX 24-PIN PQFN 98ART10511D ISSUE 0

Analog Integrated Circuit Device Data

38 Freescale Semiconductor

Analog Integrated Circuit Device Data Freescale Semiconductor 39 06XS3517 PACKAGING

Analog Integrated Circuit Device Data

40 Freescale Semiconductor

Analog Integrated Circuit Device Data Freescale Semiconductor 41 06XS3517

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 1.0 2/2012 • Initial release 2.0 2/2012 • Corrected ordering information from MC06XS3517FK to MC06XS3517AFK

• Updated 98A package drawing 3.0 9/2012 • Changed Input Passive Pull-down Resistance on SI, SCLK, FLASHER, IGN, FOG, CLOCK, LIMP, RST pins(8) maximum fro 400 to 500 k

Document Number: MC06XS3517 Rev. 3.0 Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: store.esellerate.net/store/ Policy.aspx?Selector=RT&s=STR0326182960&pc. How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C-Ware, Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony, and V ortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, MagniV , MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.