STM32F103X6 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Introduction
- 2 Description
- 2.1 Device overview
- 2.2 Overview
- 3 Pin descriptions
- 4 Memory mapping
- 5 Electrical characteristi cs
- 5.1 Test conditions
- 5.1.1 Minimum and maximum values
- 5.1.2 Typical values
- 5.1.3 Typical curves
- 5.1.4 Loading capacitor
- 5.1.5 Pin input voltage
- 5.1.6 Power supply scheme
- 5.1.7 Current consumption measurement
- 5.2 Absolute maximum ratings
- 5.3 Operating conditions
- 5.3.1 General operating conditions
- 5.3.2 Operating conditions at power-up / power-down
- 5.3.3 Embedded reset and power control block characteristics
- 5.3.4 Embedded reference voltage
- 5.3.5 Supply current characteristics
- 5.3.6 External clock source characteristics
- 5.3.7 Internal clock source characteristics
- 5.3.8 PLL characteristics
- 5.3.9 Memory characteristics
- 5.3.10 EMC characteristics
- 5.3.11 Absolute maximum ratings (electrical sensitivity)
- 5.3.12 I/O port pin characteristics
- 5.3.13 NRST pin characteristics
Features
■ Core: ARM 32-bit Cortex™-M3 CPU – 72 MHz, 90 DMIPS with 1.25 DMIPS/MHz – Single-cycle multiplication and hardware division – Nested interrupt controller with 43 maskable interrupt channels – Interrupt processing (down to 6 CPU cycles) with tail chaining ■ Memories – 32-to-128 Kbytes of Flash memory – 6-to-20 Kbytes of SRAM ■ Clock, reset and supply management – 2.0 to 3.6 V application supply and I/Os – POR, PDR, and programmable voltage detector (PVD) – 4-to-16 MHz quartz oscillator – Internal 8 MHz factory-trimmed RC – Internal 32 kHz RC – PLL for CPU clock – Dedicated 32 kHz o scillator for RTC with calibration ■ Low power – Sleep, Stop and Standby modes –V BAT supply for RTC and backup registers ■ 2 x 12-bit, 1 µs A/D converters (16-channel) – Conversion range: 0 to 3.6 V – Dual-sample and hold capability – Synchronizable with advanced control timer – Temperature sensor ■ DMA – 7-channel DMA controller – Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs ■ Debug mode – Serial wire debug (SWD) & JTAG interfaces ■ Up to 80 fast I/O ports – 32/49/80 5 V-tolerant I/Os – All mappable on 16 external interrupt vectors – Atomic read/modify/write operations ■ Up to 7 timers – Up to three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter – 16-bit, 6-channel advanced control timer: up to 6 channels for PWM output Dead time generation and emergency stop – 2 x 16-bit watchdog timers (Independent and Window) – SysTick timer: a 24-bit downcounter ■ Up to 9 communication interfaces – Up to 2 x I 2C interfaces (SMBus/PMBus) – Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) – Up to 2 SPIs (18 Mbit/s) – CAN interface (2.0B Active) – USB 2.0 full speed interface Table 1. Device summary
Table 18. LSE oscillator characteristics (f Table 34. I
1 Introduction
This datasheet provides the STM32F103xx performance line ordering information and mechanical device characteristics. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming reference manual, pm0042, available from www.st.com. For information on the Cortex-M3 core please refer to the Cortex-M3 Technical Reference Manual.
2 Description
The STM32F103xx performance line family incorporates the high-performance ARM Cortex-M3 32-bit RISC core operating at a 72 MHz frequency, high-speed embedded memories (Flash memory up to 128Kbytes and SRAM up to 20 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer two 12-bit ADCs, three general purpose 16-bit timers plus one PWM timer, as well as standard and advanced communication interfaces: up to two I 2Cs and SPIs, three USARTs, an USB and a CAN. The STM32F103xx performance line family operates in the −40 to +105 °C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows to design low-power applications. The complete STM32F103xx performance line family includes devices in 4 different package types: from 48 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the STM32F103xx performance line microcontroller family suitable for a wide range of applications:
- Motor drive and application control
- Medical and handheld equipment
- PC peripherals gaming and GPS platforms
- Industrial applications: PLC, inverters, printers, and scanners
- Alarm systems, Video intercom, and HVAC Figure 1 shows the general block diagram of the device family.
2.1 Device overview
Table 2. Device features and peripheral counts (STM32F103xx performance line)
2.2 Overview
ARM® CortexTM-M3 core with embedded Flash and SRAM The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM Cortex-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The STM32F103xx performance line family having an embedded ARM core, is therefore compatible with all ARM tools and software. Figure 1 shows the general block diagram of the device family. Embedded Flash memory
- Up to 128 Kbytes of embedded Flash is available for storing programs and data. Embedded SRAM Up to 20 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. Nested vectored interrupt controller (NVIC) The STM32F103xx performance line embeds a Nested Vectored Interrupt Controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of Cortex- M3) and 16 priority levels.
- Closely coupled NVIC gives low latency interrupt processing
- Interrupt entry vector table address passed directly to the core
- Closely coupled NVIC core interface
- Allows early processing of interrupts
- Processing of late arriving higher priority interrupts
- Support for tail-chaining
- Processor state automatically saved
- Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detectors lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect external line with pulse width lower than the Internal APB2 clock period. Up to 80 GPIOs are connected to the 16 external interrupt lines.
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected and is monitored for failure. During such a scenario, it is disabled and software interrupt management follows. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator). Several prescalers allow the configuration of the AHB frequency, the High Speed APB (APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and the High Speed APB domains is 72 MHz. The maximum allowed frequency of the Low Speed APB domain is 36 MHz. Boot modes At startup, boot pins are used to select one of three boot options:
- Boot from User Flash
- Boot from System Memory
- Boot from SRAM The boot loader is located in System Memory. It is used to reprogram the Flash memory by using the USART. Power supply schemes
- VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins.
- VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs and PLL. In VDD range (ADC is limited at 2.4 V).
- VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Power supply supervisor The device has an integrated Power On Reset (POR)/Power Down Reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when V DD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 9: Embedded reset and power control block characteristics for the values of V POR/PDR and VPVD.
The regulator has three operation modes: main (MR), low power (LPR) and power down.
- MR is used in the nominal regulation mode (Run)
- LPR is used in the Stop modes.
- Power down is used in Standby Mode: the regulator output is in high impedance: the kernel circuitry is powered-down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. It is disabled in Standby Mode, providing high impedance output. Low-power modes The STM32F103xx performance line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:
- Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
- Stop mode Stop mode allows to achieve the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB wakeup.
- Standby mode The Standby mode allows to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI and the HSE RC oscillators are also switched off. After entering Standby mode, SRAM and registers content are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. DMA The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I 2C, USART, general purpose and advanced control timers TIMx and ADC.
RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers (ten 16-bit registers) can be used to store data when VDD power is not present. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by an external 32.768 kHz oscillator, the internal low power RC oscillator or the High Speed External clock divided by 128. The internal low power RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application time out management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. SysTick timer This timer is dedicated for OS, but could also be used as a standard down counter. It features:
- A 24-bit down counter
- Autoreload capability
- Maskable system interrupt generation when the counter reaches 0.
- Programmable clock source General purpose timers (TIMx) There are up to 3 synchronizable standard timers embedded in the STM32F103xx performance line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or one pulse mode output. This gives up to 12 input captures / output compares / PWMs on the largest packages. They can work together with the Advanced Control Timer via the Timer Link feature for synchronization or event chaining. The counter can be frozen in debug mode. Any of the standard timers can be used to generate PWM outputs. Each of the timers has independent DMA request generations.
Advanced control timer (TIM1) The advanced control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It can also be seen as a complete general-purpose timer. The 4 independent channels can be used for
- Input Capture
- Output Compare
- PWM generation (edge or center-aligned modes)
- One Pulse Mode output
- Complementary PWM outputs with programmable inserted dead-times. If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). The counter can be frozen in debug mode. Many features are shared with those of the standard TIM timers which have the same architecture. The advanced control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining. I²C bus Up to two I²C bus interfaces can operate in multi-master and slave modes. They can support standard and fast modes. They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded. They can be served by DMA and they support SM Bus 2.0/PM Bus. Universal synchronous/asynchronous receiver transmitter (USART) One of the USART interfaces is able to communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s. They provide hardware management of the CTS and RTS signals, IrDA SIR ENDEC support, are ISO 7816 compliant and have LIN Master/Slave capability. All USART interfaces can be served by the DMA controller. Serial peripheral interface (SPI) Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full- duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 8-bit to 16-bit. The hardware CRC generation/verification supports basic SD Card/MMC modes. Both SPIs can be served by the DMA controller. Controller area network (CAN) The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks.
Universal serial bus (USB) The STM32F103xx performance line embeds a USB device peripheral compatible with the USB Full-speed 12 Mbs. The USB interface implements a full speed (12 Mbit/s) function interface. It has software configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock source is generated from the internal main PLL. GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current- capable. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. I/Os on APB2 with up to 18 MHz toggling speed ADC (analog to digital converter) Two 12-bit Analog to Digital Converters are embedded into STM32F103xx performance line devices and each ADC shares up to 16 external channels, performing conversions in single- shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow:
- Simultaneous sample and hold
- Interleaved sample and hold
- Single shunt The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the standard timers (TIMx) and the Advanced Control timer (TIM1) can be internally connected to the ADC start trigger, injection trigger, and DMA trigger respectively, to allow the application to synchronize A/D conversion and timers. Temperature sensor The temperature sensor has to generate a linear voltage with any variation in temperature. The conversion range is between 2 V < V DDA < 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value. Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP .
Figure 1. STM32F103xx performance line block diagram
- T A = –40 °C to +105 °C (junction temperature up to 125 °C).
- AF = alternate function on I/O port pin.
4 Channels
8 Channels
3 Pin descriptions
Figure 2. STM32F103xx performance line LQFP100 pinout
Figure 5. STM32F103xx performance line BGA100 ballout
Table 3. Pin definitions
Table 3. Pin definitions (continued)
- I = input, O = output, S = supply, HiZ = high impedance.
- Function availability depends on the chosen device. Refer to Table 2 on page 7.
- PC13, PC14 and PC15 are supplied through the power switch, and so their use in ouptut mode is limited: they can be used
only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time.
- Available only on devices with a Flash me mory density equal or higher than 64 Kbytes.
- This alternate function can be remapped by software to some other port pins (if available on the used package). For more
UM0306, available from the STMicroelectronics website: www.st.com.
- For the LQFP48 and LQFP64 packages, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset,
however the functionality of PD0 and PD1 can be remapped by software on these pins.
4 Memory mapping
The memory map is shown in Figure 6. Figure 6. Memory map
1 Kbit0x4000 0000
1 Kbit
35 Kbits
2 Kbits
7 Kbits
3 Kbits
4 Kbits
STM32F103xx Electrical characteristics
5 Electrical characteristics
5.1 Test conditions
Unless otherwise specified, all voltages are referred to VSS.
5.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T A=25°C and TA=TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ).
5.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 2V ≤VDD ≤3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ).
5.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
5.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 7.
5.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 8.
5.1.6 Power supply scheme
Figure 9. Power supply scheme Figure 7. Pin loading condition s Figure 8. Pin input voltage
5.1.7 Current con sumption measurement
Figure 10. Current consumption measurement scheme
5.2 Absolute maximum ratings
periods may affect device reliability. Table 4. Voltage characteristics
- All 3.3 V power (V DD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external 3.3 V
- I INJ(PIN) must never be exceeded (see Table 5: Current characteristics). This is implicitly insured if VIN
Table 5. Current characteristics
- All 3.3 V power (V DD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external 3.3 V
- I INJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS.
- Negative injection disturbs the analog performance of the device. See note in Section 5.3.17: 12-bit ADC
- When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
5.3 Operating conditions
5.3.1 General operating conditions
5.3.2 Operating conditions at power-up / power-down
temperature condition summarized in Table 7. Table 8. Operating conditions at power-up / power-down Table 6. Thermal characteristics Table 7. General operating conditions
5.3.3 Embedded reset and power control block characteristics
temperature and VDD supply voltage conditions summarized in Table 7.
5.3.4 Embedded reference voltage
temperature and VDD supply voltage conditions summarized in Table 7. Table 9. Embedded reset and power control block characteristics Table 10. Embedded internal reference voltage
5.3.5 Supply current characteristics
- All I/O pins are in input mode with a static value at VDD or VSS (no load)
- All peripherals are disabled except if it is explicitly mentioned
- The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above) The parameters given in Table 11 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7.
Table 11. Maximum current consumption in Run and Sleep modes (1)
72 MHz 36 TBD TBD
48 MHz 30 TBD TBD
36 MHz 22 TBD TBD
24 MHz 21 TBD TBD
8 MHz 10 TBD TBD
72 MHz 32 45 47
48 MHz 22 31 33
36 MHz 13 18 20
24 MHz 11 15 17
72 MHz 22 35 37
48 MHz 14 23 25
36 MHz 13 22 24
24 MHz 10 17 19
- TBD stands for to be determined.
- Typical values are measured at T A = 25 °C, and VDD = 3.3 V
- Data based on characterization results, tested in production at V Dmax, fHCLK max. TAmax, and code executed from RAM.
Table 12. Maximum current consumption in Stop and Standby modes (1)
- TBD stands for to be determined.
- Typical values are measured at T A = 25 °C, VDD = 3.3 V, unless otherwise specified.
- Data based on characterization results, tested in production at V DD max, fHCLK max. and TA max (for other temperature.
- Values expected for next silicon revision.
- To have the Standby consumption with RTC ON, add I
VDD is present the Backup Domain is powered by VDD supply).
- All I/O pins are in input mode with a static value at VDD or VSS (no load).
- All peripherals are disabled except if it is explicitly mentioned.
- The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHZ and 2 wait states above).
- Ambient temperature and VDD supply voltage conditions summarized in Table 7.
Table 13. Typical current consumption in Run and Sleep modes (1)
- TBD stands for to be determined.
- Typical values are measures at T A = 25 °C, VDD = 3.3 V.
72 MHz 21
48 MHz 18
36 MHz TBD
24 MHz 13
16 MHz TBD
4 MHz 7
1 MHz 1
72 MHz 6
48 MHz TBD
24 MHz TBD
16 MHz 1
8 MHz TBD
4 MHz TBD
2 MHz TBD
1 MHz TBD
Table 14. Typical current consumption in Stop and Standby modes (1)
3.3 V 24
2.4 V TBD
3.3 V 14
2.4 V TBD (3)
3.3 V 2 (3)
2.4 V 1 (3)
- TBD stands for to be determined.
- Typical values are measures at T A = 25 °C, VDD = 3.3 V.
- Values expected for next silicon revision.
- To obtain Standby consumption with RTC ON, add I
5.3.6 External cloc k source characteristics
Table 15. High-speed external (HSE) user clock characteristics
- Value based on design simulation and/or technology characteristics. It is not tested in production.
Table 16. Low-speed external user clock characteristics
- Value based on design simulation and/or technology characteristics. It is not tested in production.
Figure 13. Typical application with a 8-MHz crystal
- R EXT value depends on the crystal characteristics. Typical value is in the range of 5 to 6RS.
Table 17. HSE 4-16 MHz oscillator characteristics (1)
- Resonator characte ristics given by the crystal/ceramic resonator manufacturer.
- For C L1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 25pF range (typ.),
- The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
recommended to take this point into account if the MCU is used in tough humidity conditions.
- t SU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
8 MHz
Figure 14. Typical application with a 32.768 kHz crystal Table 18. LSE oscillator characteristics (f LSE = 32.768 kHz)
- The oscillator selection can be optimized in terms of supply current using an high quality resonator with
- t SU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768
5.3.7 Internal clock source characteristics
temperature and VDD supply voltage conditions summarized in Table 7. Table 19. HSI oscillator characteristics (1)(2)
- V DD = 3.3 V, TA = −40 to 105 °C unless otherwise specified.
- TBD stands for to be determined.
- Values based on device characte rization, not tested in production.
Table 20. LSI oscillator characteristics (1)
- V DD = 3 V, TA = −40 to 105 °C unless otherwise specified.
- Value based on device characteri zation, not tested in production.
- Stop or Standby mode: the clock source is the RC oscillator
- Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7.
5.3.8 PLL characteristics
temperature and VDD supply voltage conditions summarized in Table 7. Table 21. Low-power mode wakeup timings (1)
- TBD stands for to be determined.
- The wakeup time from Sleep and Stop mode are measur ed from the wakeup event to the point in which the
user application code reads the first instruction.
- The wakeup time from Standby mode is measured from the wakeup event to the point in which the device
40 TBD µs
Table 22. PLL characteristics (1)
- TBD stands for to be determined.
- Data based on device characterization, not tested in production.
5.3.9 Memory characteristics
The characteristics are given at TA = −40 to 105 °C unless otherwise specified. Table 24. Flash memory endurance and data retention Table 23. Flash memory characteristics
- Values based on characterization and not tested in production.
- Values based on characterization not tested in production.
5.3.10 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
- Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 1000-4-2 standard.
- FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 1000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 25. They are based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as:
- Corrupted program counter
- Unexpected reset
- Critical Data corruption (control registers...)
Table 25. EMS characteristics (1)
- TBD stands for to be determined.
to prevent unrecoverable errors occurring (see application note AN1015). 1752/3 standard which specifies the test board and the pin loading. Table 26. EMI characteristics
130 MHz to 1GHz 23 29
5.3.11 Absolute maximum rati ngs (electrical sensitivity)
stressed in order to determine its performance in terms of electrical sensitivity. either 3 parts (cumulative mode) or 3 parts × (n + 1) supply pins (non-cumulative mode). For more details, refer to the application note AN1181.
- A supply overvoltage is applied to each power supply pin
- A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 27. ESD absolute maximum ratings (1)
- TBD stands for to be determined.
- Values based on characterization results, not tested in production.
Table 28. Electrical sensitivities
5.3.12 I/O port pin characteristics
pull-up or pull-down resistor (see Figure 15). Table 29. I/O static characteristics (1)
- V DD = 3.3 V, TA = −40 to 105 °C unless otherwise specified.
- Values based on characterization re sults, and not tested in production.
- Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
- With a minimum of 100 mV.
- Leakage could be higher than max. if negativ e current is injected on adjacent pins.
5 V tolerant I/Os 3
- Pull-up and pull-down resistors are designed with a true resistance in series with a switchable
PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order).
Figure 15. Unused I/O pin connection +20 mA (with a relaxed VOL).
- The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 5).
- The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 5). ai14147b 10 kΩ 10 kΩ UNUSED I/O PORT STM32F103xx VDD UNUSED I/O PORT STM32F103xx
Table 30. Output voltage characteristics
- The I IO current sunk by the device must always respect the absolute maximum rating specified in Table 5
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
- The I IO current sourced by the device must always respect the absolute maximum rating specified in
Table 5 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
Table 31. I/O AC characteristics (1)
- Refer to the Reference user manual UM0306 for a des cription of GPIO Port configuration register.
- The maximum frequency is defined in Figure 16.
- Values based on design simulation and va lidated on silicon, not tested in production.
Figure 16. I/O AC characteristics definition
5.3.13 NRST pin characteristics
resistor, RPU (see Table 29). Table 32. NRST pin characteristics (1)
- TBD stands for to be determined.
- The pull-up is designed with a true resistance in seri es with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
- Values guaranteed by design, not tested in production.
Figure 17. Recommended NRST pin protection
- The reset network protects t he device against parasitic resets.
- The user must ensure that the level on the NRST pin can go below the V IL(NRST) max level specified in
Table 32. Otherwise the reset will not be taken into account by the device.
5.3.14 TIM time r characteristics
function characteristics (output compare, input capture, external clock, PWM output). Table 33. TIMx (1) characteristics
- TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.
5.3.15 Communications interfaces
Table 34. I 2C characteristics
- Values based on standard I2C protocol requirement, not tested in production.
- f PCLK1 must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be
higher than 4 MHz to achieve the maximum fast mode I2C frequency.
- The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
- The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
Figure 18. I 2C bus AC waveforms and measurement circuit
- Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 35. SCL frequency (f PCLK1= 36 MHz.,VDD = 3.3 V)(1)(2)(3)
- R P = External pull-up resistance, fSCL = I2C speed,
- For speeds around 200 kHz, the tole rance on the achieved speed is of ±5%. For other speed ranges, the
components used to design the application.
400 TBD
300 TBD
200 TBD
100 TBD
50 TBD
20 TBD
alternate function characteristics (NSS, SCK, MOSI, MISO). Table 36. SPI characteristics (1)
- Values based on design simulation and/or charac terization results, and not tested in production.
- Depends on f PCLK. For example, if fPCLK= 8MHz, then tPCLK = 1/fPLCLK =125 ns and tv(MO) = 255 ns.
- Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
- Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
Figure 21. SPI timing diagram - master mode
- Measurement points are done at CMOS levels: 0.3V DD and 0.7VDD.
The USB interface is USB-IF certified (Full Speed). Table 37. USB DC electrical characteristics
- All the voltages are measured from the local ground potential.
- RL is the load connected on the USB drivers
Figure 22. USB timings: definition of data signal rise and fall time
5.3.16 CAN (controller area network) interface
acteristics (CANTX and CANRX). conditions summarized in Table 7. Note: It is recommended to perform a calibration after each power-up. Table 38. USB: Full speed electrical characteristics
- Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0). Table 39. ADC characteristics (1)
- Depending on the input signal variation (f AIN), CAIN can be increased for stabilization time and reduced to
allow the use of a larger serial resistor (RAIN). It is valid for all fADC frequencies ≤ 14 MHz.
- During the sample time the input capacitance C AIN (5 max) can be charged/discharged by the external
the conversion result. Values for the sample clock tS depend on programming. Table 40. ADC accuracy (f PCLK2 = 14 MHz, fADC = 14 MHz, RAIN <10 kΩ, VDDA =
3.3 V)(1)
- ADC Accuracy vs. Negative Injection Current: In jecting negative current on any of the standard (non-
standard analog pins which may potentially inject negative current. Table 39. ADC characteristics (1) (continued)
5.3.18 Temperature sen sor characteristics
Table 41. TS characteristics
6 Package characteristics
Figure 27. LFBGA100 - low profile fine pitch ball grid array package outline Table 42. LFBGA100 - low profile fine pitch ball grid array package mechanical data
Figure 28. Recommended PCB design rules (0.80/0.75 mm pitch BGA)
Figure 29. LQFP100 – 100-pin low-profile quad flat package outline Table 43. LQFP100 – 100-pin low-profile quad flat package mechanical data
Figure 30. LQFP64 – 64 pin low-profile quad flat package outline Table 44. LQFP64 – 64 pin low-profile quad flat package mechanical data
Figure 31. LQFP48 – 48 pin low-profile quad flat package outline Table 45. LQFP48 – 48 pin low-profile quad flat package mechanical data
- Values in inches are converted from mm and rounded to 3 decimal digits.
6.1 Thermal characteristics
- TA is the Ambient Temperature in ° C,
- ΘJA is the Package Junction-to-Ambient Thermal Resistance, in ° C/W,
- PD is the sum of PINT and PI/O (PD = PINT + PI/O),
- PINT is the product of IDD and VDD, expressed in Watts. This is the Chip Internal Power. PI/O represents the Power Dissipation on Input and Output Pins; Most of the time for the application PI/O< PINT and can be neglected. On the other hand, PI/O may be significant if the device is configured to drive continuously external modules and/or memories. An approximate relationship between PD and TJ (if PI/O is neglected) is given by: Therefore (solving equations 1 and 2): K = PD x (TA + 273°C) + ΘJA x PD 2 (3) where: K is a constant for the particular part, which may be determined from equation (3) by measuring P D (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations (1) and (2) iteratively for any value of TA.
Table 46. Thermal characteristics
7 Order codes
7.1 Future family enhancements
Table 47. Order codes
8 Revision history
Table 48. Document revision history 01-jun-2007 1 Initial release. performance line BGA100 ballout added. timing diagram. VBAT ranged modified in Power supply schemes. added to Table 32: NRST pin characteristics. Figure 17: Recommended NRST pin protection corrected. Notes removed below Table 7, Table 32, Table 37. Run and Sleep modes. Table 33: TIMx characteristics modified. tSTAB, VREF+ value, tlat and fTRIG added to Table 39: ADC characteristics. Figure 9: Power supply scheme modified. Features on page 1 list optimized. Small text changes.