02N60C3 VBSEMI | Alldatasheet

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  • Low Gate Charge Q g Results in Simple Dr ive Requirement  Improved Gate, Avalanche and Dynamic dV/dt Ruggedness  Fully Characterized Capacitance and Avalanche Voltage and Current  Compliant to RoHS directive 2002/95/EC Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting TJ = 25 °C, L = 24 mH, RG = 25 Ω, IAS = 3.2 A (see fig. 12). c. ISD ≤ 3.2 A, dI/dt ≤ 90 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. e. Drain current limited by maximum junction temperature. PRODUCT SUMMARY VDS (V) 650 RDS(on) (Ω)V GS = 10 V 2.1 Qg (Max.) (nC) 48 Qgs (nC) 12 Qgd (nC) 19 Configuration Single Available RoHS ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise note d PARAMETER SYMBOL LIMIT UNIT Drain-Source Volta ge VDS 650 V Gate-Source Voltage VGS ± 30 Continuous Drain Currente VGS at 10 V TC = 25 °C ID AContinuous Drain Current TC = 100 °C 4.2 Pulsed Drain Currenta IDM 18 Linear Derating Factor 0.48 W/°C Single Pulse Avalanche Energyb EAS 325 mJ Repetitive Avalanche Currenta IAR 4 A Repetitive Avalanche Energya EAR 6m J Maximum Power Dissipation TC = 25 °C PD 60 W Peak Diode Recovery dV/dtc dV/dt 2.8 V/ns Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150 °C Soldering Recommendations (Peak Temperature)d for 10 s 300 Mounting Torque 6-32 or M3 screw 10 lbf · in

1.1 N · m

S N-Channel MOSFET G D 4.5 D2PAK (TO-263) G D S N-Channel 650 V (D-S) MOSFET www.VBsemi.tw E-mail：China@VBsemi TEL:86-755-83251052 02N60C3 TO263 A ll data sheet.com

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). Pulse width ≤ 300 µs; duty cycle ≤ 2 %. c. C oss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS. d. t = 60 s, f = 60 Hz. THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. UNIT Maximum J unction-to-Ambient RthJA -6 5 °C/W Maximum Junction-to-Case (Drain) RthJC -2 .1 SPECIFICATIONS TJ = 25 °C, unless oth erwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 µA 650 - - V VDS Temperature Coefficient ΔVDS/TJ Reference to 25 °C, I D = 1 mAd - 670 - mV/°C Gate-Source Thresho ld Voltage VGS(th) VDS = VGS, ID = 250 µA 2.0 - 4.0 V Gate-So urce Leakage IGSS VGS = ± 30 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 650 V, VGS = 0 V - - 25 µA VDS = 520 V, VGS = 0 V, TJ = 125 °C - - 250 Drain-Source On-State Resistance RDS(on) V GS = 10 V ID = 3.1 Ab - - Ω Forward Transconductance gfs VDS = 50 V, ID = 3.1 A 3.9 - - S Dynamic Input Capacitance Ciss VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 - 1417 - pF Output Capacitance Coss - 177 - Reverse Transfer Capacitance Crss -7 . 0- Output Capacitance Coss VGS = 0 V VDS = 1.0 V, f = 1.0 MHz - 1912 - VDS = 520 V, f = 1.0 MHz - 48 - Effective Output Capacitance Coss eff. VDS = 0 V to 520 Vc -8 4- Total Gate Charge Qg VGS = 10 V ID = 3.2 A, VDS = 400 V see fig. 6 and 13b -- 4 8 nC Gate-Source Charge Qgs -- 1 2 Gate-Drain Charge Qgd -- 1 9 Turn-On De lay Time td(on) VDD = 325 V, ID = 3.2 A RG = 9.1 Ω, RD = 62 Ω, see fig. 10b -1 4 - ns Rise Time tr -2 0- Turn-O ff Delay Time td(off) -3 4- Fall Time tf -1 8- Drain-Source Body Diode Characteristics Continuo us Source-Drain Diode Current I S MOSFET symbol showin g the integral reverse p - n junction diode -- 4 A Pulsed Diode Forward Currenta ISM -- 2 1 Body Diode Voltage VSD TJ = 25 °C, IS = 3.2 A, VGS = 0 Vb -- 1 . 5 V Body Diode Reverse Recovery Ti me trr TJ = 25 °C, IF = 3.2 A, dI/dt = 100 A/µsb - 493 739 ns Body Diode Reverse Recovery Charge Qrr -2 . 1 3 . 2 µ C F orward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) S D G 2.1 www.VBsemi.tw E-mail：China@VBsemi TEL:86-755-83251052 02N60C3 TO263 A ll data sheet.com

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Fig. 1 - Typical Output Characteristics Fig . 2 - Typical Output Characteristics Fig. 3 - Typical Transfer Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature 0.1 0.1 1 10 100 20µs PULSE WIDTH T = 25 CJ ° TOP BOTTOM VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V V , Drain-to-Source Voltage (V) I , Drain-to-Source Current (A) DS D 4.5V 0.1 1 10 100 20µs PULSE WIDTH T = 150 CJ ° TOP BOTTOM VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V V , Drain-to-Source Voltage (V) I , Drain-to-Source Current (A) DS D 4.5V 0.1 V = 100V 20µs PULSE WIDT H DS V , Gate-to-Source Voltage (V) I , Drain-to-Source Current (A) GS D T = 25 CJ ° T = 150 CJ ° -60 -40 -20 0 20 40 60 80 100 120 140 160 0.0 0.5 2.0 3.5 5.0 5.5 8.0 T , Juncti on Temperature ( C) R , Drain-to-Source On Resistance (Normalized) J DS(on) V = I = GS D 10V 3.2A www.VBsemi.tw E-mail：China@VBsemi TEL:86-755-83251052 02N60C3 TO263 A ll data sheet.com

Fig. 5 - Typical Capacitance vs. Drain-to-Sou rce Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area 400 800 1200 1600 2000 1 10 100 1000 C, Capacita nce (pF) DSV , Drain-to-Source Voltage (V) A V = 0V, f = 1M Hz C = C + C , C SHORTED C = C C = C + C GS iss gs gd ds rss gd oss ds gd iss oss rss 0 10 20 30 40 50 Q , Total Gate Ch arge (nC) V , Gate-to-Source Voltage (V) G GS FOR TEST CIRCUIT SEE FIGURE I =D 3.2 A V = 130VDS V = 325VDS V = 520VDS 0.1 V ,Source-to-Drain Voltage (V) I , Reverse Drain Current (A) SD SD V = 0 V GS T = 25 CJ ° T = 150 CJ ° 0.1 10 100 1000 10000 OPERATION IN THIS A REA LIMITED BY RDS(on) Single P ulse T T = 150 C = 25 C° C V , Drain-to-Source Voltage (V) I , Drain Current (A)I , Drain Current (A) DS D 10us 100us 1ms 10ms www.VBsemi.tw E-mail：China@VBsemi TEL:86-755-83251052 02N60C3 TO263 A ll data sheet.com

Fig. 9 - Maximum Drain Current vs. Case Temp erature Fig. 10a - Switching Time Test Circuit Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms 25 50 75 100 125 150 0.0 1.0 2.0 3.0 4.0 5.0 6.0 T , Case Temp erature ( C) I , Drain Current (A) D VDS Pulse width ≤ 1 µs Duty factor ≤ 0.1 % RD VGS RG D.U.T. 10 V - VDD VDS 90 % 10 % VGS td(on) tr td(off) tf 0.01 0.1 Notes: 1. Duty factor D = t / t 2. Peak T =P x Z + T 1 2 J DM thJC C P t t DM t , Rectangular Puls e Duration (s) Thermal Response (Z ) thJC 0.01 0.02 0.05 0.10 0.20 D = 0.50 SINGLE PULSE (THERMAL RESPONSE) A R G IAS 0.01 Ωtp D.U.T. LVDS - VDD Driver A 15 V 20 V tp V DS IAS www.VBsemi.tw E-mail：China@VBsemi TEL:86-755-83251052 02N60C3 TO263 A ll data sheet.com

Fig. 12c - Maximum Avalanche Energy vs. Drain Current Fig. 12d - Typical Drain-to Source Voltage vs. Avalanche Current Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit 25 50 75 100 125 150 200 400 600 800 Starting T , Junction Temperature ( C) E , Single Pulse Avalanche Energy (mJ) J AS ID TOP BOTTOM 2.3A 3.3A 700 720 740 760 780 800 0123456 A DSav avI , Avalanche C urrent (A) V , Avalanche Voltage (V) QG QGS QGD VG Charge 10 V D.U.T. 3 mA VGS VDS IG ID 0.3 µF 0.2 µF 50 kΩ 12 V Current regulator Current sampling resistors Same type as D.U.T. www.VBsemi.tw E-mail：China@VBsemi TEL:86-755-83251052 02N60C3 TO263 A ll data sheet.com

Fig. 14 - For N-Channel P.W. Period dI/dt Diode recovery dV/dt Ripple ≤ 5 % Body diode forward drop Re-applied voltage Reverse recovery current Body diode forward current VGS = 10 V* VDD ISD Driver gate drive D.U.T. ISD waveform D.U.T. VDS waveform Inductor crurent D = P.W. Period * VGS = 5 V for logic level devices Peak Diode Recovery dV/dt Test Circuit RG VDD

  • dV/dt controlled by RG
  • Driver same type as D.U.T.
  • ISD controlled by duty factor "D"
  • D.U.T. - device under test D.U.T. Circuit layout considerations
  • Low stray inductance
  • Ground plane
  • Low leakage inductance current transformer www.VBsemi.tw E-mail：China@VBsemi TEL:86-755-83251052 02N60C3 TO263 A ll data sheet.com

TO-263AB (HIGH VOLTAGE) Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. 1 3 D B B E H BA Detail A A A c A 2 x e 2 x b2 2 x b

0.010 A BMM

± 0.004 BM Base metal Plating b1, b3 (b, b2) c1(c) Section B - B and C - C Scale: none Lead tip (Datum A)

2 C C

E B H Seating plane Gauge plane 0° to 8° Detail “A” Rotated 90° CW scale 8:1 L3 A1L4L MILLIMETERS INCHES MILLIMET ERS INCHES ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 www.VBsemi.tw E-mail：China@VBsemi TEL:86-755-83251052 02N60C3 TO263 A ll data sheet.com