STM32F102C8T6 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Introduction
- 2 Description
- 2.1 Device overview
- 2.2 Full compatibility throughout the family
- 2.3 Overview
- 3 Pinout and pin description
- 4 Memory mapping
- 5 Electrical characteristi cs
- 5.1 Parameter conditions
- 5.1.1 Minimum and maximum values
- 5.1.2 Typical values
- 5.1.3 Typical curves
- 5.1.4 Loading capacitor
- 5.1.5 Pin input voltage
- 5.1.6 Power supply scheme
- 5.1.7 Current consumption measurement
- 5.2 Absolute maximum ratings
- 5.3 Operating conditions
- 5.3.1 General operating conditions
- 5.3.2 Operating conditions at power-up / powe r-down
- 5.3.3 Embedded reset and power control bloc k characteristics
- 5.3.4 Embedded reference voltage
- 5.3.5 Supply current characteristics
- 5.3.6 External clock source characteristics
- 5.3.7 Internal clock source charac teristics
- 5.3.8 PLL characteristics
- 5.3.9 Memory characteristics
- 5.3.10 EMC characteristics
- 5.3.11 Absolute maximum ratings (electrical sensitivity)
- 5.3.12 I/O current injection characteristics
Features
- Core: ARM 32-bit Cortex™-M3 CPU – 48 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 WS memory access – Single-cycle multiplic ation and hardware division
- Memories – 64 or 128 Kbytes of Flash memory – 10 or 16 Kbytes of SRAM
- Clock, reset and supply management – 2.0 to 3.6 V application supply and I/Os – POR, PDR and programmable voltage detector (PVD) – 4-to-16 MHz cr ystal oscillator – Internal 8 MHz factory-trimmed RC – Internal 40 kHz RC – PLL for CPU clock – 32 kHz oscillator for RTC with calibration
- Low power – Sleep, Stop and Standby modes BAT supply for RTC and backup registers
- Debug mode – Serial wire debug (SWD) and JTAG interfaces
- DMA – 7-channel DMA controller – Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs
- 1 × 12-bit, 1.2 µs A/D converter (up to 16 channels) – Conversion range: 0 to 3.6 V – Temperature sensor
- Up to 51 fast I/O ports – 37/51 I/Os all mappable on 16 external interrupt vectors and almost all 5 V-tolerant
- Up to 6 timers – Three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter – 2 watchdog timers (Independent and Window) – SysTick timer: 24-bit downcounter
- Up to 8 communication interfaces – Up to 2 x I 2C interfaces (SMBus/PMBus) – Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) – Up to 2 SPIs (12 Mbit/s) – One USB 2.0 full speed interface
- CRC calculation unit, 96-bit unique ID
- ECOPACK® packages
Table 1. Device summary
STM32F102x8, STM32F102xB Contents
Table 2. STM32F102x8 and STM32F102xB medium-density USB access line Table 12. Maximum current consumption in Run mode, code with data processing Table 13. Maximum current consumption in Run mode, code with data processing Table 16. Typical current consumption in Run mode, code with data processing Table 22. LSE oscillator characteristics (f Table 39. I
STM32F102x8, STM32F102xB Introduction
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of STM32F102x8 and STM32F102xB medium-density USB access line microcontrollers. For more details on the whole STMicroelectronics STM32F102xx family, please refer to Section 2.2: Full compatibility throughout the family. The medium-density STM32F102xx datasheet should be read in conjunction with the low-, medium- and high-density STM32F10xxx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual, available from the www.arm.com website at the following address:
Description STM32F102x8, STM32F102xB
2 Description
The STM32F102xx medium-density USB access line incorporates the high-performance ARM Cortex™-M3 32-bit RISC core operat ing at a 48 MHz frequency, high-speed embedded memories (Flash memory of 64 or 128 Kbytes and SRAM of 10 or 16 Kbytes), and an extensive range of enhanced peripherals and I/Os connected to two APB buses. All devices offer standard communication interfaces (two I2Cs, two SPIs, one USB and three USARTs), one 12-bit ADC and three general-purpose 16-bit timers. The STM32F102xx family operates in the –40 to +85 °C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low- power applications. The STM32F102xx medium-density USB access line is delivered in the LQFP48 7 × 7 mm and LQFP64 10 × 10 mm packages. The STM32F102xx medium-density USB access line microcontrollers are suitable for a wide range of applications.
- Application control and user interface
- Medical and handheld equipment
- PC peripherals, gaming and GPS platforms
- Industrial applications: PLC, inverters, printers, and scanners
- Alarm systems, Video intercom, and HVAC Figure 1 shows the general block diagram of the device family.
2.1 Device overview
Figure 1. STM32F102T8 medium-density USB access line block diagram
- AF = alternate function on I/O port pin.
- T A = –40 °C to +85 °C (junction temperature up to 105 °C).
4 Channels
Figure 2. Clock tree
- For the USB function to be available, both HSE and PLL must be enabled, with the USB clock output
- To have an ADC conversion time of 1.2 µs, APB2 must be at 12 MHz, 24 MHz or 48 MHz.
- The Flash memory programming interface cl ock (FLITFCLK) is always the HSI clock.
8 MHz
48 MHz
48 MHz max
24 MHz max
2.2 Full compatibility throughout the family
to as medium-density devices. capacities, a timer and a few communication interfaces less. greater degree of freedom during the development cycle. access line and STM32F103xx performance line devices.
2.3 Overview
outstanding computational performance and an advanced system response to interrupts. associated with 8- and 16-bit devices. therefore compatible with all ARM tools and software. 64 or 128 Kbytes of embedded Flash is available for storing programs and data. Table 3. STM32F102xx USB access line family
16 KB Flash 32 KB Flash (1)
- For orderable part numbers that do not show the A internal code after the temperature range code (6), the
reference datasheet for electrical characteristics is that of the STM32F102x8/B medium-density devices.
64 KB Flash 128 KB Flash
4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM
STM32F102x8, STM32F102xB Description CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. Embedded SRAM 10 or 16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. Nested vectored interrupt controller (NVIC) The STM32F102xx medium-density USB access line embeds a nested vectored interrupt controller able to handle up to 36 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) an d 16 priority levels.
- Closely coupled NVIC gives low latency interrupt processing
- Interrupt entry vector table address passed directly to the core
- Closely coupled NVIC core interface
- Allows early processing of interrupts
- Processing of late arriving higher priority interrupts
- Support for tail-chaining
- Processor state automatically saved
- Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detectors lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect external line with pulse width lower than the Internal APB2 clock period. Up to 51 GPIOs are connected to the 16 external interrupt lines. Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). Several prescalers allow the configuration of the AHB frequency, the High Speed APB (APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 48 MHz. See Figure 2 for details on the clock tree.
Description STM32F102x8, STM32F102xB Boot modes At startup, boot pins are used to select one of five boot options:
- Boot from User Flash
- Boot from System Memory
- Boot from embedded SRAM The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. For further details please refer to AN2606. Power supply schemes
- VDD = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator. Provided externally through VDD pins.
- VSSA, VDDA = 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively.
- VBAT = 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. For more details on how to connect power pins, refer to Figure 8: Power supply scheme. Power supply supervisor The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when V DD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 11: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD. Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down.
- MR is used in the nominal regulation mode (Run)
- LPR is used in the Stop mode
- Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. It is disabled in Standby mode, providing high impedance output.
STM32F102x8, STM32F102xB Description Low-power modes The STM32F102xx medium-density USB access line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:
- Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
- Stop mode The Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or the RTC alarm.
- Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and registers content are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. DMA The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I 2C, USART, general purpose timers TIMx and ADC. RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on V DD supply when present or through the VBAT pin. The backup registers are ten 16-bit registers used to store 20 bytes of user application data when VDD power is not present. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare
Description STM32F102x8, STM32F102xB register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. SysTick timer This timer is dedicated for OS, but could also be used as a standard down counter. It features:
- A 24-bit down counter
- Autoreload capability
- Maskable system interrupt generation when the counter reaches 0.
- Programmable clock source General-purpose timers (TIMx) There are 3 synchronizable general-purpose timers embedded in the STM32F102xx medium-density USB access line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture, output compare, PWM or one-pulse mode output. This gives up to 12 input captures / output compares / PWMs on the LQFP48 and LQFP64 packages. The general-purpose timers can work together via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. I²C bus Two I²C bus interfaces can operate in multi-master and slave modes. They can support standard and fast modes. They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded. They can be served by DMA and they support SM Bus 2.0/PM Bus.
STM32F102x8, STM32F102xB Description Universal synchronous/asynchronous receiver transmitter (USART) The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816 compliant and have LIN Master/Slave capability. The USART interfaces can be served by the DMA controller. Serial peripheral interface (SPI) Two SPIs are able to communicate up to 12 Mbit/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. Both SPIs can be served by the DMA controller. Universal serial bus (USB) The STM32F102xx medium-density USB access line embeds an USB device peripheral compatible with the USB Full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current capable. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. ADC (analog to digital converter) The 12-bit analog to digital converter has up to 16 external channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. Temperature sensor The temperature sensor has to generate a a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value. Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Description STM32F102x8, STM32F102xB The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
3 Pinout and pin description
Figure 3. STM32F102xx medium-density USB access line LQFP48 pinout Figure 4. STM32F102xx medium-density USB access line LQFP64 pinout
Table 4. Medium-density STM32F102xx pin definitions
11 V BAT SV BAT
Table 4. Medium-density STM32F102xx pin definitions (continued)
- I = input, O = output, S = supply.
- Function availability depends on the chos en device. For devices having reduced peripheral counts, it is always the lower
called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 9Table 3 on page 12.
- If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
- PC13, PC14 and PC15 are supplied through the power switch. Si nce the switch only sinks a limited amount of current (3
of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
- Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
STMicroelectronics website: www.st.com.
STM32F102x8, STM32F102xB Pinout and pin description 7. The pins number 5 and 6 in the LQFP48 package are conf igured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode. 8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com.
Memory mapping STM32F102x8, STM32F102xB
4 Memory mapping
The memory map is shown in Figure 5.
Figure 5. Memory map
5 Electrical characteristics
5.1 Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
5.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T A = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3 σ).
5.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 2V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2σ).
5.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
5.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 6.
5.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 7.
5.1.6 Power supply scheme
Figure 8. Power supply scheme Caution: In Figure 8, the 4.7 µF capacitor must be connected to VDD3. Figure 6. Pin loading conditions Figure 7. Pin input voltage
5.1.7 Current consumption measurement
Figure 9. Current consumption measurement scheme
5.2 Absolute maximum ratings
periods may affect device reliability. Table 5. Voltage characteristics
- All main power (V DD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
- V IN maximum must always be respected. Refer to Table 6: Current characteristics for the maximum
allowed injected current values.
Table 6. Current characteristics
- All main power (V DD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
- Negative injection disturbs the analog performance of the device. See Note: on page 66.
- Positive injection is not possible on thes e I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 5 for maximum allowed input voltage values.
- A positive injection is induced by V IN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 5 for maximum allowed input voltage values.
- When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). Table 7. Thermal characteristics
5.3 Operating conditions
5.3.1 General operating conditions
Table 8. General operating conditions
- When the ADC is used, refer to Table 47: ADC characteristics.
- It is recommended to power V DD and VDDA from the same source. A maximum difference of 300 mV
between VDD and VDDA can be tolerated during power-up and operation.
- To sustain a voltage higher than V DD+0.3 V, the internal pull-up/pull-down resistors must be disabled.
- If T A is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal
characteristics on page 73).
- In low power dissipation state, T A can be extended to this range as long as TJ does not exceed TJmax
(see Table 6.2: Thermal characteristics on page 73).
5.3.2 Operating conditions at power-up / power-down
Subject to general operating conditions for TA. Table 9. Operating conditions at power-up / power-down
5.3.3 Embedded reset and power control block characteristics
temperature and VDD supply voltage conditions summarized in Table 8.
5.3.4 Embedded reference voltage
temperature and VDD supply voltage conditions summarized in Table 8. Table 10. Embedded reset and power control block characteristics
- The product behavior is guaranteed by design down to the minimum V POR/PDR value.
- Guaranteed by design, not tested in production.
5.3.5 Supply current characteristics
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
- All I/O pins are in input mode with a static value at VDD or VSS (no load)
- All peripherals are disabled except if it is explicitly mentioned
- The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz)
- Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling)
- When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK The parameters given in Table 13 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8.
Table 11. Embedded internal reference voltage
- Shortest sampling time can be determined in the application by multiple iterations.
- Guaranteed by design, not tested in production.
- Based on characterization results, not tested in production.
- External clock is 8 MHz and PLL is on when f HCLK > 8 MHz.
- Based on characterization, tested in production at V DD max, fHCLK max.
- External clock is 8 MHz and PLL is on when f HCLK > 8 MHz.
36 MHz 24
36 MHz 16
Figure 10. Typical current consumption in Run mode versus temperature (at 3.6 V) - Figure 11. Typical current consumption in Run mode versus temperature (at 3.6 V) -
36 MHz
16 MHz
Table 14. Maximum current consumption in Sleep mode, code running from Flash or RAM
48 MHz 20
48 MHz 6
36 MHz 5
16 MHz 4
8 MHz 3
- Based on characterization, tested in production at V DD max and fHCLK max with peripherals enabled.
- External clock is 8 MHz and PLL is on when f HCLK > 8 MHz.
Table 15. Typical and maximum current consumptions in Stop and Standby modes
- Typical values are measured at T A = 25 °C.
- All I/O pins are in input mode with a static value at VDD or VSS (no load)
- All peripherals are disabled except if it is explicitly mentioned
- The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz)
- Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling)
- When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4 The parameters given in Table 17 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8.
- Typical values are measures at T A = 25 °C, VDD = 3.3 V.
- Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
- External clock is 8 MHz and PLL is on when f HCLK > 8 MHz.
Table 17. Typical current consumption in Sleep mode, code running from Flash or
- Typical values are measures at T A = 25 °C, VDD = 3.3 V.
- Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
- External clock is 8 MHz and PLL is on when f HCLK > 8 MHz.
- all I/O pins are in input mode with a static value at VDD or VSS (no load)
- all peripherals are disabled unless otherwise mentioned
- the given value is calculated by measuring the current consumption – with all peripherals clocked off – with only one peripheral clocked on
- ambient operating temperature and V DD supply voltage conditions summarized in Table 5.
Table 18. Peripheral current consumption
- f HCLK = 48 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral.
- Specific conditions for ADC: f HCLK = 48 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fHCLK/4, ADON bit
in the ADC_CR2 register is set to 1.
5.3.6 External clock source characteristics
Table 19. High-speed external user clock characteristics
- Guaranteed by design, not tested in production.
Table 20. Low-speed external user clock characteristics
- Guaranteed by design, not tested in production.
characteristics (frequency, package, accuracy). microcontrollers” available from the ST website www.st.com. Table 21. HSE 4-16 MHz oscillator characteristics(1)(2)
- Resonator characteristics given by the crystal/ceramic resonator manufacturer.
- Based on characterization results, not tested in production.
- The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
recommended to take this point into account if the MCU is used in tough humidity conditions.
- t SU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
Figure 18. Typical application with an 8 MHz crystal
- R EXT value depends on the crystal characteristics.
characteristics (frequency, package, accuracy). Table 22. LSE oscillator characteristics (fLSE = 32.768 kHz)
- Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
- t SU(LSE) is the startup time measured from the moment it is enabled by software to a stabilized 32.768 kHz oscillation is
which is the series combination of CL1 and CL2. Figure 19. Typical application with a 32.768 kHz crystal
5.3.7 Internal clock source characteristics
temperature and VDD supply voltage conditions summarized in Table 8.
32.768 KHz
Table 23. HSI oscillator characteristics(1)
- V DD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
- Stop or Standby mode: the clock source is the RC oscillator
- Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8.
5.3.8 PLL characteristics
temperature and VDD supply voltage conditions summarized in Table 8.
- Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from the
- Guaranteed by design, not tested in production.
- Based on characterization, not tested in production.
- The actual frequency of HSI oscillator may be impacted by a reflow, but does not drift out of the specified
Table 24. LSI oscillator characteristics (1)
- V DD = 3 V, TA = −40 to 85 °C unless otherwise specified.
- Based on characterization, not tested in production.
- Guaranteed by design, not tested in production.
Table 25. Low-power mode wakeup timings
- The wakeup times are measured from the wakeup event to the point at which the user application code
reads the first instruction.
5.3.9 Memory characteristics
The characteristics are given at TA = –40 to 85 °C unless otherwise specified. Table 26. PLL characteristics
- Based on characterization, not tested in production.
- Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT. Table 27. Flash memory characteristics
- Guaranteed by design, not tested in production.
Table 28. Flash memory endurance and data retention
- Based on characterization not tested in production.
5.3.10 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization. While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
- Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
- FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 31. They are based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and pre qualification tests in relation with the EMC level requested for his application. Software recommendations: the software flowchart must include the management of runaway conditions such as:
- Corrupted program counter
- Unexpected reset
- Critical Data corruption (control registers, etc.) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Table 29. EMS characteristics
IEC 61967-2 standard which specifies the test board and the pin loading.
5.3.11 Absolute maximum ratings (electrical sensitivity)
stressed in order to determine its performance in terms of electrical sensitivity. conforms to the JESD22-A114/C101 standard.
- A supply overvoltage is applied to each power supply pin
- A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78 IC latch-up standard.
Table 30. EMI characteristics
0.1 MHz to 30 MHz 7
130 MHz to 1GHz 13
Table 31. ESD absolute maximum ratings
- Based on characterization results, not tested in production.
Table 32. Electrical sensitivities
5.3.12 I/O current in jection characteristics
sample basis during device characterization. the I/O pin, one at a time, the device is checked for functional failures. example reset, oscillator frequency deviation). The test results are given in Table 35.
5.3.13 I/O port characteristics
Table 33. I/O current injection susceptibility
Table 34. I/O static characteristics
- Data based on design simulation.
- FT = Five-volt tolerant. In order to sustain a voltage higher than V
- Hysteresis voltage between Schmitt trigger switching leve ls. Based on characterization, not tested in production.
- With a minimum of 100 mV.
- Leakage could be higher than max. if negativ e current is injected on adjacent pins.
- Pull-up and pull-down resistor s are designed with a true resistance in series with a switchable PMOS/NMOS. This
to the series resistance is minimum (~10% order).
Table 8. All I/Os are CMOS and TTL compliant. Table 35. Output voltage characteristics
- The I IO current sunk by the device must always respect the absolute maximum rating specified in Table 6
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
- TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
- The I IO current sourced by the device must always respect the absolute maximum rating specified in
Table 6 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
- Based on characterization data, not tested in production.
Table 36. I/O AC characteristics(1)
- The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a
description of GPIO Port configuration register.
- The maximum frequency is defined in Figure 24.
- Guaranteed by design, not tested in production.
Figure 24. I/O AC characteristics definition
5.3.14 NRST pin characteristics
resistor, RPU (see Table 36). Table 37. NRST pin characteristics
- Guaranteed by design, not tested in production.
- The pull-up is designed with a true resistance in seri es with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
Figure 25. Recommended NRST pin protection
- The reset network protects t he device against parasitic resets.
- The user must ensure that the level on the NRST pin can go below the V IL(NRST) max level specified in
Table 39. Otherwise the reset will not be taken into account by the device.
5.3.15 TIM time r characteristics
The parameters given in Table 40 are guaranteed by design. function characteristics (output compare, input capture, external clock, PWM output).
5.3.16 Communications interfaces
DD is disabled, but is still present. Table 38. TIMx(1) characteristics
- TIMx is used as a general term to re fer to the TIM2, TIM3 and TIM4 timers.
Table 39. I2C characteristics
- Values guaranteed by design, not tested in production.
- f PCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to
- The maximum Data hold time has only to be met if the interface does not stretch the low period of the SCL
Figure 26. I2C bus AC waveforms and measurement circuit(1)
- Measurement points are done at CMOS levels: 0.3V DD and 0.7VDD.
Table 40. SCL frequency (fPCLK1= 36 MHz, VDD_I2C = 3.3 V)(1)(2)
- R P = External pull-up resistance, fSCL = I2C speed,
- For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
components used to design the application.
function characteristics (NSS, SCK, MOSI, MISO). Table 41. SPI characteristics
- Based on characterization, not tested in production.
- Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
- Min time is for the minimum time to invalidate the ou tput and the max time is for the maximum time to put
Figure 29. SPI timing diagram - master mode(1)
- Measurement points are done at CMOS levels: 0.3V DD and 0.7VDD.
The USB interface is USB-IF certified (Full Speed). Table 42. USB startup time
Figure 30. USB timings: definition of data signal rise and fall time conditions summarized in Table 8. Note: It is recommended to perform a calibration after each power-up. Table 43. USB DC electrical characteristics
- All the voltages are measured from the local ground potential.
- To be compliant with the USB 2.0 full-speed electrical specification, the USB_DP (D+) pin should be pulled
up with a 1.5 kΩ resistor to a 3.0-to-3.6 V voltage range.
- The STM32F102xx USB functionality is ensured dow n to 2.7 V but not the full USB electrical
characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.
- Guaranteed by design, not tested in production.
- RL is the load connected on the USB drivers
Table 44. USB: Full speed electrical characteristics of the driver(1)
- Guaranteed by design, not tested in production.
- Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 45. ADC characteristics
- Guaranteed by design, not tested in production.
- VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA,
- For external triggers, a delay of 1/f PCLK2 must be added to the latency specified in Table 47.
Table 46. RAIN max for fADC = 12 MHz(1)
- Data guaranteed by design, not tested in production.
Table 47. ADC accuracy - limited test conditions(1)
- ADC DC accuracy values are measured after internal calibration.
- Based on characterization, not tested in production.
Table 48. ADC accuracy(1) (2) (3)
- ADC DC accuracy values are measured after internal calibration.
- Better performance could be achieved in restricted V DD, frequency and temperature ranges.
- ADC accuracy vs. negative injection current: Inject ing a negative current on any analog input pins should
- Based on characterization, not tested in production.
should be ceramic (good quality). They should be placed as close as possible to the chip. Figure 33. Power supply and reference decoupling
5.3.18 Temperature sensor characteristics
Table 49. TS characteristics
- Guaranteed by characterizati on, not tested in production.
- Data guaranteed by design, not tested in production.
- Shortest sampling time can be determined in the application by multiple iterations.
6 Package characteristics
6.1 Package mechanical data
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 34. LQFP64 – 10 x 10 mm, 48-pin low-profile quad flat package outline
- Dimensions are in millimeters.
Figure 35. LQFP64 recommended footprint dimensions(1)(2)
- Dimensions are in millimeters.
Table 50. LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data
- Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 36. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package outline
- Dimensions are in millimeters.
Figure 37. LQFP48 recommended footprint dimensions(1)(2)
- Dimensions are in millimeters.
Table 51. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data
- Values in inches are converted from mm and rounded to 4 decimal digits.
6.2 Thermal characteristics
Table 8: General operating conditions on page 30.
- TA max is the maximum ambient temperature in °C,
- Θ JA is the package junction-to-ambient thermal resistance, in °C/W,
- PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
- PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application.
6.3 Reference document
Convection (Still Air). Available from www.jedec.org. Table 52. Package thermal characteristics
6.3.1 Evaluating the maximum juncti on temperature for an application
information scheme shown in Table 55: Ordering information scheme. temperature range 6 is available (–40 to 85 °C). compatible with the STM32F102xx junction temperature range. This is within the junction temperature range of the STM32F102xx (–40 < TJ < 105 °C). Figure 38. LQFP64 PD max vs. TA
7 Ordering information scheme
Table 53. Ordering information scheme 6 = Industrial temperature range, –40 to 85 °C.
8 Revision history
Table 54. Document revision history 23-Sep-2008 1 Initial release. current consumption in Sleep mode, code running from Flash or RAM. Figure 13, Figure 14 and Figure 15 show typical curves. Figure 31: ADC accuracy characteristics modified. Figure 33: Power supply and reference decoupling modified. Low-speed external user clock characteristics modified. ACCHSI max values modified in Table 24: HSI oscillator characteristics. different VBAT values added. Low-power mode wakeup timings. Figure 25: Recommended NRST pin protection modified. IEC 61967-2 in Section 5.3.10: EMC characteristics on page 48. Jitter added to Table 27: PLL characteristics. Table 43: SPI characteristics modified. CADC and RAIN parameters modified in Table 47: ADC characteristics. RAIN max values modified in Table 48: RAIN max for fADC = 12 MHz.
Figure 2: Clock tree: added FLITFCLK and Note 3., and modified Note 1.. Updated Note 2. in Table 41: I2C characteristics. Updated Figure 25: Recommended NRST pin protection. waveforms and measurement circuit(1). compliance and added Figure 20, Figure 21, Figure 22, and Figure 23. Updated Section : Output driving current. Added DuCy(HSI) in Table 24: HSI oscillator characteristics. specified for various ambient temperature values. (dimensions in mm)(1)(2)(3). conditions for TTL and CMOS outputs and added Note 2.. purpose inputs/outputs) in Chapter 2.3: Overview. Added Note 2. in Table 5: Voltage characteristics. Updated Note 3., Note 4. and Note 5. in Table 6: Current characteristics. Updated Note 1. in Table 38: I/O AC characteristics. Added Chapter 5.3.12: I/O current injection characteristics. Updated Note 2. in Table 41: I2C characteristics. Removed Note 4 and updated Note 3. in Table 41: I2C characteristics. Table 54. Document revision history (continued)
I2C interface characteristics section.