02046-DSH-003-F

02046-DSH-003-F MA-COM | Alldatasheet

Document overview

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Technical content

Features

 Pin compatible with the MC2046-2  Operates with a 3.3V or 5V supply  2.8 mV typical input sensitivity at 1.25 Gbps  Programmable input-s ignal level detect  On-chip DC offset cancellation circuit  CMOS and PECL Signal Detect output variants  Output Jam Function  Low power (< 200 mW (M02046-15) at 3.3V including PECL load)

02046-DSH-003-F Mindspeed Technologies™ ii Mindspeed Proprietary and Confidential Typical Eye Diagram Pin Configuration

Ordering Information

Part Number Package Operating Temperature M02046-15* CMOS Status Output (CMOS LOS Output) in QSOP16 package –40 °C to 85 °C M02046-25* PECL Status Output (CMOS LOS Output) in QSOP16 package –40 °C to 85 °C M02046-15EVM Evaluation board with M02046-15 (CMOS Status Output) –40 °C to 85 °C M02046-25EVM Evaluation board with M02046-25 (PECL Status Output) –40 °C to 85 °C * The letter “G” designator after the part number indicates that the device is RoHS-compliant. Refer to www.mindspeed.com for additional information.

Revision History

F Final July 2005 -15 Correct Jam connection in bl ock diagram and typical applications figures. Correct IREF figure (reference current generation). E Final June 2005 -15 In the DC specifications, update R INDIFF and added note 4. In the ac specifi- cations update VLOS and DJ. Updated RST values and the typical LOS curve (Figure 4-2 - Figure 4-4). Added typical hysteresis curve (Figure 4-5). D Preliminary April 2005 -15 Corrected the ASIC revision number in this table. Update the Absolute Maximum specification for I(LOS) and I(STCMOS). Add the following DC specification: IOL_CMOS. C Preliminary March 2005 -15 Corrected the device part numbers in the ordering information. Update the following DC specifications: RINDIFF, VOH_CMOS, VOL_PECL and VIH. Update the following ac specifications: VIN(MIN), vn, VLOS, HYS, DJ, RJ, tr/tf, TLOS_ON, and TLOS_OFF. Update RST values for this revision of the part. Added typical applications circuit and eye. 10 mVPP differential input

1.25 Gbps

Note: x is either a 1 or 2 as explained in the order- ing information above

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1.0 Product Specification

1.1 Absolute Maximum Ratings

These are the absolute maximum ratings at or beyond which the IC can be expected to fail or be damaged. Reliable operation at these extremes for any length of time is not implied.

1.2 Recommended Operating Conditions

Table 1-1. Absolute Maximum Ratings Symbol Parameter Rating Units VCC Power supply voltage (VCC-GND) -0.5 to +5.75 V TSTG Storage temperature -65 to +150 °C PECLP, PECLN, STPECL PECL Output pins voltage V CC - 2 to VCC + 0.4 V I(PECLP), I(PECLN), I(STPECL) PECL Output pins maximum continuous current (delivered to load) 30 mA |DINP - DINN| Data input pins differential voltage 0.80 V DINP, DINN Data input pins voltage meeting |DINP - DINN| requirement GND to V CC3 + 0.4 V STSET Signal detect threshold setting pin voltage GND to V CC3 + 0.4 V JAM Output enable pin voltage GND to V CC + 0.4 V STCMOS, LOS CMOS Status Output pins voltage GND to V CC + 0.4 V IREF Current into Reference input +0 to -120 µA I(LOS), I(STCMOS) Current into CMOS Status Output pins +3000 to -100 µA Table 1-2. Recommended Operating Conditions Parameter Rating Units Power supply: (VCC-GND) (apply no potential to VCC3) or (VCC3-GND) (connect VCC to same potential as VCC3) +5V ± 7.5% or +3.3V ± 7.5% V Junction temperature -40 to +110 °C Operating ambient -40 to +85 °C

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1.3 DC Characteristics

VCC = +3.3V ± 7.5% or +5V ± 7.5%, TA = -40°C to +85°C, unless otherwise noted. Typical specifications are for VCC = 3.3V, TA = 25°C, unless otherwise noted. Table 1-3. DC Characteristics Symbol Parameter Conditions Min Typ Max Units ICC Supply Current PECL outputs un-loaded – 26 38 mA VOUTHpecl PECL Output High Voltage (1) (PECLP, PECLN) Single ended; 50Ω load to VCC - 2V VCC-1.025 V CC-0.952 V CC-0.88 V VOUTLpecl PECL Output Low Voltage (1) (PECLP, PECLN) Single ended; 50Ω load to VCC - 2V VCC-1.81 V CC-1.71 V CC-1.62 V RINDIFF Differential Input Resistance M easured between DINP and DINN 90 110 130 Ω VOH_CMOS CMOS ST (2), LOS (2, 3) Output High Voltage External 4.7-10 kΩ pull up to VCC 2.75 V CC –V VOL_CMOS CMOS ST (2), LOS (2, 3) Output Low Voltage External 4.7-10 kΩ pull up to VCC 0– 0 . 4 V IOL_CMOS CMOS ST (2), LOS (2, 3) Output Low Current (into device) VOL determined by external pull up to VCC –– 2 . 0 m A VOH_PECL PECL ST Output High Voltage (1, 3, 4) ST terminated 50Ω to VCC - 2V VCC-1.115 V CC-1.042 V CC-0.97 V VOL_PECL PECL ST Output Low Voltage (1, 3, 4) ST terminated 50Ω to VCC - 2V VCC-1.88 V CC-1.78 V CC-1.69 V VIH JAM Input High Voltage 2.7 – V CC V VIL JAM Input Low Voltage – – 0.8 V Notes: 1. Limits apply between 0°C to +85°C. Below 0°C the minimum decreases by up to 40 mV. 2. M02046-15 3. M02046-25 4. When ST is terminated with a 510Ω resistor to ground, the ST output voltages are approximately the same as for V OUTHpecl and VOUTLpecl

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1.4 AC Characteristics

VCC = +3.3V ± 7.5% or +5V ± 7.5%, TA = -40°C to +85°C, input bit rate = 2.5 Gbps 223-1 PRBS unless otherwise noted. Typical specifications are for VCC = 3.3V, TA = 25°C, unless otherwise noted. Table 1-4. AC Characteristics Symbol Parameter Conditions Min Typ Max Units VIN(MIN) Differential Input Sensitivity 1.25 Gbps, BER < 10 -12 –2 . 8 5m V VI(MAX) Input Overload BER < 10 -12, differential input 1.25 Gbps 1200 – – mV BER < 10-12, single-ended input, 1.25 Gbps 600 – – mV vn RMS Input Referred Noise – 200 – µVRMS VLOS LOS Programmable Range Differential inputs 5 – 55 mV HYS Signal Detect/LOS Hysteresis (electri cal); across LOS programmable range 2 3.5 5.5 dB BWLF Small-Signal –3dB Low Frequency Cutoff Excluding AC coupling capacitors – 25 – kHz DJ Deterministic Jitter (includes DCD) K28.5 pattern at 1.25 Gbps, 10 mVPP input – 18 70 ps RJ Random Jitter 10 mV PP input – 5 – ps RMS tr / tf Data Output Rise and Fall Times 20% to 80%; outputs terminated into 50Ω; 10 mVPP input – 150 230 ps TLOS_ON Time from LOS state until LOS output is asserted LOS assert time after 1 VPP input signal is turned off; signal detect level set to 10 mV 2.3 – 80 µs TLOS_OFF Time from non-LOS state until LOS is deasserted LOS deassert time after input crosses signal detect level; signal detect set to 10 mV with applied input signal of 20 mV PP 2.3 – 80 µs Figure 1-1. Data Input Requirements DINP DINN 2 - 600 mV 4 - 1200 mV Differential Input Single-ended Input DINP or DIN N 4 - 600 mVUnused Input

02046-DSH-003-F Mindspeed Technologies™ 4 Mindspeed Proprietary and Confidential NOTE: For single-ended input connections. When connecting to the used input with AC-coupling, the unused input should be AC-coupled through 50Ω to the supply voltage of the TIA; When connecting to the used input with DC-coupling, the unused input should be DC-coupled through 50Ω to a voltage equal to the common mode level of the used input. Figure 1-2. Typical A pplications Circuit NOTE: AC-coupled inputs shown. optional Limiting Amplifier Comparator DINN DINP Offset cancel Output Buffer Threshold Setting Circuit Regulator VCCSTSET VCC3 Biasing IREF Jam LOS AC-Coupled to TIA RST VTT Level Detect ST T I A Photodiode +3.3 V MON M02016 12.1 kΩ PECLN PECLP AC or DC Coupled (as described in Applications Information) Clock Data Recovery Unit

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2.0 Pin Definitions

Table 2-1. Pin Descriptions QSOP Pin# Name Function 1S T SET Loss of signal threshold setting input. Connect a 1% resistor between this pin and VCC3 (pin 2) to set loss of signal threshold. 2V CC3 Power supply input for 3.3V applications or the output of the internally regulated 3.3V voltage when VCC = 5V. Connect directly to supply for 3.3V applications (internal regulator not in use). Do not connect to power supply if VCC = 5V. 3 GND Ground. 4 DINP Non-inverting data input. Internally terminated with 50 Ω to V TT (see Figure 3-2). 5 DINN Inverting data input. Internally terminated with 50 Ω to VTT (see Figure 3-2). 6 NC No Connect. Leave Floating. CC3 Power supply input for 3.3V applications or the output of the internally regulated 3.3V voltage when VCC = 5V. Connect directly to supply for 3.3V applications (internal regulator not in use). Do not connect to power supply if VCC = 5V. 8 JAM Output disable. When high, data outputs are disabled (with non-inverting output held high and inverting output held low). Connect to LOS output to disable outputs with loss of signal. Outputs are enabled when JAM is low or floating. Internal 150 kΩ resistor to ground. 9 LOS Loss of signal output. Goes high when i nput signal falls below threshold set by STSET. This output is an open collector TTL with internal 80 kΩ pull-up resistor to VCC. Leave floating if not used. 10 ST Signal detect output. Goes high when input si gnal amplitude is above threshold set by STSET. In M02046-15, this output is an open collector TTL with internal 80 kΩ pull-up resistor to VCC; In M02046-25, this output is PECL. Leave floating if not used. 11 GND Ground. 12 PECLN Inverting data output (PECL). 13 PECLP Non-inverting data output (PECL). 14 V CC Power supply. Connect to either +5V or +3.3V. 15 NC No Connect. Leave Floating. 16 I REF Internal reference current for the LOS threshold. Must be connected to ground through a 12.1 k Ω 1% resistor.

02046-DSH-003-F Mindspeed Technologies™ 6 Mindspeed Proprietary and Confidential Figure 2-1. M02046-x5 Pinout M02046-x5 Date Code GND JAM DINP SETST VCC3 DINN NC VCC3 NC GND ST LOS PECLN PECLP VCC I REF Note: x is either a 1 or 2 as explained in the ordering information

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3.0 Functional Description

3.1 Overview

The M02046 is a highly integrated high-gain limiting amplifier that can be used with the same board layout and footprint as the MC2046-2. Featuring PECL outputs, the M02046 is intended for use in applications to 1.25 Gbps. Full output swing is achieved even at minimum input sensitivity. The M02046 can operate with a 3.3V or 5V supply. Included in the M02046 is a programmable signal-level detector, allowing the user to set thresholds at which the logic outputs are enabled. The signal detect function has typically 2 dB (optical) of hysteresis which prevents chatter at low input levels. A squelch function, which turns off the output when no signal is present, is provided by externally connecting the LOS Status output to the JAM input. The M02046-15 has a CMOS Status output and the M02046-25 has a PECL Status output. Both versions have a CMOS LOS output. Figure 3-1. Block Diagram Example Level Detect Limiting Amplifier Comparator DINN DINP PECLN PECLP Offset cancel Output Buffer Threshold Setting Circuit Regulator VCCSTSET VCC3 Biasing IREF Jam VTT ST LOS

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3.2 Features

 Pin compatible with the MC2046-2  Operates with a 3.3V or 5V supply  2.8 mV typical input sensitivity at 1.25 Gbps  Programmable input-signal level detect  On-chip DC offset cancellation circuit  CMOS and PECL Signal Detect output variants  Output Jam Function  Low power (< 200 mW (M02046-15) including PECL outputs)

3.3 General Description

The M02046 is a high-gain limiting amplifier for applications up to 1.25 Gbps, and incorporates a limiting amplifier, an input signal level detection circuit and also a fully integrated DC-offset cancellation loop that does not require any external components. The M02046 features a PECL high-speed data outputs. The M02046 provides the user with the flexibility to set the signal detect threshold and features either a CMOS status output (M02046-15) or a PECL status output (M02046-25). Optional output buffer disable (squelch/jam) can be implemented using the JAM input.

3.3.1 Inputs

The data inputs are internally connected to VTT via 50Ω resistors, and generally need to be AC coupled. Referring to Figure 3-2, the nominal VTT voltage is 2.85V because of the internal resistor divider to VCC3, which means this is the DC potential on the data inputs. See the applications information section for further details on choosing the AC- coupling capacitor. Figure 3-2. CML Data Inputs VCC3 50 Ω DINP VTT 50 Ω DINN 8.3 kΩ 1.3 kΩ VCC VCC

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3.3.2 DC Offset Compensation

The M02046 contain an internal DC autozero circuit that can remove the effect of DC offsets without using external components. This circuit is configured such that the feedback is effective only at frequencies well below the lowest frequency of interest. The low frequency cut off is typically 25 kHz.

3.3.3 Data Outputs

The M02046 features 100k/300k PECL compliant outputs as shown in Figure 3-3. The outputs may be terminated using any standard AC or DC-coupling PECL termination technique. AC-coupling is used in applications where the average DC content of the data is zero e.g. SONET. The advantage of this approach is lower power consumption, no susceptibility to DC drive and compatibility with non-PECL interfaces.

3.3.4 Signal Detect (ST) and Loss of Signal (LOS)

The M02046 features input signal level detection over an extended range. Using an external resistor, RST, between pin STSET and VCC3 (Figure 3-6) the user can program the input signal threshold. The signal detect status is indicated on the both the Signal Detect (ST) and LOS output pins. The Status output is either CMOS (M02046-15) or PECL (M02046-25). The PECL version is shown in Figure 3-4 while Figure 3-5 shows the ST output for the CMOS version of the device (and the LOS output for both versions of the device). The ST (LOS) signal is active (not asserted) when the signal is above the threshold value. The signal detection circuitry has the equivalent of 3.5 dB (typical) electrical hysteresis. Figure 3-3. PECL Data Outputs VCC VCC - 2V 50 Ω50 Ω PECLP PECLN

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3.3.5 JAM Function

When asserted, the active high power down (JAM) pin forces the outputs to a logic “one” state. This ensures that no data is propagated through the system. The loss of signal detection circuit can be used to automatically force the data outputs to a high state when the input signal falls below the threshold. The function is normally used to allow data to propagate only when the signal is above the user's bit-error-rate requirement. It therefore inhibits the data outputs toggling due to noise when there is no signal present (“squelch”). In order to implement this function, LOS should be connected to the JAM pin shown in Figure 3-7, thus forcing the data outputs to a logic “one” state when the signal falls below the threshold.

3.3.6 Voltage Regulation

The M02046 contain an on-chip voltage regulator to allow both 5V and 3.3V operation. When used at 5V, the on- chip regulator is enabled and the digital inputs and outputs are compatible with TTL 5V logic levels. Figure 3-6. STset Input Figure 3-7. JAM Input VCC3 STSET RST VSTSET VCC JAM VCC 55 kΩ 100 kΩ

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4.0 Applications Information

4.1 Applications

 1.06 Gbps Fibre Channel  1.25 Gbps Ethernet  1.25 Gbps SDH/SONET

4.1.1 Reference Current Generation

The M02046 contain an accurate on-chip bias circuit that requires an external 12.1 kΩ 1% resistor, RREF, from pin IREF to ground to set the LOS threshold voltage at STSET precisely. Figure 4-1. Reference Current Generation LOS VSET VLVL_Det BG_Ref VCC3 RST RREF STSET IREF

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4.1.2 Connecting V CC and VCC3

For 5V operation, the VCC pin is connected to an appropriate 5V ± 7.5% supply. No potential should be applied to the VCC3 pin. The only connection to VCC3 should be RST as shown in Figure 3-6. When VCC = 5V all logic outputs and the data outputs are 5V compatible. For low power operation, VCC and VCC3

4.1.3 Choosing an Inpu t AC-Coupling Capacitor

When AC-coupling the input the coupling capacitor should be of sufficient value to pass the lowest frequencies of interest, bearing in mind the number of consecutive identical bits, and the input resistance of the part. For SONET data, a good rule of thumb is to chose a coupling capacitor that has a cut-off frequency less than 1/(10,000) of the input data rate. For example, for 1.25 Gbps data, the coupling capacitor should be chosen as: fCUTOFF ≤ (1.25x109 / 10x103) = 125 kHz The -3 dB cutoff frequency of the low pass filter at the 50Ω input is found as: f3dB = 1/ (2 * π * 50Ω * CAC) so solving for C where f3dB = fCUTOFF CAC = 1/ (2 * π * 50Ω * fCUTOFF) EQ.1 and in this case the minimum capacitor is 25 nF. For Ethernet or Fibre Channel, there are less consecutive bits in the data, and the recommended cut-off frequency is 1/(1,000) of the input data rate. This results in a minimum capacitor of 2.5 nF for 1.25 Gbps Ethernet. Multirate applications down to 155 Mbps In this case, the input coupling capacitor needs to be large enough to pass 15 kHz (155x106/10,000) which results in a capacitor value of 0.2 µF. However, because this low pass frequency is close to the 25 kHz low pass frequency of the internal DC servo loop, it is preferable to use a larger input coupling capacitor such as 1 µF which provides an input cutoff frequency of 3.1 kHz. This separates the two poles sufficiently to allow them to be considered independent. This capacitor should also have a 20 nF capacitor in parallel to pass the higher frequency data (in the multirate application) without distortion. In all cases, a high quality coupling capacitor should be used as to pass the high frequency content of the input data stream.

4.1.4 Setting the Signal Detect Level

Using Figure 4-2, the value for RST is chosen to set the LOS threshold at the desired value. The resulting hysteresis is also shown in Figure 4-2. From Figure 4-2, it is apparent that small variations in RST cause significant variation in the LOS threshold level, particularly for low input signal levels. This is because of the logarithmic relationship between the internal level detect voltage and the input signal level. It is recommended that a 1% resistor be used for RST and that allowance is provided for LOS variation, particularly when the LOS threshold is near the sensitivity limit of the M02046. Example RST resistor values are given in Table 4-1.

02046-DSH-003-F Mindspeed Technologies™ 14 Mindspeed Proprietary and Confidential Table 4-1. Typical LOS Assert and De-assert Levels for Various 1% R ST Resistor Values RST (kΩ) VIN (mV pp) differential LOS Assert LOS De-Assert 7.50 4.9 7.8 6.81 11.7 17.0 6.19 23.2 33.4 5.49 55.0 77.3 Figure 4-2. Typical Loss of Signal Char acteristic (Full Input Signal Range) RST (kΩ) Threshold Level (mVPP) Optical Hysteresis De-assert Assert = 10*log10(De-assert/Assert)

1.25 Gbps, 2 31 - 1

Conditions: Vcc = 3.3V, Temp = 25C

02046-DSH-003-F Mindspeed Technologies™ 15 Mindspeed Proprietary and Confidential Figure 4-3. Typical Loss of Signal Char acteristic (Low Input Signal Range) Figure 4-4. Typical Loss of Signal Char acteristic (High Input Signal Range) RST (kΩ) Threshold Level (mVPP) De-assert Assert = 10*log10(De-assert/Assert) Conditions: Vcc = 3.3V, Temp = 25C Optical Hysteresis Threshold Level (mVPP) RST (kΩ) Optical Hysteresis = 10*log10(De-assert/Assert) Conditions: Vcc = 3.3V, Temp = 25C Assert De-assert

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4.1.5 PECLP and PECLN Termination

The data outputs of the M02046 are PECL compatible. For the high speed PECLP and PECLN outputs any standard AC or DC-coupling termination technique can be used. Figure 4-6 and Figure 4-7 illustrate typical AC and DC terminations. AC-coupling is used in applications where the average DC content of the data is zero e.g. SONET. The advantage of this approach is lower power consumption, no susceptibility to DC drift and compatibility with non-PECL interfaces. Figure 4-6 shows the circuit configuration and Table 4-2 lists the resistor values. If using transmission lines other than 50Ω, the shunt terminating resistance ZT should equal twice the impedance of the transmission line (ZO). DC-coupling can be used when driving PECL interfaces and has the advantage of a reduced component count. A Thevenin termination is used at the receive end to give a 50Ω load and the correct DC bias. Figure 4-7 shows the circuit configuration and Table 4-2 the resistor values. Alternatively, if available, terminating to VCC - 2V as shown in Figure 4-8 has the advantage that the resistance value is the same for 3.3V and 5V operation and it also has performance advantages at high data rates. In the M02046, ST is a PECL output. It is recommended that it be DC terminated in a PECL load, preferably as shown in Figure 4-8, but the decoupling capacitor on the load is not required as this is a DC output. Figure 4-5. Typical Loss of Signal Hysteresi s Characteristic (Full Input Signal Range) Table 4-2. PECL Termination Resistor Values Supply Output Impedance RPULL-DOWN ZT RTA / RTB RT / RB 5V 50 Ω 270 Ω 100 Ω 2.7 kΩ / 7.8 kΩ 82 Ω / 130 Ω 3.3V 50 Ω 150 Ω 100 Ω 2.7 kΩ / 4.3 kΩ 130 Ω / 82 Ω 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Electrical Hysteresis (dB) RST (kΩ) Conditions: Vcc = 3.3V, Temp = 25C = 20*log10(De-assert/Assert)Electrical Hysteresis

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4.1.6 ST PECL (M02046-25) Termination

The ST (in the PECL version of the part) output of the M02046 is PECL swing compatible. In most module applications, it is not common for this output to be terminated into a standard PECL load as shown in Figure 4-8 for the data outputs because ST is typically in a VOH state and this would consume ~20 mA of continuous supply current. In cases where an alternative termination can be used it is recommended that a single 510 Ω resistor be connected between the ST output and ground. When this termination is used, the VOH and VOL levels of the ST output typically meet the standard defined PECL levels and the swing is within PECL limits. This has the additional advantage of reducing the current consumption due to ST being high to <5 mA.

4.1.7 Using JAM

As shown in the typical applications circuit (Figure 1-2), the LOS output pin can optionally be connected to the Jam input pin. When LOS asserts the Jam function sets the data outputs to a fixed “one” state (PECLP is held high and PECLN is held low). This is normally used to allow data to propagate only when the signal is above the users' bit error rate (BER) requirement. It prevents the outputs from toggling due to noise when no signal is present. From the LOS assert and deassert figures above (Figure 4-2 - Figure 4-4), when an input signal is below the LOS assert threshold, LOS asserts (LOS high) causing Jam to assert. When Jam asserts, the data outputs and the internal servo loop of the M02046-x5 are disabled. If the input signal reaches or exceeds the LOS deassert threshold, LOS deasserts (LOS low) causing Jam to deassert, and hence enables the data outputs and the internal servo loop. If, however, the input signal is slowly increasing to a level that does not exceed the LOS deassert threshold (operating in the hysteresis region), the internal servo loop may not be fully established and this may cause partial enabling of the data outputs. To avoid this the input signal needs to fully reach or exceed the LOS deassert level to fully enable the data outputs.

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5.0 Package Specification

Figure 5-1. Package Information EE 1 Bottom View Seating Plane Stand-Off A1 Stand-Off Symbol Tols/N QSOP16 A MAX. 1.60 A1 ±.05 0.1 A2 ±.05 1.40 D ±.05 4.95 E ±.10 6.00 E1 ±.05 3.90 L ±.15 0.60 ccc MAX. 0.080 ddd MAX. 0.10 e BASIC 0.635 b ±.025 0.224 c ±.02 0.22 R ±.05 0.25 R1 Min. 0.20

02046-DSH-003-F Mindspeed Technologies™ 20 Mindspeed Proprietary and Confidential © 2005, Mindspeed TechnologiesTM, Inc. All rights reserved. Information in this document is provided in connection with Mindspeed TechnologiesTM ("MindspeedTM") products. These materials are provided by Mindspeed as a service to its customers and may be used for informational pur- poses only. Except as provided in Mindspeed’s Terms and Conditions of Sale for such products or in any separate agreement related to this document, Mindspeed assumes no liability whatsoever. Mindspeed assumes no respon- sibility for errors or omissions in these materials. Mindspeed may make changes to specifications and product descriptions at any time, without notice. Mindspeed makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its specifications and product descriptions. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF MINDSPEED PRODUCTS INCLUDING LIABILITY OR WAR- RANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAM- AGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. MINDSPEED FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. MINDSPEED SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS. Mindspeed products are not intended for use in medical, lifesaving or life sustaining applications. Mindspeed cus- tomers using or selling Mindspeed products for use in such applications do so at their own risk and agree to fully indemnify Mindspeed for any damages resulting from such improper use or sale.

02046-DSH-003-F Mindspeed Technologies™ 21 Mindspeed Proprietary and Confidential www.mindspeed.com General Information: (949) 579-3000 Headquarters - Newport Beach 4000 MacArthur Blvd., East Tower Newport Beach, CA. 92660