01CDU6

STMicroelectronics

Clock, reset and supply management 22-Jan-2015

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Technical content

Datasheet sections

1 Introduction
2 Description
2.1 Compatibility with STM32F4 series
3 Functional overview
3.1 ARM ® Cortex®-M4 with FPU core with embedded Flash and SRAM
3.2 Adaptive real-time memory accelerator (ART Accelerator™)
3.3 Memory protection unit
3.4 Embedded Flash memory
3.5 CRC (cyclic redundancy check) calculation unit
3.6 Embedded SRAM
3.7 Multi-AHB bus matrix
3.8 DMA controller (DMA)
3.9 Nested vectored interrupt controller (NVIC)
3.10 External interrupt/event controller (EXTI)
3.11 Clocks and startup
3.12 Boot modes
3.13 Power supply schemes
3.14 Power supply supervisor
3.14.1 Internal reset ON
3.14.2 Internal reset OFF
3.15 Voltage regulator
3.15.1 Regulator ON
3.15.2 Regulator OFF
3.16 Real-time clock (RTC) and backup registers
3.17 Low-power modes
3.18 V BAT operation
3.19 Timers and watchdogs
3.19.1 Advanced-control timers (TIM1)
3.19.2 General-purpose timers (TIMx)

Datasheet sections

6.3.6 Supply current characteristics
6.3.7 Wakeup time from low-power modes
6.3.8 External clock source characteristics
6.3.9 Internal clock source charac teristics
6.3.10 PLL characteristics
6.3.11 PLL spread spectrum clock generatio n (SSCG) characteristics
6.3.12 Memory characteristics
6.3.13 EMC characteristics
6.3.14 Absolute maximum ratings (electrical sensitivity)
6.3.15 I/O current injection characteristics
6.3.16 I/O port characteristics
6.3.17 NRST pin characteristics
6.3.18 TIM timer characteristics
6.3.19 Communications interfaces
6.3.21 Temperature sensor characteristics
6.3.23 Embedded reference voltage
6.3.24 SD/SDIO MMC card host interface (SDIO) characteristics
6.3.25 RTC characteristics
7 Package characteristics
7.1 Package mechanical data
7.1.3 LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package
7.1.4 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
7.2 Thermal characteristics
7.2.1 Reference document
8 Part numbering
9 Revision history

Features

Core: ARM® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 84 MHz, memory protection unit, 105 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
Memories – up to 512 Kbytes of Flash memory – up to 96 Kbytes of SRAM
Clock, reset and supply management – 1.7 V to 3.6 V applic ation supply and I/Os – POR, PDR, PVD and BOR – 4-to-26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration
Power consumption – Run: 146 µA/MHz (peripheral off) – Stop (Flash in Stop mode, fast wakeup time): 42 µA Typ @ 25C; 65 µA max @25 °C – Stop (Flash in Deep power down mode, fast wakeup time): down to 10 µA @ 25 °C; 30 µA max @25 °C – Standby: 2.4 µA @25 °C / 1.7 V without RTC; 12 µA @85 °C @1.7 V BAT supply for RTC: 1 µA @25 °C
1×12-bit, 2.4 MSPS A/D converter: up to 16 channels
General-purpose DMA: 16-stream DMA controllers with FIFOs and burst support
Up to 11 timers: up to six 16-bit, two 32-bit timers up to 84 MHz, each with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input, two watchdog timers (independent and window) and a SysTick timer
Debug mode – Serial wire debug (SWD) & JTAG interfaces –C o r t e x ®-M4 Embedded Trace Macrocell™
Up to 81 I/O ports with interrupt capability – Up to 78 fast I/Os up to 42 MHz – All I/O ports are 5 V-tolerant
Up to 12 communication interfaces – Up to 3 x I 2C interfaces (SMBus/PMBus) – Up to 3 USARTs (2 x 10.5 Mbit/s, 1 x 5.25 Mbit/s), ISO 7816 interface, LIN, IrDA, modem control) – Up to 4 SPIs (up to 42Mbit/s at fCPU = 84 MHz), SPI2 and SPI3 with muxed full-duplex I2S to achieve audio class accuracy via internal audio PLL or external clock – SDIO interface – Advanced connectivity: USB 2.0 full-speed device/host/OTG controller with on-chip PHY
CRC calculation unit
96-bit unique ID
RTC: subsecond accuracy, hardware calendar
All packages (WLCSP49, LQFP64/100, UFQFPN48, UFBGA100) are ECOPACK

Table 1. Device summary

STM32F401xD STM32F401xE Contents 3.21 Universal synchronous/asynchronous re ceiver transmitters (USART) . . 29

3.23 Inter-integrated sound (I

Table 20. Typical and maximum current consumption, code with data processing (ART Table 21. Typical and maximum current consumption, code with data processing (ART Table 22. Typical and maximum current consumption in run mode, code with data processing Table 23. Typical and maximum current consumption in run mode, code with data processing Table 24. Typical and maximum current consumption in run mode, code with data processing Table 25. Typical and maximum current consumption in run mode, code with data processing

Table 67. ADC accuracy at f Table 84. UFBGA100, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package

STM32F401xD STM32F401xE Introduction

1 Introduction

This datasheet provides the description of the STM32F401xD/xE line of microcontrollers. The STM32F401xD/xE datasheet should be read in conjunction with RM0368 reference manual which is available from the STMicroelectronics website www.st.com. It includes all information concerning Flash memory programming. For information on the Cortex-M4 core, please refer to the Cortex-M4 programming manual (PM0214) available from www.st.com.

Description STM32F401xD STM32F401xE

2 Description

The STM32F401XD/XE devices are based on the high-performance ARM® Cortex® -M4 32- bit RISC core operating at a frequency of up to 84 MHz. Its Cortex®-M4 core features a Floating point unit (FPU) single precision which supports all ARM single-precision data- processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The STM32F401xD/xE incorporate high-speed embedded memories (512 Kbytes of Flash memory, 96 Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. All devices offer one 12-bit ADC, a low-power RTC, six general-purpose 16-bit timers including one PWM timer for motor control, two general-purpose 32-bit timers. They also feature standard and advanced communication interfaces.

Up to three I 2Cs
Up to four SPIs
Two full duplex I2Ss. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization.
Three USARTs
SDIO interface
USB 2.0 OTG full speed interface Refer to for the peripherals available for each part number. The STM32F401xD/xE operate in the –40 to +105 °C temperature range from a 1.7 (PDR OFF) to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. These features make the STM32F401xD/xE microcontrollers suitable for a wide range of applications:
Motor drive and application control
Medical equipment
Industrial applications: PLC, inverters, circuit breakers
Printers, and scanners
Alarm systems, video intercom, and HVAC
Home audio appliances
Mobile phone sensor hub Figure 3 shows the general block diagram of the devices.

Table 2. STM32F401xD/xE features and peripheral counts

2.1 Compatibility with STM32F4 series

but some slight changes have to be done on the PCB board. Figure 1. Compatible board design for LQFP100 package

Figure 2. Compatible board design for LQFP64 package

Figure 3. STM32F401xD/xE block diagram

The timers connected to APB2 are clocked from TIMxCLK up to 84 MHz, while the timers connected to APB1 are clocked

STM32F401xD STM32F401xE Functional overview

3 Functional overview

3.1 ARM ® Cortex®-M4 with FPU core with embedded Flash and

The ARM® Cortex®-M4 with FPU processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The ARM ® Cortex®-M4 with FPU 32-bit RISC processor features exceptional code- efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. The STM32F401xD/xE devices are compatible with all ARM tools and software. Figure 3 shows the general block diagram of the STM32F401xD/xE. Note: Cortex ®-M4 with FPU is binary compatible with Cortex®-M3.

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry- standard ARM® Cortex®-M4 with FPU processors. It balances the inherent performance advantage of the ARM® Cortex®-M4 with FPU over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. To release the processor full 105 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 84 MHz.

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real- time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it.

Functional overview STM32F401xD STM32F401xE

3.4 Embedded Flash memory

The devices embed 512 Kbytes of Flash memory available for storing programs and data.

3.5 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location.

3.6 Embedded SRAM

All devices embed:

96 Kbytes of system SRAM which can be accessed (read/write) at CPU clock speed with 0 wait states

3.7 Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves (Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.

Figure 4. Multi-AHB matrix

3.8 DMA controller (DMA)

buffers without requiring any special code. source and destination are independent.

SPI and I
I2C
USART
General-purpose, basic and advanced-control timers TIMx
SD/SDIO/MMC host interface
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Functional overview STM32F401xD STM32F401xE

3.9 Nested vectored inter rupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 62 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M4 with FPU.

Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency.

3.10 External interrupt/ event controller (EXTI)

The external interrupt/event controller consists of 21 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 81 GPIOs can be connected to the 16 external interrupt lines.

3.11 Clocks and startup

On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 84 MHz. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the two AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB buses is 84 MHz while the maximum frequency of the high-speed APB domains is 84 MHz. The maximum allowed frequency of the low-speed APB domain is 42 MHz. The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class performance. In this case, the I 2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz.

STM32F401xD STM32F401xE Functional overview

3.12 Boot modes

At startup, boot pins are used to select one out of three boot options:

Boot from user Flash
Boot from system memory
Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using either USART1(PA9/10), USART2(PD5/6), USB OTG FS in device mode (PA11/12) through DFU (device firmware upgrade), I2C1(PB6/7), I2C2(PB10/3), I2C3(PA8/PB4), SPI1(PA4/5/6/7), SPI2(PB12/13/14/15) or SPI3(PA15, PC10/11/12). For more detailed information on the bootloader, refer to Application Note: AN2606, STM32™ microcontroller system memory boot mode .

3.13 Power supply schemes

VDD = 1.7 to 3.6 V: external power supply for I/Os with the internal supervisor (POR/PDR) disabled, provided externally through VDD pins. Requires the use of an external power supply supervisor connected to the VDD and PDR_ON pins.
VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins.
VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively, with decoupling technique.
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Refer to Figure 18: Power supply scheme for more details.

3.14 Power supply supervisor

3.14.1 Internal reset ON

This feature is available for VDD operating voltage range 1.8 V to 3.6 V. The internal power supply supervisor is enabled by holding PDR_ON high. VBOR, without the need for an external reset circuit. message and/or put the MCU into a safe state. The PVD is enabled by software.

3.14.2 Internal reset OFF

interconnection with internal reset OFF. Figure 5. Power supply supervisor interconnection with internal reset OFF(1)

The PRD_ON pin is only available in the WLCSP49 and UFBGA100 packages.

A comprehensive set of power-saving mode allows to design low-power applications.

The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
The brownout reset (BOR) circuitry must be disabled.
The embedded programmable voltage detector (PVD) is disabled.
V BAT functionality is no more available and VBAT pin should be connected to VDD.

3.15 Voltage regulator

Regulator ON – Main regulator mode (MR) – Low power regulator (LPR) – Power-down
Regulator OFF

3.15.1 Regulator ON

BYPASS_REG low. On all other packages, the regulator is always enabled. Figure 6. PDR_ON control with internal reset OFF

Functional overview STM32F401xD STM32F401xE There are three power modes configured by software when the regulator is ON:

MR is used in the nominal regulation mode (With different voltage scaling in Run) In Main regulator mode (MR mode), different voltage scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption.
LPR is used in the Stop modes The LP regulator mode is configured by software when entering Stop mode.
Power-down is used in Standby mode. The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost. Depending on the package, one or two external ceramic capacitors should be connected on the VCAP_1 and VCAP_2 pins. The VCAP_2 pin is only available for the LQFP100 and UFBGA100 packages. All packages have the regulator ON feature.

3.15.2 Regulator OFF

The Regulator OFF is available only on the UFBGA100, which features the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V12 voltage source through V CAP_1 and VCAP_2 pins. Since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency. Refer to Table 14: General operating conditions. The two 2.2 µF VCAP ceramic capacitors should be replaced by two 100 nF decoupling capacitors. Refer to Figure 18: Power supply scheme. When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. In regulator OFF mode, the following features are no more supported:

PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin.
As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required.

3.15.3 Regulator ON/OFF and internal power supply supervisor availability

3.16 Real-time clock (RTC ) and backup registers

The real-time clock (RTC)
20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary- coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC features a reference clock detection, a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is also available in binary format. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours. A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. The backup registers are 32-bit registers used to store 80 bytes of user application data when V DD power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 3.17: Low-power modes). Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date.

Table 3. Regulator ON/OFF and internal power supply supervisor availability

Refer to Section 3.14: Power supply supervisor

Functional overview STM32F401xD STM32F401xE The RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or from the VBAT pin.

3.17 Low-power modes

The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm/ wakeup/ tamper/ time stamp events).
Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, the SRAM and register contents are lost except for registers in the backup domain when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm/ wakeup/ tamper/time stamp event occurs. Standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 V domain is controlled by an external power.

3.18 V BAT operation

The VBAT pin allows to power the device VBAT domain from an external battery, an external super-capacitor, or from VDD when no external battery and an external super-capacitor are present. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC and the backup registers. Note: When the microcontroller is supplied from VBA T, external interrupts and RTC alarm/events do not exit it from VBAT operation. When PDR_ON pin is not connected to VDD (internal Reset OFF), the VBAT functionality is no more available and VBAT pin should be connected to VDD.

3.19 Timers and watchdogs

All timer counters can be frozen in debug mode. Table 4 compares the features of the advanced-control and general-purpose timers.

3.19.1 Advanced-control timers (TIM1)

Input capture
Output compare
PWM generation (edge- or center-aligned modes)
One-pulse mode output

Table 4. Timer feature comparison

Functional overview STM32F401xD STM32F401xE If configured as standard 16-bit timers, it has the same features as the general-purpose TIMx timers. If configured as a 16-bit PWM generator, it has full modulation capability (0- 100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. TIM1 supports independent DMA request generation.

3.19.2 General-purpose timers (TIMx)

There are seven synchronizable general-purpose timers embedded in the STM32F401xD/xE (see Table 4 for differences).

TIM2, TIM3, TIM4, TIM5 The STM32F401xD/xE devices are 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16- bit auto-reload up/downcounter and a 16-bit prescaler. They all feature four independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 15 input capture/output compare/PWMs. The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors.
TIM9, TIM10 and TIM11 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10 and TIM11 feature one independent channel, whereas TIM9 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases.

3.19.3 Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes.

3.19.4 Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

3.19.5 SysTick timer

A 24-bit downcounter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source.

3.20 Inter-integrated circuit interface (I2C)

generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. The devices also include programmable analog and digital noise filters (see Table 5).

3.21 Universal synchronous/asynch ronous receiver transmitters

(USART1, USART2 and USART6). interfaces can be served by the DMA controller. Table 5. Comparison of I2C analog and digital filters

Functional overview STM32F401xD STM32F401xE

3.22 Serial peripheral interface (SPI)

The devices feature up to four SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1 and SPI4 can communicate at up to 42 Mbit/s, SPI2 and SPI3 can communicate at up to 21 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode.

3.23 Inter-integr ated sound (I2S)

Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can be operated in master or slave mode, in full duplex and simplex communication modes and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I 2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx can be served by the DMA controller.

3.24 Audio PLL (PLLI2S)

The devices feature an additional dedicated PLL for audio I2S application. It allows to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance. The PLLI2S configuration can be modified to manage an I2S sample rate change without disabling the main PLL (PLL) used for the CPU. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 kHz to 192 kHz. In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S flow with an external PLL (or Codec output). Table 6. USART feature comparison (RTS/CTS) LIN SPI master irDA Smartcard (ISO 7816) Max. baud rate in Mbit/s (oversampling by 16) Max. baud rate in Mbit/s (oversampling by 8) APB mapping USART1 X X X X X X 5.25 10.5 APB2 (max.

84 MHz)

USART2 X X X X X X 2.62 5.25 APB1 (max.

42 MHz)

USART6 X N.A X X X X 5.25 10.5 APB2 (max.

STM32F401xD STM32F401xE Functional overview

3.25 Secure digital input/ output interface (SDIO)

An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1.

3.26 Universal serial bus on -the-go full-speed (OTG_FS)

The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are:

Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
4 bidirectional endpoints
8 host channels with periodic OUT support
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are connected

3.27 General-purpose in put/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. Fast I/O handling allowing maximum I/O toggling up to 84 MHz.

3.28 Analog-to-digita l converter (ADC)

One 12-bit analog-to-digital converter is embedded and shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs.

Functional overview STM32F401xD STM32F401xE The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4 or TIM5 timer.

3.29 Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value. Refer to the reference manual for additional information. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used.

3.30 Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP .

3.31 Embedded Trace Macrocell™

The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F401xD/xE through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using any high-speed channel available. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools.

4 Pinouts and pin description

Figure 10. STM32F401xD/xE WLCSP49 pinout

The above figure shows the package bump side.

Figure 11. STM32F401xD/xE UFQFPN48 pinout

The above figure shows the package top view.

Figure 12. STM32F401xD/xE LQFP64 pinout

The above figure shows the package top view.

Figure 13. STM32F401xD/xE LQFP100 pinout

The above figure shows the package top view.

Figure 14. STM32F401xD/xE UFBGA100 pinout

This figure shows the package top view

Table 7. Legend/abbreviations used in the pinout table Table 8. STM32F401xD/xE pin definitions

1 B7 1 6 E2 VBAT S - - - -

2 D5 2 7 C1 PC13 I/O FT (2) (3) EVENTOUT, RTC_TAMP1,

7 E7 7 14 H2 NRST I/O FT - EVENTOUT -

8 E6 12 20 - VSSA/VREF- S - - - -

10 F6 14 23 L2 PA0 I/O FT

11 G7 15 24 M2 PA1 I/O FT - USART2_RTS, TIM2_CH2,

12 E5 16 25 K3 PA2 I/O FT -

Table 8. STM32F401xD/xE pin definitions (continued)

13 E4 17 26 L3 PA3 I/O FT -

14 G6 20 29 M3 PA4 I/O FT -

15 F5 21 30 K4 PA5 I/O FT -

16 F4 22 31 L4 PA6 I/O FT - SPI1_MISO, TIM1_BKIN,

17 F3 23 32 M4 PA7 I/O FT - SPI1_MOSI, TIM1_CH1N,

18 G5 26 35 M5 PB0 I/O FT - TIM1_CH2N, TIM3_CH3,

19 G4 27 36 M6 PB1 I/O FT - TIM1_CH3N, TIM3_CH4,

20 G3 28 37 L6 PB2 I/O FT - EVENTOUT BOOT1

21 E3 29 47 L10 PB10 I/O FT -

22 G2 30 48 L11 VCAP1 S - - - -

23 D3 31 49 F12 VSS S - - - -

24 F2 32 50 G12 VDD S - - - -

25 E2 33 51 L12 PB12 I/O FT -

26 G1 34 52 K12 PB13 I/O FT - SPI2_SCK/I2S2_CK,

27 F1 35 53 K11 PB14 I/O FT - SPI2_MISO, I2S2ext_SD,

28 E1 36 54 K10 PB15 I/O FT - SPI2_MOSI/I2S2_SD,

29 D1 41 67 D11 PA8 I/O FT -

30 D2 42 68 D10 PA9 I/O FT - I2C3_SMBA, USART1_TX,

31 C2 43 69 C12 PA10 I/O FT - USART1_RX, TIM1_CH3,

32 C1 44 70 B12 PA11 I/O FT -

33 C3 45 71 A12 PA12 I/O FT -

34 B3 46 72 A11 PA13 (JTMS-

35 B1 47 74 F11 VSS S - - - -

37 A1 49 76 A10 PA14 (JTCK-

38 A2 50 77 A9 PA15 (JTDI) I/O FT -

39 A3 55 89 A8 PB3

40 A4 56 90 A7 PB4

41 B4 57 91 C5 PB5 I/O FT -

42 C4 58 92 B5 PB6 I/O FT - I2C1_SCL, USART1_TX,

43 D4 59 93 B4 PB7 I/O FT - I2C1_SDA, USART1_RX,

44 A5 60 94 A4 BOOT0 I B - - V

45 B5 61 95 A3 PB8 I/O FT -

46 C5 62 96 B3 PB9 I/O FT -

47 A6 63 99 - VSS S - - - -

48 A7 64 100 - VDD S - - - -

Function availability depends on the chosen device.
PC13, PC14 and PC15 are supplied through the power switch. Si nce the switch only sinks a limited amount of current (3

The speed should not exceed 2 MHz with a maximum load of 30 pF.
These I/Os must not be used as a current source (e.g. to drive an LED).

Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after

FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
If the device is delivered in an UFBGA100 and the BYPASS_REG pi n is set to VDD (Regulator off/internal reset ON mode),

Table 9. Alternate function mapping

Table 9. Alternate function mapping (continued)

5 Memory mapping

The memory map is shown in Figure 15. Figure 15. Memory map

Table 10. STM32F401xD register boundary addresses

Table 10. STM32F401xD register boundary addresses (continued)

6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

the selected temperature range). mean value plus or minus three times the standard deviation (mean ±3 σ).

6.1.2 Typical values

6.1.3 Typical curves

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 16. Figure 16. Pin loading conditions

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 17. Figure 17. Input voltage measurement

6.1.6 Power supply scheme

Figure 18. Power supply scheme

To connect PDR_ON pin, refer to Section 3.14: Power supply supervisor.
The 4.7 µF ceramic capacitor must be connected to one of the V DD pin.
V CAP_2 pad is only available on LQFP100 and UFBGA100 packages.

device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device.

6.1.7 Current consumption measurement

Figure 19. Current consumption measurement scheme

6.2 Absolute maximum ratings

extended periods may affect device reliability. Table 11. Voltage characteristics

All main power (V DD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power

supply, in the permitted range.

V IN maximum value must always be respected. Refer to Table 12 for the values of the maximum allowed

Table 12. Current characteristics

All main power (V DD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
This current consumption must be correc tly distributed over all I/Os and control pins. The total output current must not be

sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.

Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and

negative injected currents (instantaneous values). Table 13. Thermal characteristics

Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ®

directive 2011/65/EU, July 2011).

6.3 Operating conditions

6.3.1 General operating conditions

Table 14. General operating conditions

V DD/VDDA minimum value of 1.7 V with the use of an external power supply supervisor (refer to Section 3.14.2: Internal
When the ADC is used, refer to Table 66: ADC characteristics.
If V REF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.
It is recommended to power V DD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA

can be tolerated during power-up and power-down operation.

Guaranteed by test in production
To sustain a voltage higher than VDD+0.3, the inter nal Pull-up and Pull-Down resistors must be disabled
If T A is lower, higher PD values are allowed as long as TJ does not exceed TJmax.
In low power dissipation state, T A can be extended to this range as long as TJ does not exceed TJmax.

Table 14. General operating conditions (continued) Table 15. Features depending on the operating power supply range

2.1 V(4)

1.2 Msps

20 MHz(5) 84 MHz with 4

22 MHz 84 MHz with 3

2.4 Msps

24 MHz 84 MHz with 3

3.6 V(6)

30 MHz 84 MHz with 2

84 MHz

48 MHz

6.3.2 VCAP1/VCAP2 external capacitors

are replaced by a single capacitor. CEXT is specified in Table 16. Figure 20. External capacitor CEXT

Legend: ESR is the equivalent series resistance.
Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is
Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the
Refer to for frequencies vs. external load.
Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and power.
The voltage range for the USB full speed embedded PHY can drop down to 2.7 V. However the electrical characteristics of

D- and D+ pins will be degraded between 2.7 and 3 V. Table 16. VCAP1/VCAP2 operating conditions(1)

When bypassing the voltage regulator, the two 2.2 µF V CAP capacitors are not required and should be

replaced by two 100 nF decoupling capacitors.

6.3.3 Operating conditions at pow er-up/power-down (regulator ON)

Subject to general operating conditions for TA. Table 17. Operating conditions at power-up / power-down (regulator ON)

6.3.4 Operating conditi ons at power-up / power-down (regulator OFF)

Subject to general operating conditions for TA. Note: This feature is only available for UFBGA100 package. Table 18. Operating conditions at power-up / power-down (regulator OFF)(1)

To reset the internal logic at power-down, a reset must be applied on pin PA0 when V DD reach below

6.3.5 Embedded reset and power control block characteristics

temperature and VDD supply voltage @ 3.3V. Table 19. Embedded reset and power control block characteristics

6.3.6 Supply current characteristics

with a reduced code that gives a consumption equivalent to CoreMark code.

All I/O pins are in input mode with a static value at VDD or VSS (no load).
All peripherals are disabled except if it is explicitly mentioned.
The Flash memory access time is adjusted to both fHCLK frequency and VDD ranges (refer to Table 15: Features depending on the operating power supply range).
The voltage scaling is adjusted to fHCLK frequency as follows: – Scale 3 for f HCLK ≤ 60 MHz – Scale 2 for 60 MHz < f HCLK ≤ 84 MHz
The system clock is HCLK, fPCLK1 = fHCLK/2, and fPCLK2 = fHCLK.
External clock is 4 MHz and PLL is on
The maximum values are obtained for VDD = 3.6 V and a maximum ambient temperature (TA), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified. IRUSH (2) InRush current on voltage regulator power- on (POR or wakeup from Standby) - 160 200 mA E RUSH (2) InRush energy on voltage regulator power- on (POR or wakeup from Standby) V DD = 1.7 V, TA = 105 °C, IRUSH = 171 mA for 31 µs -- 5 . 4 µ C 1. The product behavior is guaranteed by design down to the minimum V POR/PDR value. 2. Guaranteed by design, not tested in production. 3. The reset timing is measured from the power-on (POR reset or wakeup from V BAT) to the instant when first instruction is fetched by the user application code.

Table 19. Embedded reset and power control block characteristics (continued)

Guaranteed by characterization, not tested in production unless otherwise specified
When analog peripheral blocks such as ADC, HSE, LSE, HS I, or LSI are ON, an additional power consumption has to be
When the ADC is ON (ADON bit set in the ADC_CR2 regist er), add an additional power consumption of 1.6 mA for the
Guaranteed by characterization, not tested in production unless otherwise specified
When analog peripheral blocks such as ADC, HSE, LSE, HS I, or LSI are ON, an additional power consumption has to be
When the ADC is ON (ADON bit set in the ADC_CR2 regist er), add an additional power consumption of 1.6 mA for the

Guaranteed by characterization, not tested in production unless otherwise specified.
Add an additional power consumption of 1. 6 mA per ADC for the analog part. In applications, this consumption occurs only