ZADCS147

ZADCS146_11 ETC2

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 26

Technical content

Rev. 2.0 / October 2011 ZADCS146/147 12-Bit, 200ksps, ADC Family

12-Bit, 200ksps, ADC Family © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. Brief Description The ZMDI ZADCS146 and ZADCS147 are 12-Bit low power analog-to-digital (A/D) converters with up to 250ksps conversion rate. The converter is based on successive-approximation-register architecture. All converters have an 8-channel input multiplexer and a high-bandwidth a track/hold circuit. All analog inputs are software configurable as eight / four/two single ended or four/two/one differential analog input channels as well as for unipolar or bipolar output coding. The ZADCS146 and ZADCS147 operate from a single +2.7V to +5.25V supply. The synchronous four wire serial interface connects directly to a microcontroller using one of the standards like SPI™, QSPI™, and Microwire™ without external components. The ZADCS146 and ZADCS147 use either the external serial-interface clock or an internally generated clock to perform successive- approximation analog-to-di gital conversions. The internal clock mode can be used to run synchronous conversions on several ZMDI ADCs in parallel. The ZADCS 146 is equipped with a high accurate internal 2.5V reference with an additional external ±1.5% voltage adjustment range. The device provides a hard-wired shut-down pin (nSHDN) and software-selectable power-down modes to automatically shut down the IC at the end of a conversion. Accessing the serial interface automatically powers up the ZADCS146 and ZADCS147. A quick turn-on time allows the device to be shut down between measurements.

Features

 12-Bit resolution SAR ADC  8 channel single or 4 channel diff. inputs  Software configurable uni- or bipolar output code  SPI™/QSPI™, Microwire™ compatible serial interface  No missing codes  Low power consumption  Internal 2.5V reference (only ZADCS146)  Software programmable power down mode  Single-Supply Operation +2.5V to +5.25V Benefits  Accurate measurements  Long battery life cycles due to low power consumption Available Support  ZADCS146 Kit - Evaluation Kit for ZADCS146 and ZADCS147 based on ZADCS146 device - Standalone and PC based operation modus - USB 2.0 (1.1) compatible - User Interface for PC operated modus - Graphical oscilloscope appl. and FFT analyzer Physical Characteristics  Current consumption @ 200 ksps, 3V supply  85°C  20-Pin SSOP package

12-Bit, 200ksps, ADC Family © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. Typical Applications  Embedded control & real time appl.  Industrial control & process control

applications

 Motion control applications  Three phase motor control  Power generation (Solar, Windmills, etc.)  Data Acquisition  Portable Data Logging  Battery-Powered Systems  Automotive ZADCS146 Block Diagram x 2.00 8-Channel Analog Input Multiplexer SAR DAC with inherent T&H IN - IN + Comparator Internal

3.2 MHz

+1.25V Reference Serial Interface and Control State Machine CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM REFADJ VREF nCS SCLK DIN DOUT SSTRB nSHDN VDD DGND AGND Available in ZADCS146

Ordering Information

[Bit] Channels [number] Sample Rate [ksps] Temperature range [°C] Internal Vref INL DNL Pins [number] Package [Type] Packing ZADCS146VIS20T 12 8 200 -25°C to +85°C  ± 1 LSB ± 1 LSB 20 SSOP Tube ZADCS147IS20T 12 8 200 -25°C to +85°C -- ± 1 LSB ± 1 LSB 20 SSOP Tube Sales and Further Information www.zmdi.com adc@zmdi.com Zentrum Mikroelektronik Dresden AG Grenzstrasse 28

01109 Dresden

ZMD America, Inc.

8413 Excelsior Drive

Madison, WI 53717 USA Zentrum Mikroelektronik Dresden AG, Japan Office 2nd Floor, Shinbashi Tokyu Bldg. 4-21-3, Shinbashi, Minato-ku Tokyo, 105-0004 Japan ZMD FAR EAST, Ltd. 3F, No. 51, Sec. 2, Keelung Road

11052 Taipei

Phone +49 (0)351.8822.7232 Fax +49 (0)351.8822.87232 Phone +1 (608) 829-1987 Fax +1 (631) 549-2882 Phone +81.3.6895.7410 Fax +81.3.6895.7301 Phone +886 2 2377 8189 Fax +886 2 2377 8199 DISCLAIMER: This information applies to a product under development. Its characteristics and specifications are PRELIMINARY and subject to change without notice. Zentrum Mikroelektronik Dresden AG (ZMD AG) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. The information furnished hereby is believed to be true and accurate. However, under no circumstances shall ZMD AG be liable to any customer, licensee, or any other third party for any special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical data. ZMD AG hereby expressly disclaims any liability of ZMD AG to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of ZMD AG for any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or otherwise.

12-Bit, 200ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 4 of 25

Contents

12-Bit, 200ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 6 of 25 List of Tables

12-Bit, 200ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 7 of 25

1 General Device Specification

1.1. Absolute Maximum Ratings (Non Operating) Symbol Parameter Min Max Unit Note VDD-GND VDD to AGND, DGND -0.3 6 V VAGND-DGND AGND to DGND -0.3 0.3 V CH0 – CH7, COM to AGND, DGND -0.3 VDD+0.3 V VREF, VREFADJ to AGND -0.3 VDD+0.3 V Digital Inputs to DGND -0.3 6 V Digital Outputs to DGND -0.3 VDD+0.3 V Digital Output Sink Current 25 mA Iin Input current into any pin except supply pins (Latch-Up) -100 100 mA VHBM Electrostatic discharge – Human Body Model (HBM) 2000 V 1 JCT Maximum Junction Temperature +150° °C OP Operating Temperature Range -25 +85 STG Storage temperature -65 +150 °C lead Lead Temperature 100%Sn JEDEC-J-STD-20C 260 °C H Humidity non-condensing 2 Ptot Total power dissipation 250 mW Thermal resistance of Package Rthj SSOP20 / 5.3mm 100 K/W Table 1: Absolute Maximum Ratings 1 HBM: C = 100pF charged to V HBM with resistor R = 1.5k in series, valid for all pins

2 Level 4 according to JEDEC-020A is guaranteed

12-Bit, 200ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 8 of 25 1.2. Package Pin Assignment ZADCS146 / ZADCS147 Package pin numb er Name Direction Type Description

1 CH0 IN Analog Analog Input Channel 0

2 CH1 IN Analog Analog Input Channel 1

3 CH2 IN Analog Analog Input Channel 2

4 CH3 IN Analog Analog Input Channel 3

5 CH4 IN Analog Analog Input Channel 4

6 CH5 IN Analog Analog Input Channel 5

7 CH6 IN Analog Analog Input Channel 6

8 CH7 IN Analog Analog Input Channel 7

9 COM IN Analog Ground reference for analog inputs in Single- Ended Mode

10 nSHDN IN Analog Active Low Shutdown

11 VREF I/O Analog Reference Buffer Output / External Reference Input

12 REFADJ I/O Analog Input to Reference Buffer Amplifier /

13 AGND SUPPLY Analog Ground

14 DGND SUPPLY Digital Ground

15 DOUT OUT CMOS Digital Serial Data Output

16 SSTRB OUT CMOS Digital Serial Strobe Output

17 DIN IN CMOS Digital Serial Data Input

18 nCS IN CMOS Digital Active Low Chip Select

19 SCLK IN CMOS Digital Serial Clock Input

20 VDD SUPPLY Positive Supply Voltage

Table 2: Pin list ZADCS146 / ZADCS147 Figure 1 Pac kage Pin Assignment for ZADCS146 & ZADCS147 CH0 VDD SCLKCH1 ZADCS 146 / ZADCS 147 nCSCH2 DINCH3 SSTRBCH4 DOUTCH5 DGNDCH6 AGNDCH7 REFADJ / n.c. for ZADCS147 COM VREFnSHDN

12-Bit, 200ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 9 of 25 1.3. Electrical Characteristics 1.3.1. General Parameters (VDD = +2.7V to + 5.25V; f SCLK = 3.2MHz (50% duty cycle); 16 clocks/conversion cycle (200 ksps); V REF = 2.500V applied to VREF pin; OP = OPmin … OPmax) Parameter Symbol Conditions Min Typ Max Unit DC Accuracy Resolution 12 Bits Relative Accuracy INL ZADCS146/ ZADCS147  1.0 LSB No Missing Codes NMC 12 Bits Differential Nonlinearity DNL ZADCS146/ ZADCS147  1.0 LSB Offset Error  0.5  3.0 LSB Gain Error  0.5  4.0 LSB Gain Temperature Coefficient  0.25 ppm/°C Dynamic Specifications (10kHz sine-wave input, 0V to 2.500Vpp, 200ksps, 3.2MHz external clock) Signal-to-Noise + Distortion Ratio SINAD 68 73 dB Total Harmonic Distortion THD Up to the 5th harmonic -88 -75 dB Spurious-Free Dynamic Range SFDR 74 80 dB Small-Signal Bandwidth -3dB roll off 3.8 MHz Conversion Rate Sampling Time (= Track/Hold Acquisition Time) tACQ Ext. Clock = 3.2MHz, 2.5 clocks/ acquisition 0.758 µs Ext. Clock = 3.2MHz, 12 clocks/ conversion 3.75 µs Conversion Time tCONV Int. Clock = 3.2MHz +/- 12% tolerance 3.30 4.20 µs Aperture Delay 30 ns Aperture Jitter < 50 ps External Clock Frequency 0.1 3.2 MHz Internal Clock Frequency 2.81 3.2 3.58 MHz Analog Inputs Unipolar, COM = 0V 0 to VREF Input Voltage Range, Single- Ended and Differential Bipolar, COM = VREF/2  VREF / 2 V Input Capacitance 16 pF

12-Bit, 200ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 10 of 25 1.3.2. Specific Parameters of ZADCS146 versions (VDD = +2.7V to + 5.25V; fSCLK = 3.2MHz (50% duty cycle); 16 clocks/conversion cycle (200 ksps); OP = OPmin … OPmax) Parameter Symbol Conditions Min Typ Max Unit Internal Reference at VREF VREF Output Voltage TA = + 25°C 2.480 2.500 2.520 V VREF Short-Circuit Current 30 mA VREF Temperature Coefficient ± 30 ± 50 ppm/°C Load Regulation 0 to 0.2mA output load 0.35 mV Capacitive Bypass at VREF 4.7 µF Capacitive Bypass at REFADJ 0.047 µF REFADJ Adjustment Range  1.5 % External Reference at VREF (internal buffer disabled by V(REFADJ) = VDD) VREF Input Voltage Range 1.0 VDD + 50mV V VREF Input Current VREF = 2.5V 180 215 µA VREF Input Resistance 11.5 14 k Shutdown VREF Input Current 0.1 µA REFADJ Buffer Disable Threshold VDD- 0.5 V External Reference at VREF_ADJ Reference Buffer Gain 2.00 VREF_ADJ Input Current ±80 µA Full Power Down VREFADJ Input Current Full Power-Down mode 0.1 µA Power Requirements Positive Supply Voltage VDD 2.7 5.25 V Operating Mode ext. VREF 0.85 1.0 mA Operating Mode int. VREF 1.3 1.4 mA Fast Power-Down 250 300 Positive Supply Current ZADCS146 ZADCS147 IDD VDD=3.6V Full Power-Down 0.5 4.0 µA Operating Mode ext. VREF 1.00 1.3 mA Operating Mode int. VREF 1.40 1.6 mA Fast Power-Down 250 300 Positive Supply Current ZADCS146 ZADCS147 IDD VDD=5.2V Full Power-Down 0.5 4.0 µA

12-Bit, 200ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 11 of 25 1.3.3. Specific Parameters of basic ZADCS147 versions (VDD = +2.7V to + 5.25V; fSCLK = 3.2MHz (50% duty cycle); 16 clocks/conversion cycle (200 ksps); OP = OPmin … OPma x) Parameter Symbol Conditions Min Typ Max Unit External Reference at VREF VREF Input Voltage Range 1.0 VDD + 50mV V VREF Input Current VREF = 2.5V 180 215 µA VREF Input Resistance 11.5 14 k Shutdown VREF Input Current 0.1 µA Capacitive Bypass at VREF 4.7 µF Power Requirements Positive Supply Voltage VDD 2.7 5.25 V Operating Mode 0.85 1.0 Positive Supply Current IDD VDD = 3.6V Full Power-Down 0.5 4.0 µA Operating Mode 1.00 1.3 Positive Supply Current IDD VDD = 5.25V Full Power-Down 0.5 4.0 µA 1.3.4. Digital Pin Parameters (VDD = +2.7V to + 5.25V; fSCLK = 3.2MHz (50% duty cycle); 16 clocks/conversion cycle (200 ksps); OP = OPmin … OPmax) Parameter Symbol Conditions Min Typ Max Unit Digital Inputs (DIN, SCLK, CS, nSHDN) VDD = 2.7V 1.9 V Logic High Level VIH VDD = 5.25V 3.3 V VDD = 2.7V 0.7 V Logic Low Level VIL VDD = 5.25V 1.4 V Hysteresis V Hyst 0.7 V Input Leakage IIN VIN = 0V or VDD ± 0.1 ± 1.0 µA Input Capacitance CIN 5 pF Digital Outptus (DOUT, SSTRB) VDD = 2.7V 3.5 8.5 mA Output High Current IOH V OH= VDD – 0.5V VDD = 5.25V 5.5 10.8 mA VDD = 2.7V 4 11.5 mA Output Low Voltage IOL V OL= 0.4V VDD = 5.25V 6.4 15.3 mA Three-State Leakage Current ILeak nCS = VDD ± 0.1 ± 1.0 µA Three-State Output Capacitance COUT nCS = VDD 5 pF

12-Bit, 200ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 12 of 25 1.4. Typical Operating Characteristics Integral Nonlinearity vs. Code -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 0 512 1024 1536 2048 2560 3072 3584 4096 Code INL (LSB) Differential Nonlinearity vs. Code -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 0 512 1024 1536 2048 2560 3072 3584 4096 Code DNL (LSB) IDD vs. VDD 150 300 450 600 750 900 1050 1200 1350 1500 2 . 73 . 44 . 14 . 8 VDD (V) IDD (µA) 5.5 IDDstatic vs. Temperature ZADCS146 with internal reference at VDD = 3.3V 500 550 600 650 700 - 4 0 - 2 0 0 2 04 06 08 0 1 0 0 Temperatur (°C) IDD (µA) Frequency Spectrum fIN = 1kHz, 4096 Point FFT -140 -120 -100 -80 -60 -40 -20 0 1 02 03 04 05 06 07 08 09 0 1 0 0 Frequency (kHz) Amplitude (dB) Frequency Spectrum fIN = 10kHz, 4096 Point FFT -140 -120 -100 -80 -60 -40 -20 0 1 02 03 04 05 06 07 08 09 0 1 0 0 Frequency (kHz) Amplitude (dB) IDDactive (converting) IDDstatic External V Internal V REF REF

12-Bit, 200ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 13 of 25 Offset Error vs. VDD -2.5 -1.5 -0.5 VDD (V) Offset Error (LSB) Offset Error vs. Temperatur -2.2 -2.1 -1.9 -1.8 -1.7 -1.6 -1.5 -50 -25 0 25 50 75 100 Temperature (°C) Offset Error (LSB) Δ Gain Error vs. VDD -0.45 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 VDD (V) Gain Error (LSB) Δ Gain Error vs. Temperatur -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 - 5 0 - 2 50 2 55 07 5 1 0 Temperature (°C) Gain Error (LSB)

12-Bit, 200ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 14 of 25

2 Detailed Description

2.1. General Operation The ZADCS 14x are classic successive approximation r egister (SAR) type converte rs. The architecture is based on a capacitive charge redistribution DAC merged with a resistor string DAC building a hybrid converter with excellent monotonicity and DNL properties. The Sample & Hold function is inherent to the capacitive DAC. Thi s avoids additional active components in t he signal path that could dist ort the input signal or introduce errors. Both devices ZADCS146 / ZADCS147 build on the same converter core and differ only in the availability of an internal reference voltage generator. ZADCS146 is equi pped with a highly accurate internal 1.25V bandgap reference which is available at the VREFADJ pin. The bandgap voltage is further amplified by an internal buffer amplifier to 2.50V that is available at pin VR EF. ZADCS147 comes without the internal reference and the internal buffer amplifier. It requires an exter nal reference supplied at VREF, with the benefit of considerably lower power consumption. A basic application schematic for ZADCS146 is shown in Figure 2, for ZADCS147 in Figure 3. ZADCS 146 can also be operated with an external reference, if VREFADJ is tied to VDD. Figure 2: Basic application schematic for ZADCS146 Figure 3: Basic application schematic for ZADCS147 A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 0 0 0 IN+ IN- 1 0 0 IN+ IN- 0 0 1 IN+ IN- 1 0 1 IN+ IN- 0 1 0 IN+ IN- 1 1 0 IN+ IN- 0 1 1 IN+ IN- 1 1 1 IN+ IN- Table 3: Channel selection in Single Ended Mode A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 0 0 0 IN+ IN- 0 0 1 IN+ IN- 0 1 0 IN+ IN- 0 1 1 IN+ IN- 1 0 0 IN- IN+ 1 0 1 IN- IN+ 1 1 0 IN- IN+ 1 1 1 IN- IN+ Table 4: Channel selection in Differential Mode Single-ended or differential analog inputs, 0V … +2.5V nCS 1 DIN 2 DGND 3 AGND 4 VREF 5 COM 6 CH0 7 CH1 8 CH4 9 CH5 10 SCLK 20 SSTRB 19 DOUT 18 nSHDN 17 VDD 16 VREFADJ 15 CH2 14 CH3 13 CH6 12 CH7 11 ZADCS146 47nF ≥ 4.7µF 0.1µF 10µF SCK I/O MOSI MISO µC +2.7V to 5.25V Single-ended or differential analog inputs, 0V … +V REF nCS 1 DIN 2 DGND 3 AGND 4 VREF 5 COM6 CH0 7 CH1 8 CH4 9 CH5 10 SCLK 20 SSTRB 19 DOUT 18 nSHDN 17 VDD 16 n.c. 15 CH2 14 CH3 13 CH6 12 CH7 11 ZADCS147 ≥ 4.7µF 0.1µF µC MI SO MOSI SCK I/O +2.7V to 5.25V 10µF

12-Bit, 200ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 20 of 25 Digital Timing In gen eral the clock frequency at SCLK may vary from 0.1MHz to 3.2MHz. Considering all telegram pauses or other interruptions of a continuous clock at SCLK, each conversion must be completed within 1.2ms from the falling clock edge of the eighth bit in the Control By te. Otherwise the signal that was captured during sample/hold may drop to noticeable affect the conversion result. Further detailed timing information on the digital interface is provided in Table 6 and Figure 13. Parameter Symbol Conditions Min Typ Max Unit SCLK Periode tSCLK 303.0 ns SCLK Pulse Width High tSCLKhigh 151.5 ns SCLK Pulse Width Low tSCLKlow 151.5 ns DIN to SCLK Setup tDinSetup 30 ns DIN to SCLK Hold tDinHold 10 ns nCS Fall to SCLK Setup tnCSSetup 30 ns SCLK Fall to DOUT & SSTRB Hold tOutHold C Load = 20pF 10 ns SCLK Fall to DOUT & SSTRB Valid t OutValid C Load = 20pF 40 ns nCS Rise to DOUT & SSTRB Disable t OutDisable C Load = 20pF 10 60 ns nCS Fall to DOUT & SSTRB Enable t OutEnable C Load = 20pF 60 ns nCS Pulse Width High tnCSHigh 100 ns Table 6: Timing Characterisitics (VDD = +2.7V to + 5.25V; OP = OPmin … OPmax) Figure 13 Detailed Timing Diagram nCS SCLK DIN SSTRB DOUT t tSCLKhigh SCL tSCLKlow tDINhold tDINsetup tnCSSetup tOutValid tOutEnable tOutEnable tOutDisable tOutHold tnCSHig

12-Bit, 200ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 21 of 25 Outpu t Code Format ZADCS146 and ZADCS147 do support unipolar and bipolar operation modes. The digital output code is straight binary in unipolar mode. It ranges from 0x00 for an input voltage difference of 0V to 0xFF for an input voltage difference of VREF (Full Scale = FS). The first code transition (0x00  0x01) occurs at a voltage equivalent to ½ LSB, the last (0xFE  0xFF) at VREF-1.5 LSB. See also Figure 14 for details. In bipolar mode a two’s complement coding is applied. Code transitions occur again halfway between successive integer LSB values. The transfer function is shown in Figure 15. Figure 14 : Unipolar Transfer Function Figure 15: Bipolar Transfer Function 2.5. Power Dissipation ZADCS1 46 and ZADCS147 offer three different ways to save operating current between conversions. Two different software controlled power down modes can be activated to automatically shut-down the device after completion of a conversion. They differ in the amount of circuitry that is powered down. Software Power Down Full Power Down Mode shuts down the entire analog part of the IC, reducing the static IDD of the device to less than 0.5µA if no external clock is provided at SCLK. Fast Power Down mode is only useful with ZADCS146 devices if the internal voltage reference is used. During Fast Power-Down the bandgap and the VREFADJ output buffer are kept alive while all other inte rnal analog circuitry is shut down. The benefit of Fast Power Down mode is a shorter turn on time of the reference compared to Full Power-Down Mode. This is basically due to the fact that the low pass which is formed at the VREFADJ output by the internal 20kΩ resistor and the external buffer capacitor of 47nF is not discharged in Fast Power-Down Mode. The settling time of the low pass at VREFADJ is about 9ms to re ach 12 bit accuracy. The Fast Power Down mode omits this settling and reduces the turn on time to about 200µs. To wake up the IC out of either software power down mode, it is sufficient to send a Start Bit while nCS is LOW. Since micro controllers can commonly transfer full bytes per transaction only, a dummy conversion is usually carried out to wake the device. In all application cases where an external reference voltage is supplied (ZADCS147 and ZADCS146 with VREFADJ tied to VDD) there is no turn on time to be considered. The first conversion is already valid. Fast Power-Down and Full Power-Down Mode do not show any difference in this configuration. 11 … 111 11 … 110 11 … 101 00 … 000 00 … 001 00 … 010 1 2 3 FS 0 Input Voltage (LSB) FS-3/2 LSB ZS = V(IN-) FS = VREF +V(IN- 1LSB = VREF 4096 (ZS) Output Code Output Code ZS = V(IN-) + FS = ½V +V(IN-) REF 01 … 111 01 … 110 10 … 000 10 … 001 00 … 000 +FS-FS Input Voltage (LSB) +FS-3/2 LSB 1LSB = VREF 4096 00 … 001 00 … 011 11 … 111 11 … 110 - FS = -½V +V(IN-) REF 11 … 101 ZS

12-Bit, 200ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 22 of 25 Hardware Power Down The third power down mode is called Hardware Power-Down. It is initiated by pulling the nSHDN pin LOW. If this condition is true, the device will immediately shut down all circuitry just as in Full Power Down-Mode. The IC wakes up if nSHDN is tied HIGH. There is no internal pull-up that would allow nSHDN to float during normal operation. This ensures the lowest possible power consumption in power down mode. General Power Considerations Even without activating any power down mode, the ZADCS146 and ZADCS147 reduce their power consumption between conversions automatically. The com parator, which contributes a considerable amount to the overall current consumption of the device, is shut off as soon as a conversion is ended. It gets turned on at the start of the next acquisition period. This expl ains the difference between the IDDstatic and IDDactive measurements shown in chapter 1.4 Typical Operating Characteristics. The avera ge current consumption of the device depe nds very much on the sampling frequency and the type of protocol used to communicate with the device. In order to achieve the lowest powe r consumption at low sampling frequencies, it is suggested to keep the conversion clock frequency at the maximum level of 3.2MHz and to power down the device between consecutive conversions. Figure 16 shows the characteristic current con sumption of the ZADCS147 with external reference supply versus Sampling Rate

12-Bit, 200ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 23 of 25

3 Layout

ptimum conversion performance care must be taken in design and layout of the application board. It is highly recommended to use printed circuit boar ds instead of wire wrap designs and to establish a single point star connection ground system towards AGND (see Figure 17). For optim al noise performance the star point should be lo cated very close to the AGND pin of the converter. The ground return to the power supply should be as short as possible and low impedance. All other analog ground points of external circuitry that is related to the A/D converter as well as the DGND pin of the device should be connected to this ground poin t too. Any other digital ground system should be kept apart as far as possible and connect on the power supply point only. Analog and digital signal domains should also be separ ated as well as possible and analog input signals should be shielded by AGND ground planes from electromagnetic interferences. Four-layer PCB boards that allow smaller vertical distances between the ground plane and the shielded signals do generally show a better performance than two-layer boards. The sampling phase is the most critical portion of the overall conversion timing for signal distortion. If possible, the switching of any high power devic es or nearby digital logic should be avoided during the sampling phase of the converter. Current consumption vs. Sample Rate External Clock Mode, External V REF, fSCLK = 3.3MHz 100 1000 10000 1 10 100 1000 Sample Rate (ksps) Average Supply Current (µA) Figure 16: Supply Current versus Sampling Rate Figure 17: Optimal Power-Supply Grounding System Optional R = 10Ω VDD1 (+2.7 … +5.25V) ZADCS146 ZA DCS147 Power Supplies COM DGND Other DGND GND Digital DVDDCircuitr y VDD2 The fully differential internal architecture of the ZADCS146 and ZADCS147 ensures very good suppression of power supply noise. Nevertheless, the SAR architecture is generally sensitive to glitches or sudden changes of the power supply that occur shortly before the la tching of the comparator output. It is therefore recommended to bypass the power supply connection very close to the device with capacitors of 0.1µF (ceramic) and >1µF (electrolytic). In case of a noisy su pply, an additional series resistor of 5 to 10 ohms can be used to low-pass filter the supply voltage. T he reference voltage should always be bypassed with capacitors of 0.1µF (ceramic) and ≥ 4.7µF (electrolytic) as close as possible to the VREF pin. If V REF is provided by an external source, any series resistance in the V REF supply path can cause a gain error of the converter. During conversion, a DC current of about 100µA is drawn th rough the VREF pin that could cause a noticeable voltage drop across the resistance.

12-Bit, 200ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 24 of 25

4 Package Drawing

46 and ZADCS147 devices are delivered in a 20-pin SSOP-package that has the dimensions as shown in Figure 18 and Table 7. Figure 18: Package Outline Dimensions Symbol A A 1 A 2 b P c D E enom H E L P Z k  0.65 7.65 0.63 0.25 0° Table 7: Package Dimensions for ZADC146/ZADCS147 devices (mm)

12-Bit, 200ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 25 of 25 Sales and Further Information www.zmdi.com adc@zmdi.com Zentrum Mikroelektronik Dresden AG Grenzstrasse 28 ZMD America, Inc. Madison, WI 53717 USA Zentrum Mikroelektronik Dresden AG, Japan Office 2nd Floor, Shinbashi Tokyu Bldg. 4-21-3, Shinbashi, Minato-ku Tokyo, 105-0004 Japan ZMD FAR EAST, Ltd. 3F, No. 51, Sec. 2, Keelung Road Phone +49 (0)351.8822.7232 Fax +49 (0)351.8822.87232 Phone +1 (608) 829-1987 Fax +1 (631) 549-2882 Phone +81.3.6895.7410 Fax +81.3.6895.7301 Phone +886 2 2377 8189 Fax +886 2 2377 8199 DISCLAIMER: This information applies to a product under development. Its characteristics and specifications are PRELIMINARY and subject to change without notice. Zentrum Mikroelektronik Dresden AG (ZMD AG) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. The information furnished hereby is believed to be true and accurate. However, under no circumstances shall ZMD AG be liable to any customer, licensee, or any other third party for any special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical data. ZMD AG hereby expressly disclaims any liability of ZMD AG to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of ZMD AG for any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or otherwise.

Click to View Pricing, Inventory, Delivery & Lifecycle Information: ZMDI: ZADCS146VIS20T ZADCS147IS20T