ZADCS1042

ZADCS1082_11 ETC2

Document overview

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Technical content

Rev. 2.0 / October 2011 ZADCS1082/1042/1022 10-Bit, 250ksps, ADC Family

10-Bit, 250ksps, ADC Family © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. ns possible due to downward compatibility within the family power t  ZADCS1282 Kit or ZMDI ZADCS10x2 Family S1282 device 5.25V ax. ply Brief Description The ZMDI ZADCS1082/ZADCS1042/ZADCS1022 are 10-Bit low power analog-to-digital (A/D) converters with up to 250ksps conversion rate. The converter is based on successive- approximation-register architecture. All converters have an 8-channel input multiplexer and a high-bandwidth a track/hold circuit. All analog inputs are software configurable as eight / four/two single ended or four/two/one differential analog input channels as well as for unipolar or bipolar output coding. The ZADCS1082/ ZADCS1042/ ZADCS1022 operate from a single +2.7V to +5.25V supply. The synchronous four wire serial interface connects directly to a microcontroller using one of the standards like SPI™, QSPI™, and Microwire™ without external components. The ZADCS1082/ZADCS1042/ZADCS1022 use either the external serial-interface clock or an internally generated clock to perform successive- approximation analog-to-di gital conversions. The internal clock mode can be used to run synchronous conversions on several ZMDI ADCs in parallel. The “V” versions ZADCS1082V/ZADCS1042V/ ZADCS1022V are equipped with a high accurate internal 2.5V reference with an additional external ±1.5% voltage adjustment range. The device provides a hard-wired shut-down pin (nSHDN) and software-selectable power-down modes to automatically shut down the IC at the end of a conversion. Accessing the serial interface automatically power s up the ZADCS1082/ ZADCS1042/ZADCS1022. A quick turn-on time allows the device to be shut down between measurements.

Features

 10-Bit resolution SAR ADC  2/4/8 channel single or 1/2/4 channel diff. inputs  Software configurable uni- or bipolar output code  SPI™/QSPI™, Microwire™ compatible serial interface  No missing codes  Low power consumption  Internal 2.5V reference (only “V” version - ZADCS1082V/ ZADCS1042V/ZADCS1022V)  Software programmable power down mode  Single-Supply Operation +2.5V to +5.25V Benefits  Scalable system solutio upward/ ( 8, 10, 12 bit resolution, 2, 4, 8 channels)  Accurate measurements  Long battery life cycles due to low consumption  Synchronous sampling with several ZADCS parts in parallel Available Suppor Evaluation Kit f based on ZADC - Standalone and PC based operation modus - USB 2.0 (1.1) compatible - User Interface for PC operated modus l. and FFT analyzer - Graphical oscilloscope app Physical Characteristics  Current consumption @ 200 ksps, 3V sup 14 / 16 / 20-Pin SSOP package

10-Bit, 250ksps, ADC Family © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. Typical Applications  Embedded control & real time appl.  Industrial control & process control

applications

 Motion control applications  Three phase motor control  Power generation (Solar, Windmills, etc.)  Data Acquisition  Portable Data Logging  Battery-Powered Systems  Automotive ZADCS1082 Block Diagram x 2.00 8-Channel Analog Input Multiplexer SAR DAC with inherent T&H IN - IN + Comparator Internal

3.2 MHz

+1.25V Reference Serial Interface and Control State Machine CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM REFADJ VREF nCS SCLK DIN DOUT SSTRB nSHDN VDD DGND AGND Available in ZADCS1082V / ZADCS1042V / ZADCS1022V

Ordering Information

[Bit] Channels [number] Sample Rate [ksps] Temperature range [°C] Internal Vref INL DNL Pins [number] Package [Type] Packing ZADCS1082VIS20T 10 8 250 -25°C to +85°C  ± 0,4 LSB ± 0,4 LSB 20 SSOP Tube ZADCS1082IS20T 10 8 250 -25°C to +85°C -- ± 0,4 LSB ± 0,4 LSB 20 SSOP Tube ZADCS1042VIS16T 10 4 250 -25°C to +85°C  ± 0,4 LSB ± 0,4 LSB 16 SSOP Tube ZADCS1042IS16T 10 4 250 -25°C to +85°C -- ± 0,4 LSB ± 0,4 LSB 16 SSOP Tube ZADCS1022VIS14T 10 2 250 -25°C to +85°C  ± 0,4 LSB ± 0,4 LSB 14 SSOP Tube ZADCS1022IS14T 10 2 250 -25°C to +85°C -- ± 0,4 LSB ± 0,4 LSB 14 SSOP Tube Sales and Further Information www.zmdi.com adc@zmdi.com Zentrum Mikroelektronik Dresden AG Grenzstrasse 28

01109 Dresden

ZMD America, Inc.

8413 Excelsior Drive

Madison, WI 53717 USA Zentrum Mikroelektronik Dresden AG, Japan Office 2nd Floor, Shinbashi Tokyu Bldg. 4-21-3, Shinbashi, Minato-ku Tokyo, 105-0004 Japan ZMD FAR EAST, Ltd. 3F, No. 51, Sec. 2, Keelung Road

11052 Taipei

Phone +49 (0)351.8822.7232 Fax +49 (0)351.8822.87232 Phone +1 (608) 829-1987 Fax +1 (631) 549-2882 Phone +81.3.6895.7410 Fax +81.3.6895.7301 Phone +886 2 2377 8189 Fax +886 2 2377 8199 DISCLAIMER: This information applies to a product under development. Its characteristics and specifications are PRELIMINARY and subject to change without notice. Zentrum Mikroelektronik Dresden AG (ZMD AG) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. The information furnished hereby is believed to be true and accurate. However, under no circumstances shall ZMD AG be liable to any customer, licensee, or any other third party for any special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical data. ZMD AG hereby expressly disclaims any liability of ZMD AG to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of ZMD AG for any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or otherwise.

10-Bit, 250ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 4 of 26

Contents

10-Bit, 250ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 6 of 26 List of Tables

10-Bit, 250ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 7 of 26

1 General Device Specification

1.1. Absolute Maximum Ratings (Non Operating) Symbol Parameter Min Max Unit Note VDD-GND VDD to AGND, DGND -0.3 6 V VAGND-DGND AGND to DGND -0.3 0.3 V CH0 – CH7, COM to AGND, DGND -0.3 VDD+0.3 V VREF, VREFADJ to AGND -0.3 VDD+0.3 V Digital Inputs to DGND -0.3 6 V Digital Outputs to DGND -0.3 VDD+0.3 V Digital Output Sink Current 25 mA Iin Input current into any pin except supply pins (Latch-Up) -100 100 mA VHBM Electrostatic discharge – Human Body Model (HBM) 2000 V 1 JCT Maximum Junction Temperature +150° °C OP Operating Temperature Range -25 +85 STG Storage temperature -65 +150 °C lead Lead Temperature 100%Sn JEDEC-J-STD-20C 260 °C H Humidity non-condensing 2 Ptot Total power dissipation 250 mW Thermal resistance of Package Rthj SSOP20 / 5.3mm 100 K/W Table 1: Absolute Maximum Ratings 1 HBM: C = 100pF charged to V HBM with resistor R = 1.5k in series, valid for all pins

2 Level 4 according to JEDEC-020A is guaranteed

10-Bit, 250ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 8 of 26 1.2. Package Pin Assignment ZADCS1082 / ZADCS1082V Package pin numb er Name Direction Type Description 1 nCS IN CMOS Digital Active Low Chip Select

2 DIN IN CMOS Digital Serial Data Input

3 DGND SUPPLY Digital Ground

4 AGND SUPPLY Analog Ground

5 VREF I/O Analog Reference Buffer Output / External Reference Input

6 COM IN Analog Ground reference for analog inputs in single ended mode

7 CH0 IN Analog Analog Input Channel 0

8 CH1 IN Analog Analog Input Channel 1

9 CH4 IN Analog Analog Input Channel 4

10 CH5 IN Analog Analog Input Channel 5

11 CH7 IN Analog Analog Input Channel 7

12 CH6 IN Analog Analog Input Channel 6

13 CH3 IN Analog Analog Input Channel 3

14 CH2 IN Analog Analog Input Channel 2

15 REFADJ I/O Analog Input to Reference Buffer Amplifier

16 VDD SUPPLY Positive Supply

17 nSHDN IN CMOS Digital Active Low Shutdown

18 DOUT OUT CMOS Digital Serial Data Output

19 SSTRB OUT CMOS Digital Serial Strobe Output

20 SCLK IN CMOS Digital Serial Clock Input

Table 2: Pin list ZADCS1082 / ZADCS1082V Figure 1 Pac kage Pin Assignment for ZADCS1082 & ZADCS1082V nCS SCLK SSTRBDIN ZADCS 1082 / ZADCS 1082V DOU TDGND nSHDNAGND VDDVREF REFADJ on ZADCS1082V, COM No connect on ZADCS1082 CH2CH0 CH3CH1 CH6 CH4 CH7CH5

10-Bit, 250ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 9 of 26 1.3. Package Pin Assignment ZADCS1042 / ZADCS1042V Package pin number Name Direction Type Description 1 nCS IN CMOS Digital Active Low Chip Select

9 CH3 IN Analog Analog Input Channel 3

10 CH2 IN Analog Analog Input Channel 2

11 REFADJ I/O Analog Input to Reference Buffer Amplifier

12 VDD SUPPLY Positive Supply

13 nSHDN IN CMOS Digital Active Low Shutdown

14 DOUT OUT CMOS Digital Serial Data Output

15 SSTRB OUT CMOS Digital Serial Strobe Output

16 SCLK IN CMOS Digital Serial Clock Input

Table 3: Pin list ZADCS1042 / ZADCS1042V Figure 2 Pac kage Pin Assignment for ZADCS1042 & ZADCS1042V nCS SCLK ZADCS 1042 / ZADCS 1042V SSTRBDIN DOU TDGND nSHDNAGND VDDVREF REFADJ on ZADCS1042V, COM No connect on ZADCS1042 CH2CH0 CH3CH1

10-Bit, 250ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 10 of 26 1.4. Package Pin Assignment ZADCS1022 / ZADCS1022V Package pin numb er Name Direction Type Description 1 nCS IN CMOS Digital Active Low Chip Select

9 REFADJ I/O Analog Input to Reference Buffer Amplifier

10 VDD SUPPLY Positive Supply

11 nSHDN IN CMOS Digital Active Low Shutdown

12 DOUT OUT CMOS Digital Serial Data Output

13 SSTRB OUT CMOS Digital Serial Strobe Output

14 SCLK IN CMOS Digital Serial Clock Input

Table 4: Pin list ZADCS1022 / ZADCS1022V Figure 3 Pac kage Pin Assignment for ZADCS1022 & ZADCS1022V nCS SCLK SSTRBDIN ZADCS 1022 ZADCS 1022V DOU TDGND nSHDNAGND VDDVREF REFADJ on ZADCS1022V, COM No connect on ZADCS1022 CH1CH0

10-Bit, 250ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 11 of 26 1.5. Electrical Characteristics 1.5.1. General Parameters (VDD = +2.7V to + 5.25V; f SCLK = 3.3MHz (50% duty cycle); 13 clocks/conversion cycle (250 ksps); V REF = 2.500V applied to VREF pin; OP = OPmin … OPmax) Parameter Symbol Conditions Min Typ Max Unit DC Accuracy Resolution 10 Bits Relative Accuracy INL ZADCS1082 / ZADCS1082V ZADCS1042 / ZADCS1042V ZADCS1022 / ZADCS1022V  0.4 LSB No Missing Codes NMC 10 Bits Differential Nonlinearity DNL ZADCS1082 / ZADCS1082V ZADCS1042 / ZADCS1042V ZADCS1022 / ZADCS1022V  0.4 LSB Offset Error  0.5  2.0 LSB Gain Error  0.5  2.0 LSB Gain Temperature Coefficient  0.25 ppm/°C Dynamic Specifications (10kHz sine-wave input, 0V to 2.500Vpp, 250ksps, 3.3MHz external clock) Signal-to-Noise + Distortion Ratio SINAD 61 dB Total Harmonic Distortion THD Up to the 5th harmonic -72 dB Spurious-Free Dynamic Range SFDR 74 dB Small-Signal Bandwidth -3dB roll off 3.8 MHz Conversion Rate Sampling Time (= Track/Hold Acquisition Time) tACQ Ext. Clock = 3.3MHz, 2.5 clocks/ acquisition 0.758 µs Ext. Clock = 3.3MHz, 10 clocks/ conversion 3.03 µs Conversion Time tCONV Int. Clock = 3.3MHz +/- 12% tolerance 2.75 3.50 µs Aperture Delay 30 ns Aperture Jitter < 50 ps External Clock Frequency 0.1 3.3 MHz Internal Clock Frequency 2.81 3.3 3.58 MHz Analog Inputs Unipolar, COM = 0V 0 to VREF Input Voltage Range, Single- Ended and Differential Bipolar, COM = VREF/2  VREF / 2 V Input Capacitance 16 pF

10-Bit, 250ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 12 of 26 1.5.2. Specific Parameters of ZADCS10x2V versi ons (with Internal Reference) (VDD = +2.7V to + 5.25V; fSCLK = 3.3MHz (50% duty cycle); 13 clocks/conversion cycle (250 ksps); OP = OPmin … OPmax) Parameter Symbol Conditions Min Typ Max Unit Internal Reference at VREF VREF Output Voltage TA = + 25°C 2.480 2.500 2.520 V VREF Short-Circuit Current 30 mA VREF Temperature Coefficient ± 30 ± 50 ppm/°C Load Regulation 0 to 0.2mA output load 0.35 mV Capacitive Bypass at VREF 4.7 µF Capacitive Bypass at REFADJ 0.047 µF REFADJ Adjustment Range  1.5 % External Reference at VREF (internal buffer disabled by V(REFADJ) = VDD) VREF Input Voltage Range 1.0 VDD + 50mV V VREF Input Current VREF = 2.5V 180 215 µA VREF Input Resistance 11.5 14 k Shutdown VREF Input Current 0.1 µA REFADJ Buffer Disable Threshold VDD- 0.5 V External Reference at VREF_ADJ Reference Buffer Gain 2.00 VREF_ADJ Input Current ±80 µA Full Power Down VREFADJ Input Current Full Power-Down mode 0.1 µA Power Requirements Positive Supply Voltage VDD 2.7 5.25 V Operating Mode ext. VREF 0.85 1.0 mA Operating Mode int. VREF 1.3 1.4 mA Fast Power-Down 250 300 Positive Supply Current ZADCS1082VI ZADCS1042VI ZADCS1022VI IDD VDD=3.6V Full Power-Down 0.5 4.0 µA Operating Mode ext. VREF 1.00 1.3 mA Operating Mode int. VREF 1.40 1.6 mA Fast Power-Down 250 300 Positive Supply Current ZADCS1082VI ZADCS1042VI ZADCS1022VI IDD VDD=5.2V Full Power-Down 0.5 4.0 µA

10-Bit, 250ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 13 of 26 1.5.3. Specific Parameters of basic ZADCS10x2 versio ns (without Internal Reference) (VDD = +2.7V to + 5.25V; fSCLK = 3.3MHz (50% duty cycle); 13 clocks/conversion cycle (250 ksps); OP = OPmin … OPmax) Parameter Symbol Conditions Min Typ Max Unit External Reference at VREF VREF Input Voltage Range 1.0 VDD + 50mV V VREF Input Current VREF = 2.5V 180 215 µA VREF Input Resistance 11.5 14 k Shutdown VREF Input Current 0.1 µA Capacitive Bypass at VREF 4.7 µF Power Requirements Positive Supply Voltage VDD 2.7 5.25 V Operating Mode 0.85 1.0 Positive Supply Current ZADCS1082I ZADCS1042I ZADCS1022I IDD VDD = 3.6V Full Power-Down 0.5 4.0 µA Operating Mode 1.00 1.3 Positive Supply Current ZADCS1082I ZADCS1042I ZADCS1022I IDD VDD = 5.25V Full Power-Down 0.5 4.0 µA 1.5.4. Digital Pin Parameters (VDD = +2.7V to + 5.25V; fSCLK = 3.3MHz (50% duty cycle); 13 clocks/conversion cycle (250 ksps); OP = OPmin … OPmax) Parameter Symbol Conditions Min Typ Max Unit Digital Inputs (DIN, SCLK, CS, nSHDN) VDD = 2.7V 1.9 V Logic High Level VIH VDD = 5.25V 3.3 V VDD = 2.7V 0.7 V Logic Low Level VIL VDD = 5.25V 1.4 V Hysteresis V Hyst 0.7 V Input Leakage IIN VIN = 0V or VDD ± 0.1 ± 1.0 µA Input Capacitance CIN 5 pF Digital Outptus (DOUT, SSTRB) VDD = 2.7V 3.5 8.5 mA Output High Current IOH V OH= VDD – 0.5V VDD = 5.25V 5.5 10.8 mA VDD = 2.7V 4 11.5 mA Output Low Voltage IOL V OL= 0.4V VDD = 5.25V 6.4 15.3 mA Three-State Leakage Current ILeak nCS = VDD ± 0.1 ± 1.0 µA Three-State Output Capacitance COUT nCS = VDD 5 pF

10-Bit, 250ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 14 of 26 1.6. Typical Operating Characteristics Integral Nonlinearity vs. Code -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 0 128 256 384 512 640 768 896 1024 Code INL (LSB) Differential Nonlinearity vs. Code -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 0 128 256 384 512 640 768 896 1024 Code DNL (LSB) IDD vs. VDD 150 300 450 600 750 900 1050 1200 1350 1500 2 . 73 . 44 . 14 . 8 VDD (V) IDD (µA) 5.5 IDDstatic vs. Temperature ZADCS12x2V, internal reference active, at VDD = 3.3V 500 550 600 650 700 -40 -20 0 20 40 60 80 100 Temperatur (°C) IDD (µA) IDDactive (converting) vs. Temperature ZADCS12x2V, internal reference active, at VDD = 3.3V 900 950 1000 1050 - 4 0 - 2 00 2 04 06 08 0 1 0 0 Temperatur (°C) IDD (µA) VREF vs. Temperature 2.498 2.499 2.500 2.501 -25 0 25 50 75 Temperature (°C) Reference Voltage (v) IDDactive (converting) IDDstatic External V Internal V REF REF

10-Bit, 250ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 15 of 26

2 Detailed Description

2.1. General Operation The ZADCS 10x2 family is a set of classic successive approximation register (SAR) type converters. The architecture is based on a capacitive charge redist ribution DAC merged with a resistor string DAC building a hybrid converter with excellent monotonicity and DNL properties. The Sample & Hold function is inherent to the cap acitive DAC. This avoids additional active com ponents in the signal path t hat could distort the input signal or introduce errors. All devices in the ZADCS10x2 family build on the same converter core and differ only in the number of input channels and the availability of an internal reference voltage generator. The ZADCS10x2 V versions are equipped with a highly accurate internal 1.25V bandgap reference which is available at the VREFADJ pin. The bandgap voltage is further amplified by an internal buffer am plifier to 2.50V that is available at pin VREF. All other versions come without the internal reference and the internal buffer amplifier. They require an external reference supplied at VREF, with the benefit of considerably lower power consumption. A basic application schematic for ZADC1082 V is shown in Figure 4 , for ZADCS1082 in Figure 5 . ZADCS1 082V can also be operated with an external reference, if VREFADJ is tied to VDD. Figure 4: Basic application schematic for ZADCS1082V Figure 5: Basic application schematic for ZADCS1082 A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 0 0 0 IN+ IN- 1 0 0 IN+ IN- 0 0 1 IN+ IN- 1 0 1 IN+ IN- 0 1 0 IN+ IN- 1 1 0 IN+ IN- 0 1 1 IN+ IN- 1 1 1 IN+ IN- Table 5: Channel selection in Single Ended Mode A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 0 0 0 IN+ IN- 0 0 1 IN+ IN- 0 1 0 IN+ IN- 0 1 1 IN+ IN- 1 0 0 IN- IN+ 1 0 1 IN- IN+ 1 1 0 IN- IN+ 1 1 1 IN- IN+ Table 6: Channel selection in Differential Mode Single-ended or differential analog inputs, 0V … +2.5V nCS 1 DIN 2 DGND 3 AGND 4 VREF 5 COM 6 CH0 7 CH1 8 CH4 9 CH5 10 SCLK 20 SSTRB 19 DOUT 18 nSHDN 17 VDD 16 VREFADJ 15 CH2 14 CH3 13 CH6 12 CH7 11 ZADCS1082V 47nF ≥ 4.7µF 0.1µF 10µF SCK I/O MOSI MISO µC +2.7V to 5.25V Single-ended or differential analog inputs, 0V … +V REF nCS 1 DIN 2 DGND 3 AGND 4 VREF 5 COM6 CH0 7 CH1 8 CH4 9 CH5 10 SCLK 20 SSTRB 19 DOUT 18 nSHDN 17 VDD 16 n.c. 15 CH2 14 CH3 13 CH6 12 CH7 11 ZADCS1082 ≥ 4.7µF 0.1µF µC MI SO MOSI SCK I/O +2.7V to 5.25V 10µF

10-Bit, 250ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 21 of 26 Field Prog rammable Gate Arrays (FPGA) or Application Specific Integrated Circuits (ASIC) may use this operation mode. Digital Timing In general the clock frequency at SCLK may vary from 0.1MHz to 3.3MHz. Considering all telegram pauses or other interruptions of a continuous clock at SCLK, each conversion must be completed within 1.2ms from the falling clock edge of the eighth bit in the Control By te. Otherwise the signal that was captured during sample/hold may drop to noticeable affect the conversion result. Further detailed timing information on the digital interface is provided in Table 8 and Figure 15. Parameter Symbol Conditions Min Typ Max Unit SCLK Periode tSCLK 303.0 ns SCLK Pulse Width High tSCLKhigh 151.5 ns SCLK Pulse Width Low tSCLKlow 151.5 ns DIN to SCLK Setup tDinSetup 30 ns DIN to SCLK Hold tDinHold 10 ns nCS Fall to SCLK Setup tnCSSetup 30 ns SCLK Fall to DOUT & SSTRB Hold tOutHold C Load = 20pF 10 ns SCLK Fall to DOUT & SSTRB Valid t OutValid C Load = 20pF 40 ns nCS Rise to DOUT & SSTRB Disable t OutDisable C Load = 20pF 10 60 ns nCS Fall to DOUT & SSTRB Enable t OutEnable C Load = 20pF 60 ns nCS Pulse Width High tnCSHigh 100 ns Table 8: Timing Characterisitics (VDD = +2.7V to + 5.25V; OP = OPmin … OPmax) Figure 15 Detailed Timing Diagram nCS SCLK DIN SSTRB DOUT t tSCLKhigh SCL tSCLKlow tDINhold tDINsetup tnCSSetup tOutValid tOutEnable tOutEnable tOutDisable tOutHold tnCSHig

10-Bit, 250ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 22 of 26 Outpu t Code Format ZADCS10x2 family devices do all support unipolar and bi polar operation modes. The digital output code is straight binary in unipolar mode. It ranges from 0x00 for an input voltage difference of 0V to 0xFF for an input voltage difference of VREF (Full Scale = FS). The first code transition (0x00  0x01) occurs at a voltage equivalent to ½ LSB, the last (0xFE  0xFF) at VREF-1.5 LSB. See also Figure 16 for details. In bipolar mode a two’s complement coding is applied. Code transitions occur again halfway between successive integer LSB values. The transfer function is shown in Figure 17. Figure 16 : Unipolar Transfer Function Figure 17: Bipolar Transfer Function 2.5. Power Dissipation The ZADCS1 0x2 family offers three different ways to save operating current between conversions. Two different software controlled power down modes can be activated to automatically shut-down the device after completion of a conversion. They differ in the amount of circuitry that is powered down. Software Power Down Full Power Down Mode shuts down the entire analog part of the IC, reducing the static IDD of the device to less than 0.5µA if no external clock is provided at SCLK. Fast Power Down mode is only useful with ZADCS10x2V devices if the internal voltage reference is used. During Fast Power-Down the bandgap and the VREFADJ output buffer are kept alive while all other inte rnal analog circuitry is shut down. The benefit of Fast Power Down mode is a shorter turn on time of the reference compared to Full Power-Down Mode. This is basically due to the fact that the low pass which is formed at the VREFADJ output by the internal 20kΩ resistor and the external buffer capacitor of 47nF is not discharged in Fast Power-Down Mode. The settling time of the low pass at VREFADJ is about 7ms to re ach 10 bit accuracy. The Fast Power Down mode omits this settling and reduces the turn on time to about 200µs. To wake up the IC out of either software power down mode, it is sufficient to send a Start Bit while nCS is LOW. Since micro controllers can commonly transfer full bytes per transaction only, a dummy conversion is usually carried out to wake the device. In all application cases where an external reference voltage is supplied (basic ZADCS10x2 and ZADCS10x2 V with VREFADJ tied to VDD) there is no turn on time to be considered. The first conversion is already valid. Fast Power-Down and Full Power-Down Mode do not show any difference in this configuration. 11 … 111 11 … 110 11 … 101 00 … 000 00 … 001 00 … 010 1 2 3 FS 0 Input Voltage (LSB) FS-3/2 LSB ZS = V(IN-) FS = VREF +V(IN- 1LSB = VREF 1024 (ZS) Output Code Output Code ZS = V(IN-) + FS = ½V +V(IN-) REF 01 … 111 01 … 110 10 … 000 10 … 001 00 … 000 +FS-FS Input Voltage (LSB) +FS-3/2 LSB 1LSB = VREF 1024 00 … 001 00 … 011 11 … 111 11 … 110 - FS = -½V +V(IN-) REF 11 … 101 ZS

10-Bit, 250ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 23 of 26 Hardware Power Down The third power down mode is called Hardware Power-Down. It is initiated by pulling the nSHDN pin LOW. If this condition is true, the device will immediately shut down all circuitry just as in Full Power Down-Mode. The IC wakes up if nSHDN is tied HIGH. There is no internal pull-up that would allow nSHDN to float during normal operation. This ensures the lowest possible power consumption in power down mode. General Power Considerations Even without activating any power down mode, the devic es out of the ZADCS10x2 family reduce their power consumption between conversions automatically. The com parator, which contributes a considerable amount to the overall current consumption of the device, is shut off as soon as a conversion is ended. It gets turned on at the start of the next acquisition period. This expl ains the difference between the IDDstatic and IDDactive measurements shown in chapter 1.6 Typical Operating Characteristics. The avera ge current consumption of the device depe nds very much on the sampling frequency and the type of protocol used to communicate with the device. In order to achieve the lowest powe r consumption at low sampling frequencies, it is suggested to keep the conversion clock frequency at the maximum level of 3.3MHz and to power down the device between consecutive conversions. Figure 18 shows the characteristic current consumption of the ZADCS10x2 family with external reference supply versus Sampling Rate

10-Bit, 250ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 24 of 26

3 Layout

ptimum conversion performance care must be taken in design and layout of the application board. It is highly recommended to use printed circuit boar ds instead of wire wrap designs and to establish a single point star connection ground system towards AGND (see Figure 19). For optim al noise performance the star point should be lo cated very close to the AGND pin of the converter. The ground return to the power supply should be as short as possible and low impedance. All other analog ground points of external circuitry that is related to the A/D converter as well as the DGND pin of the device should be connected to this ground poin t too. Any other digital ground system should be kept apart as far as possible and connect on the power supply point only. Analog and digital signal domains should also be separ ated as well as possible and analog input signals should be shielded by AGND ground planes from electromagnetic interferences. Four-layer PCB boards that allow smaller vertical distances between the ground plane and the shielded signals do generally show a better performance than two-layer boards. The sampling phase is the most critical portion of the overall conversion timing for signal distortion. If possible, the switching of any high power devic es or nearby digital logic should be avoided during the sampling phase of the converter. Current consumption vs. Sample Rate External Clock Mode, External V REF, fSCLK = 3.3MHz 100 1000 10000 1 10 100 1000 Sample Rate (ksps) Average Supply Current (µA) Figure 18: Supply Current versus Sampling Rate Figure 19: Optimal Power-Supply Grounding System Optional R = 10Ω VDD1 (+2.7 … +5.25V) ZADCS10x2 Family Power Supplies COM DGND Other DGND GND Digital DVDDCircuitr y VDD2 The fully differential internal architecture of the ZADCS10x2 family ensures very good suppression of power supply noise. Nevertheless, the SAR architecture is generally sensitive to glitches or sudden changes of the power supply that occur shortly befor e the latching of the comparator outpu t. It is therefore recommended to bypass the power supply connection very close to the device with capacitors of 0.1µF (ceramic) and >1µF (electrolytic). In case of a noisy supply, an additional se ries resistor of 5 to 10 ohms can be used to low-pass filter the supply voltage. The reference voltage should alwa ys be bypassed with capacitors of 0.1µF (ceramic) and ≥ 4.7µF (electrolytic) as close as possible to the VREF pin. If V REF is provided by an external source, any series resistance in the V REF supply path can cause a gain error of the converter. Duri ng conversion, a DC current of about 100µA is drawn through the VREF pin that could cause a noticeable voltage drop across the resistance.

10-Bit, 250ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 25 of 26

4 Package Drawing

082 devices are delivered in a 20-pin SSOP- package that has the dimensions as shown in Figure 20 and Table 9 . ZADCS1042 and ZADCS1022 devices apply respective 16-pin and 14-pin SSOP-packages. Their dim ensions are specified in Table 9 and Table 10. Figure 20: Package Outline Dimensions Symbol A A 1 A 2 b P c D E enom H E L P Z k  0.65 7.65 0.63 0.25 0° Table 9: Package Dimensions for ZADC1082 devices (mm) Symbol A A 1 A 2 b P c D E enom H E L P Z k  0.65 7.65 0.63 0.25 0° Table 10: Package Dimensions for ZADC1042 devices (mm) Symbol A A 1 A 2 b P c D E enom H E L P Z k  0.65 7.65 0.63 0.25 0° Table 11: Package Dimensions for ZADC1022 devices (mm)

10-Bit, 250ksps, ADC Family Data Sheet October 12, 2011 © 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 26 of 26 Sales and Further Information www.zmdi.com adc@zmdi.com Zentrum Mikroelektronik Dresden AG Grenzstrasse 28 ZMD America, Inc. Madison, WI 53717 USA Zentrum Mikroelektronik Dresden AG, Japan Office 2nd Floor, Shinbashi Tokyu Bldg. 4-21-3, Shinbashi, Minato-ku Tokyo, 105-0004 Japan ZMD FAR EAST, Ltd. 3F, No. 51, Sec. 2, Keelung Road Phone +49 (0)351.8822.7232 Fax +49 (0)351.8822.87232 Phone +1 (608) 829-1987 Fax +1 (631) 549-2882 Phone +81.3.6895.7410 Fax +81.3.6895.7301 Phone +886 2 2377 8189 Fax +886 2 2377 8199 DISCLAIMER: This information applies to a product under development. Its characteristics and specifications are PRELIMINARY and subject to change without notice. Zentrum Mikroelektronik Dresden AG (ZMD AG) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. The information furnished hereby is believed to be true and accurate. However, under no circumstances shall ZMD AG be liable to any customer, licensee, or any other third party for any special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical data. ZMD AG hereby expressly disclaims any liability of ZMD AG to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of ZMD AG for any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or otherwise.

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