X9400

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Technical content

FN8189 Rev 4.00 Page 1 of 20 September 2, 2015 FN8189 Rev 4.00 September 2, 2015 X9400 Low Noise/Low Power/SPI Bus Quad Digitally Controlled Potentiometers (XDCP™) DATASHEET

FEATURES

• Four potentiometers per package
• 64 resistor taps
• SPI serial interface for write, read, and transfer operations of the potentiometer
• Wiper resistance, 40 typical at 5V.
• Four non-volatile data registers for each potentiometer
• Non-volatile storage of multiple wiper position
• Power-on recall. Loads saved wiper position on power-up.
• Standby current < 1µA max
• S y s t e m V CC: 2.7V to 5.5V operation
• A n a l o g V+/V–: -5V to +5V
• 1 0 k, 2.5k end to end resistance
• 100 yr. data retention
• Endurance: 100,000 data changes per bit per register
• Low power CMOS
• 24 Ld SOIC and 24 Ld TSSOP
• Pb-free plus anneal available (RoHS compliant)

DESCRIPTION

The X9400 integrates four digitally controlled potentiometers (XDCPs) on a monolithic CMOS integrated circuit. The digitally controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI serial bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four nonvolatile Data Registers (DR0-3) that can be directly writte n to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power-up recalls the contents of DR0 to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. BLOCK DIAGRAM Interface and Control Circuitry CS SCK SO R0 R1 R2 R3 Wiper Counter Register (WCR) Resistor Array Pot 1 VH1/RH1 VL1/RL1 R0 R1 R2 R3 Wiper Counter Register (WCR) VH0/RH0 VL0/RL0 Data VW0/RW0 VW1/RW1 R0 R1 R2 R3 Resistor Array VH2/RH2 VL2/RL2 VW2/RW2 R0 R1 R2 R3 Resistor Array VH3/RH3 VL3/RL3 VW3/RW3 Wiper Counter Register (WCR) Wiper Counter Register (WCR) Pot 3 Pot 2 HOLD Pot 0VCC VSS WP SI

FN8189 Rev 4.00 Page 2 of 20 September 2, 2015

Ordering Information

(V) POTENTIOMETER ORGANIZATION (k) TEMP. RANGE (°C) PACKAGE PKG. DWG. # X9400WS24ZT1 (Note) (No longer available, recommended replacement: X9400WS24IZT1) X9400WS Z 5 ±10% 10 0 to +70 24 Ld SOIC (300 mil) (Pb-free) Tape and Reel M24.3 X9400WS24IZ* (Note) X9400WS ZI -40 to +85 24 Ld SOIC (300 mil) (Pb-free) M24.3 X9400WV24IZ* (Note) X9400WV ZI -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9400WV24Z* (Note) (No longer available, recommended replacement: X9400WS24IZT1) X9400WV Z 0 to +70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9400WS24IZ-2.7* (Note) X9400WS ZG 2.7 to 5.5 -40 to +85 24 Ld SOIC (300 mil) (Pb-free) M24.3 X9400WV24IZ-2.7* (Note) (No longer available, recommended replacement: X9400WS24IZT1) X9400WV ZG -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9400WV24Z-2.7* (Note) (No longer available, recommended replacement: X9400WS24IZT1) X9400WV ZF 0 to +70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FN8189 Rev 4.00 Page 3 of 20 September 2, 2015 PIN DESCRIPTIONS Host Interface Pins Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on th is pin. Data is clocked out by the falling edge of the serial clock. Serial Input SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The SCK input is used to clock data into and out of the X9400. Chip Select (CS When CS is HIGH, the X9400 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the de vice will be in the standby state. CS LOW enables the X9400, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Hold (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again wh ile SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. Device Address (A0 - A1) The address inputs are used to set the least significant 2 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9400. A maximum of 4 devices may occupy the SPI serial bus. Potentiometer Pins V H/RH (VH0/RH0 - VH3/RH3), VL/RL (VL0/RL0 - VL3/RL3) The VH/RH and VL/RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. VW/RW (VW0/RW0 - VW3/RW3) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. Hardware Write Protect Input (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. Analog Supplies (V+, V-) The analog Supplies V+, V- are the supply voltages for the XDCP analog section. PIN CONFIGURATION VCC VL0/RL0 VH0/RH0 WP SI VL3/RL3 VH3/RH3 VW3/RW3 SO HOLD SCK V L2/RL2 VH2/RH2 SOIC X9400 VSS VW0/RW0 CS VL1/RL1 VH1/RH1 VW1/RW1 VW2/RW2 SI VH2/RH2 WP CS VW0/RW0 VCC VL3/RL3 VH3/RH3 VW3/RW3 TSSOP X9400 VW2/RW2 12HOLD VL1/RL1 VH1/RH1 VW1/RW1 SO VH0/RH0 SCK VL2/RL2 VL0/RL0 VSS

FN8189 Rev 4.00 Page 4 of 20 September 2, 2015 PIN NAMES DEVICE DESCRIPTION The X9400 is a highly integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers. Serial Interface The X9400 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. Array Description The X9400 is comprised of four resistor arrays. Each array contains 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (V H/RH and VL/RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (VW/RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by a wiper counter register (WCR). The six bits of the WCR are decoded to select, and enable, one of sixty-four switches. Wiper Counter Register (WCR) The X9400 contains four Wiper Counter Registers, one for each XDCP potentiometer. The WCR is equivalent to a serial-in, parallel-out regi ster/counter with its outputs decoded to select one of si xty-four switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register or global XFR data register instructions (parallel load); it can be mo dified one step at a time by the increment/decrement instruction. Finally, it is loaded with the contents of its Data Register zero (DR0) upon power-up. The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9400 is powered-down. Although the register is aut omatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Data Registers Each potentiometer has four 6-bit nonvolatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Counter Register. All operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Data Register Detail Symbol Description SCK Serial Clock SI, SO Serial Data A0 - A1 Device Address VH0/RH0 - VH3/RH3, VL0/RL0 - VL3/RL3 Potentiometer Pins (terminal equivalent) V W0/RW0 - VW1/RW1 Potentiometer Pins (wiper equivalent) WP Hardware Write Protection VCC System Supply Voltage VSS System Ground NC No Connection (MSB) (LSB) D5 D4 D3 D2 D1 D0 NV NV NV NV NV NV

Figure 3. Instruction Byte Format is to be affected by the instruction. to the associated Wiper Counter Register. Register to the specified associated Data Register. Registers to the associated Wiper Counter Registers. Registers to the specified associated Data Registers. all potentiometers and one associated register. for this operation are shown in Figure 7 and Figure 8.

Figure 4. Two-Byte Instruction Sequence Figure 5. Three-Byte Instruction Sequence (Write) Figure 6. Three-Byte Instruction Sequence (Read) Figure 7. Increment/Decrement Instruction Sequence

010100 A 1 A 0 I3 I2 I1 I0 0 P1 P0

Figure 8. Increment/Decrement Timing Limits Table 1. Instruction Set

1 R0 P1 P0 Transfer the contents of the Data Register pointed to

1 R0 P1 P0 Transfer the contents of the Wiper Counter

1 R0 0 0 Transfer the contents of the Data Registers pointed

1000 R 1 R0 0 0 Transfer the contents of all Wiper Counter

FN8189 Rev 4.00 Page 9 of 20 September 2, 2015 Instruction Format Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master. (2) WPx refers to wiper position data in the Counter Register (3) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high). (4) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high). Read Wiper Counter Register (WCR) Write Wiper Counter Register (WCR) Read Data Register (DR) Write Data Register (DR) Transfer Data Register (DR) to Wiper Counter Register (WCR) Transfer Wiper Counter Register (WCR) to Data Register (DR) CS Falling Edge device type identifier device addresses instruction opcode WCR addresses wiper position (sent by X9400 on SO) CS Rising Edge010100 A A 0 100100 P P 0 00 W P W P W P W P W P W P CS Falling Edge device type identifier device addresses instruction opcode WCR addresses Data Byte (sent by Host on SI) CS Rising Edge010100 A A 0 101000 P P 0 00 W P W P W P W P W P W P CS Falling Edge device type identifier device addresses instruction opcode DR and WCR addresses Data Byte (sent by X9400 on SO) CS Rising Edge010100 A A 0 1011 R R P P 0 00 W P W P W P W P W P W P CS Falling Edge device type identifier device addresses instruction opcode DR and WCR addresses Data Byte (sent by host on SI) CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 010100 A A 0 1100 R R P P 0 00 W P W P W P W P W P W P CS Falling Edge device type identifier device addresses instruction opcode DR and WCR addresses CS Rising Edge010100 A A 0 1101 R R P P CS Falling Edge device type identifier device addresses instruction opcode DR and WCR addresses CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 010100 A A 0 1110 R R P P

FN8189 Rev 4.00 Page 10 of 20 September 2, 2015 Increment/Decrement Wiper Counter Register (WCR) Global Transfer Data Register (DR) to Wiper Counter Register (WCR) Global Transfer Wiper Counter Register (WCR) to Data Register (DR) Read Status CS Falling Edge device type identifier device addresses instruction opcode WCR addresses increment/decrement (sent by master on SDA) CS Rising Edge010100 A A 0 0010XX P P D D .... I/ D D CS Falling Edge device type identifier device addresses instruction opcode DR addresses CS Rising Edge010100 A A 0 0001 R R 0 00 CS Falling Edge device type identifier device addresses instruction opcode DR addresses CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 010100 A A 0 1000 R R 0 00 CS Falling Edge device type identifier device addresses instruction opcode wiper addresses Data Byte (sent by X9400 on SO) CS Rising Edge010100 A A 0 010100010000000 W I P

FN8189 Rev 4.00 Page 11 of 20 September 2, 2015 ABSOLUTE MAXIMUM RATINGS Voltage on SCK, SCL or any address Any V COMMENT Stresses above those liste d under “Absolute Maximum Ratings” may cause perman ent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sectio ns of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Notes: (1) Absolute linearity is utilized to determi ne actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to deter mine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT/63 or (R H - RL)/63, single pot Symbol Parameter Limits Test ConditionsMin. Typ. Max. Unit RTOTAL End to end resistance ±20 % Power rating 50 mW 25 C, each pot IW Wiper current ±6 mA RW Wiper resistance 150 250  Wiper Current =  1mA, VCC =3 V 40 100  Wiper Current =  1mA, VCC =5 V Vv+ Voltage on V+ Pin X9400 +4.5 +5.5 V Vv- Voltage on V- Pin X9400 -5.5 -4.5 V VTERM Voltage on any VH/RH or VL/RL Pin V- V+ V Noise -120 dBV Ref: 1kHz Resolution 1.6 % Absolute linearity (1) -1 +1 MI (3) Rw(n)(actual) - Rw(n)(expected) Relative linearity (2) -0.2 +0.2 MI (3) Rw(n + 1) - [Rw(n) + MI] Temperature coefficient of RTOTAL 300 ppm/ C Ratiometric temp. coefficient ±20 ppm/°C CH/CL/CW Potentiometer capacitances 10/10/25 pF See Spice Macromodel IAL RH, RL, RW leakage current 0.1 10 µA V IN = VSS to VCC. Device is in stand-by mode. RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial 0 C+ 7 0 C Industrial -40 C+ 8 5 C Device Supply Voltage (V CC) Limits X9400 5V 10% X9400-2.7 2.7V to 5.5V

FN8189 Rev 4.00 Page 12 of 20 September 2, 2015 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) ENDURANCE AND DATA RETENTION CAPACITANCE POWER-UP TIMING POWER-UP REQUIREMENTS (Power-up sequencing can affect correct recall of the wiper registers) The preferred power-on sequence is as follows: First VCC, then the potentiometer pins, R H, R L, and R W. Voltage should not be applied to the potentiometer pins before V+ or V- is applied. The V CC ramp rate specifi- cation should be met, and any glitches or slope changes in the V CC line should be held to <100mV if possible. If VCC powers down, it should be held below 0.1V for more than 1 second before powering up again in order for proper wiper register recall. Also, V CC should not reverse polarity by more than 0.5V. Recall of wiper position will not be complete until V CC, V+ and V-reach their final value. EQUIVALENT A.C. LOAD CIRCUIT Symbol Parameter Limits Test ConditionsMin. Typ. Max. Units ICC1 VCC supply current (Active) 400 µA f SCK = 2MHz, SO = Open, Other Inputs = VSS ICC2 VCC supply current (Nonvolatile Write) 1m A f SCK = 2MHz, SO = Open, Other Inputs = VSS ISB VCC current (standby) 1 µA SCK = SI = V SS, Addr. = VSS ILI Input leakage current 10 µA V IN = VSS to VCC ILO Output leakage current 10 µA V OUT = VSS to VCC VIH Input HIGH voltage V CC x 0.7 V CC + 0.5 V VIL Input LOW voltage -0.5 V CC x 0.1 V VOL Output LOW voltage 0.4 V I OL = 3mA Parameter Min. Unit Minimum endurance 100,000 Data changes per bit per register Data retention 100 years Symbol Test Max. Unit Test Conditions COUT(4) Output capacitance (SO) 8 pF V OUT = 0V CIN(4) Input capacitance (A0, A1, SI, and SCK) 6 pF V IN = 0V Symbol Parameter Min. Max. Unit tPUR(5) Power-up to initiation of read operation 1 ms tPUW(5) Power-up to initiation of write operation 5 ms tR VCC(4) VCC Power-up ramp 0.2 50 V/msec 1533 100pF SDA Output

FN8189 Rev 4.00 Page 13 of 20 September 2, 2015 A.C. TEST CONDITIONS Notes: (4) This parameter is periodically sampled and not 100% tested (5) t PUR and t PUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific instruction can be issued. These parameters are peri- odically sampled and not 100% tested. SPICE Macro Model SYMBOL TABLE AC TIMING Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5 10pF RH RTOTAL CH 25pF CW CL 10pF RW RL WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance Symbol Parameter Min. Max. Unit fSCK SSI/SPI clock frequency 2.0 MHz tCYC SSI/SPI clock cycle time 500 ns tWH SSI/SPI clock high time 200 ns tWL SSI/SPI clock low time 200 ns tLEAD Lead time 250 ns tLAG Lag time 250 ns tSU SI, SCK, HOLD and CS input setup time 50 ns tH SI, SCK, HOLD and CS input hold time 50 ns tRI SI, SCK, HOLD and CS input rise time 2 µs tFI SI, SCK, HOLD and CS input fall time 2 µs tDIS SO output disable time 0 500 ns tV SO output valid time 100 ns tHO SO output hold time 0 ns tRO SO output rise time 50 ns tFO SO output fall time 50 ns tHOLD HOLD time 400 ns tHSU HOLD setup time 100 ns tHH HOLD hold time 100 ns tHZ HOLD low to output in High Z 100 ns tLZ HOLD high to output in Low Z 100 ns TI Noise suppression time constant at SI, SCK, HOLD and CS inputs 20 ns tCS CS deselect time 2 µs tWPASU WP, A0 and A1 setup time 0 ns tWPAH WP, A0 and A1 hold time 0 ns

FN8189 Rev 4.00 Page 14 of 20 September 2, 2015 HIGH-VOLTAGE WRITE CYCLE TIMING XDCP TIMING TIMING DIAGRAMS Input Timing Output Timing Symbol Parameter Typ. Max. Unit tWR High-voltage write cycle time (store instructions) 5 10 ms Symbol Parameter Min. Max. Unit tWRPO Wiper response time after the third (last) power supply is stable 10 µs tWRL Wiper response time after instruction issued (all load instructions) 10 µs tWRID Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 450 ns ... CS SCK SI SO MSB LSB High Impedance tLEAD tHtSU tFI tCS tLAGtCYC tWL ... tRItWH ... CS SCK SO SI ADDR MSB LSB tDIStHOtV ...

FN8189 Rev 4.00 Page 15 of 20 September 2, 2015 Hold Timing XDCP Timing (for All Load Instructions) XDCP Timing (for Increment/Decrement Instruction) ... CS SCK SO SI HOLD tHSU tHH tLZtHZ tHOLD tRO tFO ... CS SCK SI MSB LSB VW/RW tWRL ... SO High Impedance ... CS SCK SO SI ADDR tWRID High Impedance VW/RW ...Inc/Dec Inc/Dec ...

FN8189 Rev 4.00 Page 16 of 20 September 2, 2015 Write Protect and Device Address Pins Timing APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers Application Circuits CS WP tWPASU tWPAH (Any Instruction) VR VW/RW +VR I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Noninverting Amplifier Voltage Regulator Offset Voltage Adjustment Comparator with Hysteresis VS VO VO = (1+R2/R1)VS Iadj VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO (REG)VIN 317 VS VO R2R1 VUL = {R1/(R1+R2)} VO(max) VLL = {R1/(R1+R2)} VO(min) 100k 10k10k 10k -12V+12V TL072 –VS VO R2R1

FN8189 Rev 4.00 Page 17 of 20 September 2, 2015 Application Circuits (continued) Inverting Amplifier Equivalent L-R Circuit VS VO R2R1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VS Function Generator VO = G VS G = - R2/R1 R2C1 ZIN – R2 RA RB frequency  R1, R2, C amplitude  RA, RB C Attenuator Filter VS VO VO = G VS -1/2  G  +1/2 GO = 1 + R2/R1 fc = 1/(2RC) R4 All RS = 10k VS R C VO

FN8189 Rev 4.00 Page 18 of 20 September 2, 2015 X9400 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see For additional products, see © Copyright Intersil Americas LLC 2005-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE September 2, 2015 FN8189.4 Updated Ordering Information Table on page 2. Added Revision History and About Intersil sections. Updated POD M24.3 from rev 1 to rev 2. Changes since rev 1: Updated to new POD standard by removing table listing dimensions and putting dimensions on drawing. Added Land Pattern. Updated POD MDP004 from rev E to rev F. Changes since rev E: Added dimensions (MILLIMETERS) to table column heading.

FN8189 Rev 4.00 Page 19 of 20 September 2, 2015 Package Outline Drawing M24.3

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC)

Rev 2, 3/11 TOP VIEW NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions in ( ) are not necessarily exact. 8. This outline conforms to JEDEC publication MS-013-AD ISSUE C. SIDE VIEW “A” SIDE VIEW “B” TYPICAL RECOMMENDED LAND PATTERN INDEX AREA 123 SEATING PLANE DETAIL "A" x 45° 7.60 (0.299) 7.40 (0.291) 0.75 (0.029) 0.25 (0.010) 10.65 (0.419) 10.00 (0.394) 1.27 (0.050) 0.40 (0.016) 15.60 (0.614) 15.20 (0.598) 2.65 (0.104) 0.10 (0.004) 1.27 (0.050) 0.51 (0.020) 0.23 (0.009) 1.981 (0.078) 9.373 (0.369)

FN8189 Rev 4.00 Page 20 of 20 September 2, 2015 Thin Shrink Small Outline Package Family (TSSOP) N (N/2)+1 (N/2) TOP VIEW AD 0.20 C B A N/2 LEAD TIPSB E1E

0.25 CABM

H PIN #1 I.D. 0.05 eC 0.10 C N LEADS SIDE VIEW

0.10 CABMb

c SEE DETAIL “X” END VIEW DETAIL X 0° - 8° GAUGE PLANE 0.25 LA1 A SEATING PLANE MDP0044 THIN SHRINK SMALL OUTLINE PACKAGE FAMILY SYMBOL MILLIMETERS TOLERANCE14 LD 16 LD 20 LD 24 LD 28 LD Rev. F 2/07 NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusi ons shall not exceed 0.25mm per side. 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M -1994.