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Document overview
- Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 18
Technical content
Features
- 1024 resistor taps – 10-bit resolution
- SPI serial interface for write, read, and transfer operations of the potentiometer
- Wiper resistance, 40 Ωtypical at 5V
- Four nonvolatile data registers
- Nonvolatile storage of multiple wiper positions
- Power-on recall, loads saved wiper position on power-up
- Standby current <5µA maximum
- S y s t e m V CC: 2.7V to 5.5V operation
- Analog V+/V-: -5V to +5V
- 100k Ωend-to-end resistance
- 100 year data retention
- Endurance: 100,000 data changes per bit per register
- 1 4 L d T S S O P
- Dual supply version of the X9111
- L o w p o w e r C M O S
- Pb-free (RoHS compliant)
FIGURE 1. FUNCTIONAL DIAGRAM
FN8158 Rev 5.00 Page 2 of 18 October 28, 2016
Applications
Circuit Level Applications
- Vary the gain of a voltage amplifier
- Provide programmable DC refe rence voltages for comparators and detectors
- Control the volume in audio circuits
- Trim out the offset voltage error in a voltage amplifier circuit
- Set the output voltage of a voltage regulator
- Trim the resistance in Wh eatstone bridge circuits
- Control the gain, characteristic frequency and Q-factor in filter circuits
- Set the scale factor and zero point in sensor signal conditioning circuits
- Vary the frequency and duty cycle of timer ICs
- Vary the DC biasing of a pin diode attenuator in RF circuits
- Provide a control variable (I, V, or R) in feedback circuits System Level Applications
- Adjust the contrast in LCD displays
- Control the power level of LED transmitters in communication systems
- Set and regulate the DC biasing point in an RF power amplifier in wireless systems
- Control the gain in audio and home entertainment systems
- Provide the variable DC bias for tuners in RF wireless systems
- Set the operating points in temperature control systems
- Control the operating point for sensors in industrial systems
- Trim offset and gain errors in artificial intelligent systems
Ordering Information
(Notes 2, 3) PART MARKING VCC LIMITS (V) POTENTIOMETER RANGE (kΩ) TEMP RANGE (°C) PACKAGE (RoHS COMPLIANT) PKG. DWG. # X9110TV14Z (Note 1) X9110 TVZ 5 ±10 100 0 to +70 14 Ld TSSOP M14.173 X9110TV14IZ X9110 TVZI -40 to +85 14 Ld TSSOP M14.173 X9110TV14Z-2.7 X9110 TVZF 2.7 to 5.5 0 to +70 14 Ld TSSOP M14.173 X9110TV14IZ-2.7 (Note 1 ) X9110 TVZG -40 to +85 14 Ld TSSOP M14.173 NOTES: 1. Add “T1” suffix for 2.5k unit tape and reel option. 2. These Intersil Pb-free plastic packaged products employ spec ial Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), see product information page for X9110 . For more information on MSL, see tech brief TB363.
this pin. Data is latched by the rising edge of the serial clock. The SCK input is used to clock data into and out of the X9110. HOLD is used in conjunction with the CS pin to select the device. communication, HOLD is brought HIGH, again while SCK is LOW. FIGURE 2. DETAILED FUNCTIONAL DIAGRAM
14 LD TSSOP
1 V+ Analog Supply Voltage
2 SO Serial Data Output
3 A0 Device Address
4 SCK Serial Clock
6 SI Serial Data Input
8 V- Analog Supply Voltage
11 R W Wiper Terminal of the Potentiometer
12 R H High Terminal of the Potentiometer
13 R L Low Terminal of the Potentiometer
14 V CC System Supply Voltage
prior to the start of any operation. voltage limits of the potentiometer. HIGH during the entire operation. three state outputs. This can help to reduce system pin count. FIGURE 3. DETAILED POTENTIOMETER BLOCK DIAGRAM
individual array only one switch may be turned on at a time. and enable, one of 1024 switches. data register zero (DR0) upon power-up. may be different from the value present at power-down. loadings of the DR0 value into the WCR. The potentiometer has four 10-bit nonvolatile Data Registers. WIP: Write In Progress status bit, read only.
- When WIP = 1, indicates that high-voltage write cycle is in progress.
- When WIP = 0, indicates that no high-voltage write cycle is in progress.
TABLE 3. STATUS REGISTER, SR (1-BIT) TABLE 4. IDENTIFICATION BYTE FORMAT TABLE 1. WIPER CONTROL REGISTER , WCR (10-BIT), WCR9–WCR0: Used to store the current wiper position (Volatile, V) TABLE 2. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: Used to store wiper positions or data (Nonvolatile, NV)
FIGURE 4. TWO-BYTE INSTRUCTION SEQUENCE FIGURE 5. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS)
01010 XX X
FIGURE 6. FOUR-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTERS)
TABLE 6. INSTRUCTION SET
110000000 R e a d t h e c o n t e n t s o f t h e W i p e r C o u n t e r
010100000 W r i t e n e w v a l u e t o t h e W i p e r C o u n t e r
checking the WIP bit (read status register).
10000000 XXXXXX W
10100000 XXXXXX W
1010 R B R A 00 XXXXXX W
FN8158 Rev 5.00 Page 9 of 18 October 28, 2016 Write Data Register (DR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Address Wiper Position or Data (Sent by Master on SI) Wiper Position or Data (Sent by Master on SI) CS Rising Edge HIGH-VOLTAGE WRITE CYCLE
010100 A 0
R/ W = 0
1100 R B R A 00XXXXXX W
C R W C R W C R W C R W C R W C R W C R W C R W C R W C R Transfer Data Register (DR) to Wiper Counter Register (WCR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Address CS Rising Edge010100 A 0 R/ W = 1 1100 R B R A 00 Transfer Wiper Counter Register (WCR) to Data Register (DR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Address CS Rising Edge HIGH-VOLTAGE WRITE CYCLE R/ W = 0 1 1 1 0 RB RA 0 0 Read Status Register (SR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Addresses Status Data (Sent by Slave on SO) Status Data (Sent by Slave on SO) CS Rising Edge010100 A 0 R/ W = 1010X0001XXXXXXXX 0000000 W I P NOTES: 4. “A0”: stands for the device address sent by the master. 5. WCRx refers to wiper position data in the Wiper Counter Register 6. “X”: Do not care.
FN8158 Rev 5.00 Page 10 of 18 October 28, 2016 Absolute Maximum Ratings Thermal Information Voltage on SCK any Address Input Thermal Resistance (Typical, Note 7) JA (°C/W) Recommended Operating Conditions Temperature Range Supply Voltage (VCC) Limits (Note 11) CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. NOTE: 7. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Analog Specifications Over recommended industrial (2.7V) operation conditions, unless otherwise stated. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 16)T Y P MAX (Note 16)U N I T RTOTAL End-to-End Resistance 100 k Ω End-to-End Resistance Tolerance ±20 % Power Rating +25°C, each potentiometer 50 mW IW Wiper Current ±3 mA RW Wiper Resistance Wiper current = ±3mA, V CC = 3V 150 500 Ω RW Wiper Resistance I W = ±3mA, VCC = 5V 100 Ω Vv+ Voltage on V+ Pin X9110 ( Note 11) +4.5 +5.5 V Vv- Voltage on V- Pin X9110 ( Note 11) -5.5 -4.5 V VTERM Voltage on any RH or RL Pin V SS = 0V V- V+ V Noise Reference: 1V -120 dBV Resolution 0.1 % Absolute Linearity (Note 8)R w(n)(actual) – Rw(n)(expected), where n = 8 to 1006 ±1 MI ( Note 10) Rw(n)(actual) – Rw(n)(expected) (Note 12)± 1 . 5 M I ( Note 10) Relative Linearity (Note 9)R w(m + 1) – [Rw(m) + MI], where m = 8 to 1006 ±0.5 MI ( Note 10) Rw(m + 1) – [Rw(m) + MI] (Note 12)± 1 M I ( Note 10) Temperature Coefficient of RTOTAL ±300 ppm/°C Ratiometric Temperature Coefficient 20 ppm/°C CH/CL/CW Potentiometer Capacitances See macromodel 10/10/25 pF NOTES: 8. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 9. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 10. MI = RTOT/1023 or (R H – RL)/1023, single pot 11. V CC, V+, V- must reach their final values within 1ms of each other.
FN8158 Rev 5.00 Page 11 of 18 October 28, 2016 DC Operating Specifications Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 16)T Y P MAX (Note 16)U N I T ICC1 VCC Supply Current (active) fSCK = 2.5MHz, SO = Open, VCC = 5.5V Other inputs = VSS 400 µA ICC2 VCC Supply Current (nonvolatile write) fSCK = 2.5MHz, SO = Open, VCC = 5.5V Other inputs = VSS 15m A ISB VCC Current (standby) SCK = SI = V SS, Address = VSS, CS = VCC = 5.5V 5µ A ILI Input Leakage Current V IN = VSS to VCC 10 µA ILO Output Leakage Current V OUT = VSS to VCC 10 µA VIH Input HIGH Voltage V CC x 0.7 V CC + 1 V VIL Input LOW Voltage -1 V CC x 0.3 V VOL Output LOW Voltage I OL = 3mA 0.4 V VOH Output HIGH Voltage I OH = -1mA, VCC ≥ +3V V CC - 0.8 V VOH Output HIGH Voltage I OH = -0.4mA, VCC ≤ +3V V CC - 0.4 V Endurance and Data Retention PARAMETER MIN UNITS Minimum Endurance 100,000 Data changes per bit per register Data Retention 100 years Capacitance SYMBOL TEST TEST CONDITIONS MAX UNIT CIN/OUT (Notes 11, 13) Input/Output Capacitance (SI) V OUT = 0V 8 pF COUT (Note 13) Output Capacitance (SO) V OUT = 0V 8 pF CIN (Note 13) Input Capacitance (A0, CS , WP, HOLD, and SCK) V IN = 0V 6 pF Power-up Timing SYMBOL PARAMETER MIN MAX UNIT tr VCC (Note 13) V CC Power-Up Rate 0.2 50 V/ms tPUR (Notes 13, 14) Power-Up to Initiation of Read Operation 1 ms tPUW (Note 14) Power-Up to Initiation of Write Operation 50 ms NOTES: 13. Limits established by characterization and are not production tested. 14. t PUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. 16. Parts are 100% tested at +25°C. Over-temperature limits es tablished by characterization and are not production tested. AC Test Conditions Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Level V CC x 0.5
FN8158 Rev 5.00 Page 12 of 18 October 28, 2016 Equivalent A.C. Load Circuit 1462Ω 100pF SO RH 10pF CL CL RW RTOTAL CW 25pF 10pF RL SPICE MACRO MODEL 2714Ω 2.7V 1382Ω 100pF SO 1217Ω AC Timing SYMBOL PARAMETER MIN MAX UNIT fSCK SSI/SPI Clock Frequency 2.5 MHz tCYC SSI/SPI Clock Cycle Time 400 ns tWH SSI/SPI Clock High Time 150 ns tWL SSI/SPI Clock Low Time 150 ns tLEAD Lead Time 150 ns tLAG Lag Time 150 ns tSU SI, SCK, HOLD and CS Input Set-Up Time 50 ns tH SI, SCK, HOLD and CS Input Hold Time 50 ns tRI SI, SCK, HOLD and CS Input Rise Time 50 ns tFI SI, SCK, HOLD and CS Input Fall Time 50 ns tDIS SO Output Disable Time 0 500 ns tV SO Output Valid Time 100 ns tHO SO Output Hold Time 0 ns tRO SO Output Rise Time 50 ns tFO SO Output Fall Time 50 ns tHOLD HOLD Time 400 ns tHSU HOLD Set-Up Time 50 ns tHH HOLD Hold Time 50 ns tHZ HOLD Low to Output in High Z 100 ns tLZ HOLD High to Output in Low Z 100 ns TI Noise Suppression Time Constant at SI, SCK, HOLD and CS Inputs 20 ns tCS CS Deselect Time 100 ns tWPASU WP, A0 Set-Up Time 0 ns tWPAH WP, A0 Hold Time 0 ns High-Voltage Write Cycle Timing SYMBOL PARAMETER TYP MAX UNIT tWR High-Voltage Write Cycle Time (store instructions) 5 10 ms
FN8158 Rev 5.00 Page 17 of 18 October 28, 2016 X9110 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005-2016. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. Revision History The revision history provided is for informational purposes only and is believed to be accurate, however, not warranted. Please visit our website to make sure that you have the latest revision. DATE REVISION CHANGE October 28, 2016 FN8158.5 Added Related Literature section on page 1. Updated fSCK maximum specification on page 12. August 3, 2016 FN8158.4 Updated entire datasheet applying Intersil’s new standards. Updated Note 1 and added Note 3. Changed the maximum limit for parameter Vcc Current (standby) ISB from 3µA to 5µA on page 11. Added Revision History and About Intersil sections. Updated POD to latest revision changes are as follows: Updated drawing to remove table and added land pattern.
FN8158 Rev 5.00 Page 18 of 18 October 28, 2016 Package Outline Drawing M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09 DETAIL "X"SIDE VIEW TYPICAL RECOMMENDED LAND PATTERN TOP VIEW B A 814 C PLANE SEATING 0.10 C 0.10 CBA H PIN #1 I.D. MARK 5.00 ±0.10 4.40 ±0.10 0.25 +0.05/-0.06 6.40
0.20 C B A
0.05 0°-8° GAUGE PLANE SEE 0.90 +0.15/-0.10 0.60 ±0.15 0.09-0.20
1.00 REF
0.65
1.20 MAX
0.25
0.05 MIN
0.15 MAX
(1.45) (5.65) (0.65 TYP) (0.35 TYP) DETAIL "X" 1. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation AB-1. NOTES: END VIEW For the most recent package outline drawing, see M14.173.