X80070 RENESAS

Document overview

  • Manufacturer or author: Renesas
  • PDF pages: 14

Technical content

FN8150 Rev 0.00 Page 1 of 14 March 15, 2005 FN8150 Rev 0.00 March 15, 2005 X80070, X80071, X80072, X80073 Hot Swap Controller with Advanced Fault Protection and Voltage Regulator Output DATASHEET

FEATURES

  • Hot swap controller — Overvoltage and undervoltage protection — Undervoltage lockout for battery/redundant supplies — Electronic circuit breaker — Slew Rate for Extern al FET Gate Control — Overcurrent Detection and Gate Shut-off — 3X overcurrent limit on insertion — 5µs overcurrent filter — Hardshort Retry and Indicator — Typically operates from -30V to -80V. Tolerates tran- sients to -200V (limited by external components) — Positive Voltages (low side switching) from 12V to 60V — Soft Re-insertion — Soft extraction
  • Battery backup mode
  • Hardshort retry
  • Overcurrent Filter
  • Insertion Limits.
  • Selectable Gate Current
  • Voltage Regulator Output for Supervisory Functions
  • Debounced manual reset input
  • Available packages — 20-lead Quad No-Lead Frame (QFN)

APPLICATIONS

  • -48V Hot Swap Power Backplane/Distribution Central Office, Ethernet for VOIP
  • Positive Voltage Hotswap 12V to 60V Applications (low side switching)
  • Card Insertion Detection
  • IP Phone Applications
  • Databus Power Interfacing
  • Custom Industrial Power Backplanes
  • Distributed Power Systems

DESCRIPTION

The X80070 is a hot swap controller that allows a board to be safely inserted and removed from a live backplane without turning off the main power supply. During insertion, the gate of an external power MOSFET is clamped low to suppress contact bounce. The undervoltage/overvoltage circuits and the power-on reset circuitry suppress the gate turn on until the mechanical bounce has ended. The X80070 turns on the gate with a slew rate to limit the inrush current and incorporates an electronic circuit breaker set by a sense resistor. After the load is successfully charged, the PWRGD signal is asserted; indicating that the device is ready to power sequence the DC-DC power bricks. At all times, the X80070 monitors for undervoltage, overvoltage, and overcurrent conditions. If any fault occurs, the gate will be immediately shut off and the PWRGD will be returned to the inactive state. The X80070 contains overvoltage, undervoltage and overcurrent detection, hardshort retry, gate control slew rate and power good control. TYPICAL APPLICATION VDD X80070 VUV/OV VEE SENSE UV=43V OV=75V -48V GATE Rs 0.02 182k 1%R5 30k 10k IRFR120 DC-DC Module ON/OFF PWRGD 100 22K 3.3n 100n VRGO IGQ1 IGQ0 Gate Current Select -48V Return *Optional components Depends on choice of DC-DC Module

X80070, X80071, X80072, X80073 FN8150 Rev 0.00 Page 2 of 14 March 15, 2005

ORDERING INFORMATION

Voltage on given pin (Hot Side Functions): V Voltage on given pin (Cold Side Functions): COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS ORDER NUMBER OV (V) UV1 (V) UV2 (V) t NF (us) VOC (mV) VOCI (mV) Over- current Retry Retry Delay (ms) IGATE (uA) TDELAY (ms) tPOR (ms) Temp PART MARK X80070Q20I 74.9 42.4 33.2 5 50 150 Always 100 50 100 100 -40 oC to 85oC 80070I X80071Q20I 68.0 42.4 33.2 5 50 150 Always 100 50 100 100 -40 oC to 85oC 80071I X80072Q20I 74.9 42.4 33.2 5 50 150 5 retries 100 50 100 100 -40 oC to 85oC 80072I X80073Q20I 68.0 42.4 33.2 5 50 150 5 retries 100 50 100 100 -40 oC to 85oC 80073I QFN package (Top view) IGQ1 MR VRGO DNC IGQ0 DNC NA DNC GATE NA VUV/OV SENSE FAR PWRGD BATT-ON VDD DNC DNC DNC VEE 5 678 9 1 0 151617181920 5mm x 5mm Temperature Min. Max. Industrial -40°C +85°C Supply Voltage VDD = 12V

X80070, X80071, X80072, X80073 FN8150 Rev 0.00 Page 3 of 14 March 15, 2005 ELECTRICAL CHARACTERISTICS (Standard Settings) (Over the recommended operating conditions unless otherwise specified). Symbol Parameter Min. Typ. Max. Unit Test Conditions DC Characteristics VDD Supply Operating Range 10 12 14 V IDD Supply Current 2.5 5 mA VRGO Regulated 5V output 4.5 5.5 I RGO = 10uA IRGO VRGO current output 50 µA IGATE Gate Pin Current 46.2 52. 5 58.8 µA Gate Drive On, VGATE = VEE, VSENSE = VEE (sourcing) 9m A V GATE - VEE = 3V VSENSE-VEE = 0.1V (sinking) VGATE External Gate Drive (Slew Rate Con- trol) VDD-1 V DD VI GATE = 50uA VPGA Power Good Threshold (PWRGD High to Low) 0.9 1 1.1 V Referenced to V EE VUV1 < VUV/OV < VOV VIHB Voltage Input High (BATT-ON) V EE + 4 V EE + 5 V VILB Voltage Input Low (BATT-ON) V EE + 2 V ILI Input Leakage Current (MR, IGQ0, IGQ1) 10 µA V IL = GND to VCC ILO Output Leakage Current (PWRGD) 10 µA Gate is Off VIL Input LOW Voltage (MR, IGQ0, IGQ1) -0.5 + V EE (VEE + 5) x 0.3 V VIH Input HIGH Voltage (MR, IGQ0, IGQ1) (V EE + 5) x 0.7 (V EE + 5) + 0.5 V VOL Output LOW Voltage (FAR, PWRGD) VEE + 0.4 V I OL = 4.0 mA (VEE + 2.7 to VEE + 5.5V) IOL = 2.0 mA (VEE + 2.7 to VEE + 3.6V) COUT(1) Output Capacitance (FAR)8 p F V OUT = 0V CIN(1) Input Capacitance (MR) 6 pF V IN = 0V VOC Overcurrent threshold 45 50 55 mV V OC = VSENSE - VEE VOCI Overcurrent threshold (Insertion) 135 150 165 mV V OC = VSENSE - VEE PWRGD = HIGH Initial Power-up condition VOVR Overvoltage threshold (rising) X80070, X80072 X80071, X80073 3.85 3.49 3.90 3.54 3.95 3.59 V Referenced to V EE VOVF Overvoltage threshold (falling) X80070, X80072 X80071, X80073 3.82 3.46 3.87 3.51 3.92 3.56 V Referenced to V EE VUV1R Undervoltage 1 threshold (rising) 2.19 2.24 2.29 V Referenced to V EE BATT-ON = VEEVUV1F Undervoltage 1 threshold (falling) 2.16 2.21 2.26 V VUV2R Undervoltage 2 threshold (rising) 1.71 1.76 1.81 V Referenced to V EE BATT-ON = VRGOVUV2F Undervoltage 2 threshold (falling) 1.68 1.73 1.78 V AC Characteristics tFOC Sense High to Gate Low 1.5 2.5 3.5 s

X80070, X80071, X80072, X80073 FN8150 Rev 0.00 Page 4 of 14 March 15, 2005 Notes: (1) This parameter is based on characterization data. EQUIVALENT A.C. OUTPUT LOAD CIRCUIT A.C. TEST CONDITIONS tFUV Undervoltage conditions to Gate Low 0.5 1.0 1.5 s tFOV Overvoltage Conditions to Gate Low 1.0 1.5 2 s tVFR Overvoltage/undervoltage failure re- covery time to Gate =1V. 1.2 1.6 2 sV DD does not drop below 3V, No other failure conditions. tBATT-ON Delay BATT-ON Valid 100 ns tMR Minimum time high for reset valid on the MR pin 5 s tMRE Delay from MR enable to Gate Pin LOW 1.0 1.6 2.4 sI GATE = 60µA, No Load tMRD Delay from MR disable to GATE reaching 1V 1.8 2.6 sI GATE = 60µA, No Load tQC Delay from IGQ1 and IGQ0 to valid Gate pin current 1 s tSC_RETRY Delay between Retries 90 100 110 ms tNF Noise Filter for Overcurrent 4.5 5 5.5 µs tDPOR Device Delay before Gate assertion 45 50 55 ms Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels VCC x 0.5 Output load Standard output load ELECTRICAL CHARACTERISTICS (Standard Settings) (Continued) (Over the recommended operating conditions unless otherwise specified). Symbol Parameter Min. Typ. Max. Unit Test Conditions 4.6k 30pF FAR PWRGD

X80070, X80071, X80072, X80073 FN8150 Rev 0.00 Page 6 of 14 March 15, 2005 TYPICAL PERFORMANCE CHARACTERISTICS Overcurrent Threshold vs. Temperature Overvoltage Threshold vs. Temperature Undervoltage 1 Threshold vs. Temperature Undervoltage 2 Threshold vs. Temperature IGATE (source) vs. Temperature IGATE (sink) vs. Temperature 46.000 47.000 48.000 49.000 50.000 51.000 52.000 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature Inrush Current Limit (mV) 3.85 3.86 3.87 3.88 3.89 3.90 3.91 3.92 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature Rising Falling OV Threshold (V) 2.190 2.200 2.210 2.220 2.230 2.240 2.250 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature Rising Falling Undervoltage 1 Threshold (V) 1.690 1.700 1.710 1.720 1.730 1.740 1.750 1.760 1.770 1.780 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature Rising Falling Undervoltage 2 Threshold (V) 120 160 200 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature 150µA 70µA 50µA 10µA Gate Current (µA) 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature Gate Current - Sink (mA)

X80070, X80071, X80072, X80073 FN8150 Rev 0.00 Page 7 of 14 March 15, 2005 tFUV vs. Temperature tFOV vs. Temperature tFOC vs. Temperature 0.500 0.550 0.600 0.650 0.700 0.750 0.800 - 5 5 - 4 0 - 2 5 - 1 05 2 0 3 55 06 58 09 5 1 1 0 1 2 5 Temperature tUV1 tUV2 tUV (µs) 1.0 1.1 1.1 1.2 1.2 1.3 1.3 1.4 1.4 - 5 5 - 4 0 - 2 5 - 1 052 03 55 06 5 8 09 5 1 1 0 1 2 5 Temperature tOV (µs) 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature tOC (µs)

Figure 4. Block Diagram

converter can draw huge transient currents as they charge up. backplane input voltage is stable and within tolerance. Figure 5. Typical Inrush with Gate Slew Rate Control BATT-ON and MRH (if needed). 2D N C Pin not used. Do not connect to this pin. 3N A 2 Not Available. Connect to VEE. 4N A 2 Not Available. Connect to VEE. 5V DD Positive Supply Voltage Input. 6V EE Negative Supply Voltage Input. pin detects the overcurrent condition. 10 DNC Pin not used. Do not connect to this pin. 11 DNC Pin not used. Do not connect to this pin. 12 NA1 Not Available. Connect to VRGO. 13 NA1 Not Available. Connect to VRGO. 14 NA2 Not Available. Connect to VEE. 15 FAR Failure After Re-try (FAR) output signal. 18 IGQ1 Gate Current Quick Select Bit 1 Input. 19 IGQ0 Gate Current Quick Select Bit 0 Input.

current provides a controlled slew rate for the FET. the GATE pin current is less than 1 second. Figure 11. Slew Rate (Inrush Current) Control The value of C2 can be selected with the following formula. – there is no overvoltage or no undervoltage condition, (i.e. Table 3. IGQ Gate Current Selection

Figure 12. Power Good Indicator Manual Reset Table 4. Manual Reset (Gate Signal)

1 Operational When MR is HIGH the reset

FN8150 Rev 0.00 Page 14 of 14 March 15, 2005 X80070, X80071, X80072, X80073 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. PACKAGING INFORMATION 20-Lead Quad Flat No Lead Package (Package Code: Q20) 5mm x 5mm Body with 0.65mm Lead Pitch Note: 1. The package outline drawing is com- patilbe with JEDEC MO-220; variations: WHHC-2, except dimensions D2 and E2. 2. The terminal #1 identifier is a laser marked feature Symbols Dimensions in Millimeters Min Nom Max A 0.70 0.75 0.80 A1 0.00 0.02 0.05 b 0.25 0.30 0.35 A3 0.19 0.20 0.25 D 4.90 5.00 5.10 D2 3.70 3.80 3.90 E 4.90 5.00 5.10 E2 3.70 3.80 3.90 e — 0.65 — L 0.35 0.40 0.45 y — 0.08 Pin 1 Indent E D A b e L C y C