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Document overview
- Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 17
Technical content
Features
- 10mA source and sink current capability
- Input voltage range
- 5kV ESD (human body model) Related Literature
- See AN1494, “Reflow and PC Board Assembly Effects on Intersil FGA References”
- See AN1533, “X-Ray Effects on Intersil FGA References”
FIGURE 1. I IN vs VIN (3 UNITS)
3 GND Ground Connection
FIGURE 2. TYPICAL APPLICATION PRECISION 16 TO 24-BIT A/D CONVERTER
16 TO 24-BIT
FN8137 Rev 5.00 Page 3 of 17 September 1, 2015
Ordering Information
(Notes 2, 3) PART MARKING (Note 4) VOUT (V) GRADE (°C) TEMP. RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG # X60003BIG3Z-41T1 (Note 1) APF 4.096 ±1.0mV, 10ppm -40 to +85 3 Ld SOT-23 P3.064 X60003CIG3Z-41T1 (Note 1) APH ±2.5mV, 20ppm -40 to +85 3 Ld SOT-23 P3.064 X60003DIG3Z-41 (No longer available, recommended replacement: X60003BIG3Z-41T1) APJ ±5.0mV, 20ppm -40 to +85 3 Ld SOT-23 P3.064 X60003DIG3Z-41T1 (Note 1) (No longer available, recommended replacement: X60003BIG3Z-41T1) APJ ±5.0mV, 20ppm -40 to +85 3 Ld SOT-23 P3.064 X60003BIG3Z-50T1 (Note 1) APG 5.00 ±1.0mV, 10ppm -40 to +85 3 Ld SOT-23 P3.064 X60003CIG3Z-50T1 (Note 1) API ±2.5mV, 20ppm -40 to +85 3 Ld SOT-23 P3.064 X60003DIG3Z-50T1 (Note 1) APK ±5.0mV, 20ppm -40 to +85 3 Ld SOT-23 P3.064 X60003-EVALZ Evaluation Board NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ spec ial Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for X60003. For more information on MSL please see techbrief TB363. 4. The part marking is located on the bottom of the part
FN8137 Rev 5.00 Page 4 of 17 September 1, 2015 Absolute Voltage Ratings Thermal Information Max Voltage Applied ESD Ratings Environmental Operating Conditions Thermal Resistance (Typical) JA (°C/W) JC (°C/W) Recommended Operating Conditions CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications ar e guaranteed. Typ values are for information purposes only. Unle ss otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA NOTES: 5. Measured with no filtering, distance of 10” from source, intensity set to 55kV and 70mA current, 30s duration. Other exposure levels should be analyzed for Output Voltage drift effects. See “Applications Information” on page 12. 6. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 7. For JC, the “case temp” location is taken at the package top center. 8. Post-reflow drift for the X60003 devices will range from 100µV to 1.0mV based on experimental results with devices on FR4 double sided boards. The design engineer must take this into account when considering the reference voltage after assembly. Electrical Specifications Operating Conditions: IOUT = 0mA, COUT = 0.001µF, TA = -40 to +85°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. SYMBOL PARAMETER CONDITIONS MIN (Note 12) TYP MAX (Note 12) UNITS VOA VOUT Accuracy @ TA = +25°C X60003B -1.0 +1.0 mV X60003C -2.5 +2.5 mV X60003D -5.0 +5.0 mV IIN Supply Current 500 900 nA TC VOUT Output Voltage Temperature Coefficient (Note 9) X60003B 10 ppm/°C X60003C 20 ppm/°C X60003D 20 ppm/°C VN Output Voltage Noise 0.1Hz to 10Hz 30 µV P-P ISC Short Circuit Current T A = +25°C 50 80 mA Electrical Specifications (X60003-41) VIN = 5.0, TA = -40°C to +85°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. SYMBOL PARAMETER CONDITIONS MIN (Note 12) TYP MAX (Note 12) UNITS VIN Input Voltage Range 4.5 9.0 V VOUT Output Voltage 4.096 V VOUT/VIN Line Regulation +4.5V VIN +8.0V 150 µV/V VOUT/IOUT Load Regulation Sourcing: 0mA ISOURCE 10mA 10 50 µV/mA Sinking: -10mA ISINK 0mA 20 100 µV/mA VOUT/TA Thermal Hysteresis (Note 10) T = -40°C to +85°C 150 ppm VOUT/t Long Term Stability (Note 11) T A = +25°C 50 ppm
FN8137 Rev 5.00 Page 5 of 17 September 1, 2015 Electrical Specifications (X60003-50) VIN = 6.5V, TA = -40°C to +85°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. SYMBOL PARAMETER CONDITIONS MIN (Note 12) TYP MAX (Note 12) UNITS VIN Input Voltage Range 5.1 9.0 V VOUT Output Voltage 5.000 V VOUT/VIN Line Regulation +5.5V VIN +8.0V 150 µV/V VOUT/IOUT Load Regulation Sourcing: 0mA ISOURCE 10mA 10 50 µV/mA Sinking: -10mA ISINK 0mA 20 100 µV/mA VDO Dropout Voltage I OUT = 5mA, VOUT = -0.01% 150 300 mV VOUT/TA Thermal Hysteresis (Note 10) T = -40°C to +85°C 100 ppm VOUT/t Long Term Stability (Note 11) T A = +25°C 45 ppm NOTES: 9. Over the specified temperature range. Temperature coefficien t is measured by the box method whereby the change in VOUT is divided by the temperature range; in this case, -40°C to +85°C = +125°C. 10. Thermal Hysteresis is the change of V OUT measured at TA = +25°C after temperature cycling over a specified range, TA. VOUT is read initially at TA = +25°C for the device under test. The device is temperature cycled and a second VOUT measurement is taken at +25°C. The difference between the initial VOUT reading and the second VOUT reading is then expressed in ppm. For TA = +125°C, the device under test is cycled from +25°C to +85°C to -40°C to +85°C. 11. Long term drift is logarithmic in natu re and diminishes over time. Drift after the first 1000 hours will be approximately 10ppm/sqrt(1kHrs). 12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested.
customer-specific voltages are available). 1mV drift from the solder reflow process. up continuously, and after initial stabilization has taken place. essentially presents no load to the battery.
- Data acquisition circuits providing 12 to 24-bits of accuracy
settle to a final value as power-on time may be short. will likewise cause loss of reference accuracy. this may reduce device initial accuracy.
12 TO 24-bit
FIGURE 33. BATTERY-POWERED DATA CONVERTER CIRCUITS
FN8137 Rev 5.00 Page 16 of 17 September 1, 2015 X60003 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005-2017. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support.
FN8137 Rev 5.00 Page 17 of 17 September 1, 2015 Package Outline Drawing P3.064
3 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE (SOT23-3)
Rev 3, 3/12 Reference JEDEC TO-236. Footlength is measured at reference to gauge plane. Dimension does not include interlead flash or protrusions. Dimensioning and tolerancing conform to AMSEY14.5m-1994. Dimensions are in millimeters.1. NOTES: DETAIL "A"SIDE VIEW TYPICAL RECOMMENDED LAND PATTERN TOP VIEW C 0.10 C
0.20 M C
LC 1.30±0.10 CL 0.950 2.37±0.27 2.92±0.12 4 10° TYP (2 plcs) 0.013(MIN) 0.100(MAX) SEATING PLANE 1.00±0.12 0.95±0.07 SEATING PLANE GAUGE PLANE 0.25 0.38±0.10 DETAIL "A" 0.435±0.065 0 - 8 deg. (2.15) (1.25) (0.60) (0.95 typ.) 0.085 - 0.19 Dimensions in ( ) for Reference Only. Interlead flash or protrusions shall not exceed 0.25mm per side.(0.4 RAD TYP.)