X40010

X40010 INTERSIL

Document overview

• PDF pages: 24

Technical content

Page 1

®

Dual Voltage Monitor with Integrated CPU

Supervisor

FEATURES

• Dual voltage detection and reset assertion —Standard reset threshold settings See Selection table on page 2.

—Adjust low voltage reset threshold voltages using special programming sequence —Reset signal valid to VCC = 1V —Monitor three voltages or detect power fail

• Independent Core Voltage Monitor (V2MON)
• Fault detection register
• Selectable power on reset timeout (0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval (25ms, 200ms,1.4s, off)
• Low power CMOS —25µA typical standby current, watchdog on —6µA typical standby current, watchdog off
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages —8-lead SOIC, TSSOP
• Monitor Voltages: 5V to 0.9V
• Independent Core Voltage Monitor

BLOCK DIAGRAM

APPLICATIONS

• Communication Equipment —Routers, Hubs, Switches —Disk Arrays, Network Storage
• Industrial Systems —Process Control —Intelligent Instrumentation
• Computer Systems —Computers —Network Servers

DESCRIPTION

The X40010/11/14/15 combines power-on reset control, watchdog timer, supply voltage supervision, and secondary voltage supervision, in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying voltage to VCC activates the power on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and system oscillator to stabilize before the processor can execute code.

(V1MON)

V2MON

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

Page 2

Low VCC detection circuitry protects the user’s system from low voltage conditions, resetting the system when VCC falls below the minimum VTRIP1 point. RESET/RESET is active until VCC returns to proper operating level and stabilizes. A second voltage monitor circuit tracks the unregulated supply to provide a power fail warning or monitors different power supply voltage. Three common low voltage combinations are available, however, Intersil’s unique circuits allows the threshold for either voltage monitor to be reprogrammed to meet special needs or to fine-tune the threshold for applications requiring higher precision.

Dual Voltage Monitors

The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the WDO signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device features a 2-wire interface and software protocol allowing operation on an I2C® bus.

Table 1:

\*Voltage monitor requires VCC to operation. Others are independent of VCC.

PIN CONFIGURATION

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PIN DESCRIPTION (Continued)

PRINCIPLES OF OPERATION

Power On Reset Application of power to the X40010/11/14/15 activates a Power On Reset Circuit that pulls the RESET/RESET pins active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. – It prevents the processor from operating prior to stabilization of the oscillator. – It allows time for an FPGA to download its configuration prior to initialization of the circuit. – It prevents communication to the EEPROM, greatly reducing the likelihood of data corruption on power up. When VCC exceeds the device VTRIP1 threshold value for tPURST (selectable) the circuit releases the RESET (X40011) and RESET (X40010) pin allowing the system

to begin operation.

Low Voltage VCC (V1 Monitoring) During operation, the X40010/11/14/15 monitors the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum

VTRIP1. The

RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The V1FAIL signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP1 for tPURST.

Low Voltage V2 Monitoring The X40010/11/14/15 also monitors a second voltage level and asserts V2FAIL if the voltage falls below a preset minimum VTRIP2. The V2FAIL signal is either ORed with RESET to prevent the microprocessor from operating in a power fail or brownout condition or used to interrupt the microprocessor with notification of an impending power failure. For the X40010/11 the V2FAIL signal remains active until the VCC drops below 1V (VCC falling). It also remains active until V2MON returns and exceeds VTRIP2 by 0.2V. This voltage sense circuitry monitors the power supply connected to the V2MON pin. If VCC = 0, V2MON can still be monitored.

For the X40014/15 devices, the V2FAIL signal remains actice until VCC drops below 1Vx and remains active until V2MON returns and exceeds VTRIP2. This sense circuitry is powered by VCC. If VCC = 0, V2MON cannot be monitored.

Figure 1. Two Uses of Multiple Voltage Monitoring

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Figure 2. VTRIPX Set/Reset Conditions

VTRIPX

(X = 1, 2)

VCC/V2MON

WDO

7

0

0

SCL

SDA

A0h

WATCHDOG TIMER

The Watchdog Timer circuit monitors the microprocessor activity by monitoring the SDA and SCL pins. The microprocessor must toggle the SDA pin HIGH to LOW periodically, while SCL also toggles from HIGH to LOW (this is a start bit) followed by a stop condition prior to the expiration of the watchdog time out period to prevent a WDO signal going active. The state of two nonvolatile control bits in the Status Register determines the watchdog timer period. The microprocessor can change these watchdog bits by writing to the X40010/11/14/15 control register (also refer to page 19).

Figure 3. Watchdog Restart

V1 AND V2 THRESHOLD PROGRAM PROCEDURE

(OPTIONAL)

The X40010/11/14/15is shipped with standard V1 and V2 threshold (VTRIP1, VTRIP2) voltages. These values will not change over normal operating and storage conditions. However, in applications where the standard thresholds are not exactly right, or if higher precision is needed in the threshold value, the X40010/11/14/15trip points may be adjusted. The procedure is described below, and uses the application of a high voltage control signal.

VP

7 0

7

tWC

00h

Setting a VTRIPx Voltage (x = 1, 2) There are two procedures used to set the threshold voltages (VTRIPx), depending if the threshold voltage to be stored is higher or lower than the present value. For example, if the present VTRIPx is 2.9 V and the new VTRIPx is 3.2 V, the new voltage can be stored directly into the VTRIPx cell. If however, the new setting is to be lower than the present setting, then it is necessary to “reset” the VTRIPx voltage before setting the new value.

Setting a Higher VTRIPx Voltage (x = 1, 2) To set a VTRIPx threshold to a new voltage which is higher than the present threshold, the user must apply the desired VTRIPx threshold voltage to the corresponding input pin Vcc(V1MON), or V2MON. The Vcc(V1MON) and V2MON must be tied together during this sequence. Then, a programming voltage (Vp) must be applied to the WDO pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h, followed by the Byte Address 01h for VTRIP1 and 09h for VTRIP2, and a 00h Data Byte in order to program VTRIPx. The STOP bit following a valid write operation initiates the programming sequence. Pin WDO must then be brought LOW to

complete the operation. Note: This operation does not corrupt the memory array.

Setting a Lower VTRIPx Voltage (x = 1, 2) In order to set VTRIPx to a lower voltage than the present value, then VTRIPx must first be “reset” according to the procedure described below. Once VTRIPx has been “reset”, then VTRIPx can be set to the desired voltage using the procedure described in “Setting a Higher VTRIPx Voltage”.

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Resetting the VTRIPx Voltage To reset a VTRIPx voltage, apply the programming voltage (Vp) to the WDO pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h followed by the Byte Address 03h for VTRIP1 and 0Bh for VTRIP2, followed by 00h for the Data Byte in order to reset VTRIPx. The STOP bit following a valid write operation initiates the programming sequence. Pin WDO must then be brought LOW to complete the operation. After being reset, the value of VTRIPx becomes a nominal value of 1.7V or lesser. Note: This operation does not corrupt the memory array.

CONTROL REGISTER

The Control Register provides the user a mechanism for changing the Block Lock and Watchdog Timer settings. The Block Lock and Watchdog Timer bits are nonvolatile and do not change when power is removed. The Control Register is accessed with a special preamble in the slave byte (1011) and is located at address 1FFh. It can only be modified by performing a byte write operation directly to the address of the register and only

Figure 4. Sample VTRIP Reset Circuit

one data byte is allowed for each register write operation. Prior to writing to the Control Register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps. See "Writing to the Control Registers" on page 7. The user must issue a stop, after sending this byte to the register, to initiate the nonvolatile cycle that stores WD1, WD0, PUP1, PUP0, BP1, and BP0. The X40010/11/14/15 will not acknowledge any data bytes written after the first byte is entered. The state of the Control Register can be read at any time by performing a random read at address 01Fh, using the special preamble. Only one byte is read by each register read operation. The master should sup-

ply a stop condition to be consistent with the bus protocol, but a stop is not required to end this operation.

RWEL: Register Write Enable Latch (Volatile) The RWEL bit must be set to “1” prior to a write to the Control Register.

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Figure 5. VTRIPX Set/Reset Sequence (X = 1, 2)

WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the memory and to

the Register during a write operation. This bit is a vola-

tile latch that powers up in the LOW (disabled) state.

While the WEL bit is LOW, writes to any address,

including any control registers will be ignored (no

acknowledge will be issued after the Data Byte). The

WEL bit is set by writing a “1” to the WEL bit and zeros

to the other bits of the control register.

Once set, WEL remains set until either it is reset to 0

(by writing a “0” to the WEL bit and zeros to the other

bits of the control register) or until the part powers up

again. Writes to the WEL bit do not cause a high volt-

age write cycle, so the device is ready for the next

operation immediately after the stop condition.

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PUP1, PUP0: Power Up Bits (Nonvolatile) The Power Up bits, PUP1 and PUP0, determine the tPURST time delay. The nominal power up times are shown in the following table.

WD1, WD0: Watchdog Timer Bits (Nonvolatile) The bits WD1 and WD0 control the period of the Watchdog Timer. The options are shown below.

Writing to the Control Registers Changing any of the nonvolatile bits of the control and trickle registers requires the following steps: – Write a 02H to the Control Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceded by a start and ended with a stop). – Write a 06H to the Control Register to set the Register Write Enable Latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation proceeded by a start and ended with a stop). – Write a one byte value to the Control Register that has all the control bits set to the desired state. The

Control register can be represented as qxys 001r in binary, where xy are the WD bits, s isthe BP bit and qr are the power up bits. This operation proceeded by a start and ended with a stop bit. Since this is a nonvolatile write cycle it will take up to 10ms to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to ‘1’ in this third step (qxys 011r) then the RWEL bit is set, but the WD1, WD0, PUP1, PUP0, and BP bits remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and returns a NACK.

– A read operation occurring between any of the previous operations will not interrupt the register write operation. – The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. To illustrate, a sequence of writes to the device consisting of [02H, 06H, 02H] will reset all of the nonvolatile bits in the Control Register to 0. A sequence of [02H, 06H, 06H] will leave the nonvolatile bits unchanged and the RWEL bit remains set.

FAULT DETECTION REGISTER

The Fault Detection Register (FDR) provides the user the status of what causes the system reset active. The Manual Reset Fail, Watchdog Timer Fail and three Low Voltage Fail bits are volatile.

The FDR is accessed with a special preamble in the slave byte (1011) and is located at address 0FFh. It can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. There is no need to set the WEL or RWEL in the control register to access this fault detection register.

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Figure 6. Valid Data Changes on the SDA Bus

SCL

SDA

Data Stable

At power-up, the Fault Detection Register is defaulted to all “0”. The system needs to initialize this register to all “1” before the actual monitoring take place. In the event of any one of the monitored sources failed. The corresponding bits in the register will change from a “1” to a “0” to indicate the failure. At this moment, the system should perform a read to the register and noted the cause of the reset. After reading the register the system should reset the register back to all “1” again. The state of the Fault Detection Register can be read at any time by performing a random read at address 0FFh, using the special preamble. The FDR can be read by performing a random read at

OFFh address of the register at any time. Only one byte of data is read by the register read operation.

WDF, Watchdog Timer Fail Bit (Volatile) The WDF bit will set to “0” when the WDO goes active.

LV1F, Low VCC Reset Fail Bit (Volatile) The LV1F bit will be set to “0” when VCC (V1MON) falls below VTRIP1.

LV2F, Low V2MON Reset Fail Bit (Volatile) The LV2F bit will be set to “0” when V2MON falls below VTRIP2.

Data Change

Data Stable

SERIAL INTERFACE

Interface Conventions The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the devices in this family operate as slaves in all applications.

Serial Clock and Data Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 6.

Serial Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. See Figure 6.

Serial Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the Standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. See Figure 6.

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Figure 7. Valid Start and Stop Conditions

SCL

SDA

Serial Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. See Figure 8. The device will respond with an acknowledge after recognition of a start condition and if the correct Device Identifier and Select bits are contained in the Slave Address Byte. If a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. The device will acknowledge all incoming data and address bytes,

except for the Slave Address Byte when the Device Identifier and/or Select bits are incorrect. In the read mode, the device will transmit eight bits of data, release the SDA line, then monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. The device will terminate further data transmissions if an acknowledge is not

Figure 8. Acknowledge Response From Receiver

detected. The master must then issue a stop condition to return the device to Standby mode and place the device into a known state.

Serial Write Operations

Byte Write For a write operation, the device requires the Slave Address Byte and a Word Address Byte. This gives the master access to any one of the words in the array. After receipt of the Word Address Byte, the device responds with an acknowledge, and awaits the next eight bits of data. After receiving the 8 bits of the Data Byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. During this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. The SDA output is at high

impedance. See Figure 9. A write to a protected block of memory will suppress the acknowledge bit.

SCL from Master

Data Output from

Data Output from Receiver

Start

Acknowledge

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Read Operation Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a “dummy” write operation. The master issues the start condition and the Slave Address Byte, receives an acknowledge, then issues the Word Address Bytes. After acknowledging receipts of the Word Address Bytes, the master immedi-

Figure 9. Read Sequence

ately issues another start condition and the Slave Address Byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the eight bit word. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. See Figure 12 for the address, acknowledge, and data transfer sequence.

Signals from the Master

SDA Bus

A

Signals from

C K

the Slave

Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write. The contents of the array will not be effected.

Acknowledge Polling The disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. Once the stop condition is issued to indicate the end of the master’s byte load operation, the device initiates the internal high voltage cycle. Acknowledge polling can be initiated immediately. To do this, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the high voltage cycle then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation.

See Figure 12.

A

A

C

C

Data K

K

Serial Read Operations Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the Slave Address Byte is set to one. There are three basic read operations: Current Address Reads, Random Reads, and Sequential Reads.

Current Address Read Internally the device contains an address counter that maintains the address of the last word read incremented by one. Therefore, if the last read was to address n, the next read operation would access data from address n+1. On power up, the address of the address counter is undefined, requiring a read or write operation for initialization. Upon receipt of the Slave Address Byte with the R/W bit set to one, the device issues an acknowledge and then transmits the eight bits of the Data Byte. The master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. See Figure 13 for the

address, acknowledge, and data transfer sequence.

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Figure 10. Acknowledge Polling Sequence

It should be noted that the ninth clock cycle of the read operation is not a “don’t care.” To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition.

Random Read Random read operation allows the master to access any memory location in the array. Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a “dummy” write operation. The master issues the start condition and the Slave Address Byte, receives an acknowledge, then issues the Word Address Bytes. After acknowledging receipts of the Word Address Bytes, the master immediately issues another start condition and the Slave Address Byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the eight bit word. The master terminates the read operation by not responding with an acknowledge

and then issuing a stop condition. See Figure 14 for the address, acknowledge, and data transfer sequence.

A similar operation called “Set Current Address” where the device will perform this operation if a stop is issued instead of the second start shown in Figure 13. The device will go into standby mode after the stop and all bus activity will be ignored until a start is detected. This operation loads the new address into the address counter. The next Current Address Read operation will read from the newly loaded address. This operation could be useful if the master knows the next address it needs to read, but is not ready for the data.

Sequential Read Sequential reads can be initiated as either a current address read or random address read. The first Data Byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indicating it requires additional data. The device continues to output data for each acknowledge received. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. The data output is sequential, with the data from address n followed by the data from address n + 1. The address counter for read operations increments through all page and column addresses, allowing the entire memory contents to be serially read during one opera-

tion. At the end of the address space the counter “rolls over” to address 0000H and the device continues to output data for each acknowledge received. See Figure 15 for the acknowledge and data transfer sequence.

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SERIAL DEVICE ADDRESSING

Memory Address Map CR, Control Register, CR7: CR0 Address: 1FFhex FDR, Fault DetectionRegister, FDR7: FDR0 Address: 0FFhex

Slave Address Byte Following a start condition, the master must output a Slave Address Byte. This byte consists of several parts: – a device type identifier that is always ‘101x’. Where x=0 is for Array, x=1 is for Control Register or Fault Detection Register. – next two bits are ‘0’. – next bit that becomes the MSB of the address.

Figure 12. Current Address Read Sequence

S Slave t

Signals from

a Address

the Master

r t

SDA Bus

1 0 1 0 0 0

Signals from the Slave

Figure 13. Random Address Read Sequence

– One bit of the slave command byte is a R/W bit. The R/W bit of the Slave Address Byte defines the operation to be performed. When the R/W bit is a one, then a read operation is selected. A zero selects a write operation.

Figure 11. X40010/11/14/15 Addressing

Slave Byte

Control Register

Fault Detection Register

Word Address

Control Register

Fault Detection Register

S t o p

1

Data

Signals from the Master

SDA Bus

A

A

A

Signals from

C

C

C

Data K

K

K

the Slave

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Word Address The word address is either supplied by the master or obtained from an internal counter. The internal counter is undefined on a power up condition.

Operational Notes The device powers-up in the following state: – The device is in the low power standby state. – The WEL bit is set to ‘0’. In this state it is not possible to write to the device. – SDA pin is the input mode. – RESET/RESET Signal is active for tPURST.

Figure 14. Sequential Read Sequence

Slave

Signals from

Data Protection The following circuitry has been included to prevent inadvertent writes: – The WEL bit must be set to allow write operations. – The proper clock count and bit sequence is required prior to the stop bit in order to start a nonvolatile write cycle. – A three step sequence is required before writing into the Control Register to change Watchdog Timer or Block Lock settings.

S t

the Master

SDA Bus

Signals from the Slave

(n is any integer greater than 1)

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ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................... -65°C to +135°C Storage temperature ......................... -65°C to +150°C Voltage on any pin with respect to VSS ...................................... -1.0V to +7V D.C. output current ...............................................5mA Lead temperature (soldering, 10 seconds)........ 300°C

RECOMMENDED OPERATING CONDITIONS

D.C. OPERATING CHARACTERISTICS

COMMENT

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 2:

X40010/11-C

2 7V to 5 5V

1V to 3 6V

(Over the recommended operating conditions unless otherwise specified)

Page 15

D.C. OPERATING CHARACTERISTICS (Continued) (Over the recommended operating conditions unless otherwise specified)

Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte. (3) VIL Min. and VIH Max. are for reference only and are not tested. (4) At 25°C, VCC = 5V. (5) See Ordering Information for standard programming levels. For custom programmed levels, contact factory.

(6) Based on characterization data.

EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2)

∆V = 100mV

VxMON

∆V

Vref

Output Pin

CAPACITANCE

Note: (1) This parameter is not 100% tested.

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SYMBOL TABLE

EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR

VCC = 5V

A.C. TEST CONDITIONS

Page 17

A.C. CHARACTERISTICS

Note: (1) Cb = total capacitance of one bus line in pF.

TIMING DIAGRAMS

Bus Timing

tHIGH tLOW

tR

tF

SCL

SDA IN

SDA OUT

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Write Cycle Timing

SCL

SDA

Stop

Start

Condition

Condition

Nonvolatile Write Cycle Timing

Note: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

Power Fail Timings

VTRIPX [ VCC or V2MON

[ LOWLINE or V2FAIL or V3FAIL

X = 2, 3

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RESET/RESET Timings

LOW VOLTAGE AND WATCHDOG TIMING PARAMETERS

Notes: (1) VCC = 5V at 25°C. (2) Values based on characterization data only.

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Watchdog Time Out For 2-Wire Interface

Start

Start

Minimum Sequence to Reset WDT

SCL

SDA

VTRIPX Set/Reset Conditions

resets VTRIP1

01h\*

03h\*

sets VTRIP1

0Bh\* resets VTRIP2

09h\* sets VTRIP2 \* all others reserved

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VTRIP1, VTRIP2, Programming Specifications: VCC = 2.0-5.5V; Temperature = 25°C

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PACKAGING INFORMATION

8-Lead Plastic, SOIC, Package Code S8

Pin 1 Index

0.014 (0.35) 0.019 (0.49)

(4X) 7°

0.0075 (0.19) 0.010 (0.25)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

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PACKAGING INFORMATION

8-Lead Plastic, TSSOP, Package Code V8

Gage Plane

0° - 8°

Seating Plane

(4.16) (7.72)

Detail A (20X)

(1.78)

(0.42)

(0.65)

All Measurements Are Typical

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

Page 24

ORDERING INFORMATION

PART MARK INFORMATION

8-Lead Package

Package - S/V A, B, or C

I – Industrial Blank – Commercial

WW – Workweek YY – Year

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com