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FN8097 Rev 3.00 Page 1 of 22 May 2, 2006 FN8097 Rev 3.00 May 2, 2006 X1205 2-Wire™ RTC Real Time Clock/Calendar DATASHEET
FEATURES
- Real Time Clock/Calendar —Tracks time in Hours, Minutes, and Seconds —Day of the Week, Day, Month, and Year
- 2 Polled Alarms (Non-volatile) —Settable on the Second, Minute, Hour, Day of the Week, Day, or Month —Repeat Mode (periodic interrupts)
- Oscillator Compensation on Chip —Internal Feedback Resistor and Compensation Capacitors —64 Position Digitally Controlled Trim Capacitor —6 Digital Frequency Adjustment Settings to ±30ppm
- Battery Switch or Super Cap Input
- 2-Wire™ Interface Interoperable with I 2C* —400kHz Data Transfer Rate
- Low Power CMOS —1.25µA Operating Current (Typical)
- Small Package Options —8 Ld SOIC and 8 Ld TSSOP
- Repetitive Alarms
- Temperature Compensation
- Pb-Free Plus Anneal Available (RoHS Compliant)
APPLICATIONS
- Utility Meters
- HVAC Equipment
- Audio/Video Components
- Set Top Box/Television
- M o d e m s
- Network Routers, Hubs, Switches, Bridges
- Cellular Infrastructure Equipment
- Fixed Broadband Wireless Equipment
- Pagers/PDA
- POS Equipment
- Test Meters/Fixtures
- Office Automation (Copiers, Fax)
- Home Appliances
- Computer Products
- Other Industrial/Medical/Automotive
DESCRIPTION
The X1205 device is a Real Time Clock with clock/calendar, two pol led alarms, oscillator compensation, and battery backup switch. The oscillator uses an external, low-cost 32.768kHz crystal. All compensation and trim components are integrated on the chip. This eliminates several external discrete components and a trim capacitor, saving board area and component cost. The Real-Time Clock keeps track of time with separate registers for Hours, Minutes, and Seconds. The Calendar has separate registers for Date, Month, Year and Day-of-week. The calendar is correct through 2099, with automatic leap year correction. BLOCK DIAGRAM Oscillator Frequency Timer LogicDivider Calendar 32.768kHz Control Registers 1Hz Time Keeping Registers Alarm Regs Compare Mask IRQ Control Decode Logic Alarm (EEPROM) (EEPROM)SCL SDA Serial Interface Decoder Interrupt Enable Registers Status (SRAM) Alarm Alarm (SRAM) OSC Compensation
FN8097 Rev 3.00 Page 2 of 22 May 2, 2006 PIN DESCRIPTIONS PIN ASSIGNMENTS NC = No internal connection VBACK VCC IRQ SCL SDA VSS
8 Ld TSSOP
8 Ld SOIC
Ordering Information
PART NUMBER PART MARKING V CC RANGE (V) TEMP RANGE (°C) PACKAGE PKG. DWG. # X1205S8* X1205 2.7 to 5.5 0 to 70 8 Ld SOIC (150 mil) MDP0027 X1205S8Z* (Note) X1205 Z 0 to 70 8 Ld SOIC (150 mil) (Pb Free) MDP0 027 X1205S8I* X1205 I -40 to 85 8 Ld SOIC (150 mil) MDP0027 X1205S8IZ* (Note) X1205 Z I -40 to 85 8 Ld SOIC (150 mil) (Pb Free ) MDP0027 X1205V8* 1205 0 to 70 8 Ld TSSOP (4.4mm) M8.173 X1205V8Z* (Note) 1205 Z 0 to 70 8 Ld TSSOP (4.4mm) (Pb-free) M8.173 X1205V8I* 1205I -40 to 85 8 Ld TSSOP (4.4mm) M8.173 X1205V8IZ* (Note) 1205I Z -40 to 85 8 Ld TSSOP (4.4mm) (Pb-free) M8 .173 *Add “T1” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pin Number Symbol Brief DescriptionSOIC TSSOP 13 X 1 X1. The X1 pin is the input of an inverting amplifier and should be connected to one pin of a 32.768kHz quartz crystal. 24 X 2 X2. The X2 pin is the output of an inverting amplifier and should be connected to one pin of a 32.768kHz quartz crystal. 35 I R Q Interrupt Output – IRQ. This is an interrupt signal output. This signal notifies a host proces- sor that an alarm has occurred and requests action. It is an open drain active low output. 46 V SS VSS. 57 S D A Serial Data (SDA). SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. 68 S C L Serial Clock (SCL). The SCL input is used to clock all data into and out of the device. 71 V BACK VBACK. This input provides a backup supply voltage to the device. VBACK supplies power to the device in the event the VCC supply fails. This pin can be connected to a battery, a Supercap or tied to ground if not used. 82 V CC VCC.
FN8097 Rev 3.00 Page 3 of 22 May 2, 2006 ABSOLUTE MAXIMUM RATINGS Voltage on V CC, VBACK and IRQ Voltage on SCL, SDA, X1 and X2 above V CC or VBACK (whichever is higher) Stresses above those liste d under “Absolute Maximum Ratings” may cause perman ent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifi- cation is not implied. Exposure to absolute maximum rat- ing conditions for extended periods may affect device reliability. DC OPERATING CHARACTERISTICS (Temperature = -40°C to +85°C, unless otherwise stated.) OPERATING CHARACTERISTICS Symbol Parameter Conditions Min Typ Max Unit Notes VCC Main Power Supply 2.7 5.5 V VBACK Backup Power Supply 1.8 5.5 V VCB Switch to Backup Supply V BACK -0.2 V BACK -0.1 V VBC Switch to Main Supply V BACK VBACK +0.2 V Symbol Parameter Conditions Min Typ Max Unit Notes ICC1 Read Active Supply Current VCC = 2.7V 400 µA 1, 5, 7, 14 VCC = 5.0V 800 µA ICC2 Program Supply Current (nonvolatile) VCC = 2.7V 2.5 mA 2, 5, 7, 14 VCC = 5.0V 3.0 mA ICC3 Main Timekeeping Current VCC = 2.7V 10 µA 3, 7, 8, 14, 15 VCC = 5.0V 20 µA IBACK Timekeeping Current V BACK = 1.8V 1.25 µA 3, 6, 9, 14, 15 “See Perfor- mance Data”VBACK = 3.3V 1.5 µA ILI Input Leakage Current 10 µA 10 ILO Output Leakage Current 10 µA 10 VIL Input LOW Voltage -0.5 V CC x 0.2 or VBACK x 0.2 V1 3 VIH Input HIGH Voltage V CC x 0.7 or VBACK x 0.7 VCC + 0.5 or VBACK + 0.5 V1 3 VHYS Schmitt Trigger Input Hysteresis VCC related level .05 x V CC or .05 x VBACK V1 3 VOL Output LOW Voltage for SDA/IRQ VCC = 2.7V 0.4 V 11 VCC = 5.5V 0.4
Byte are incorrect or until 200nS after a stop ending a read or write operation. (2) The device enters the Program state 200nS after a stop ending a write operation and continues for tWC. (4) For reference only and not tested. (13)Threshold voltages based on the higher of Vcc or Vback. (14)Using recommended crystal and oscillator network applied to X1 and X2 (25°C). Notes: (1) This parameter is not 100% tested. Figure 1. Standard Output Load for testing the device with VCC = 5.0V
FN8097 Rev 3.00 Page 5 of 22 May 2, 2006 AC Specifications (TA = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.) Notes: (1) This parameter is not 100% tested. (2) Cb = total capacitance of one bus line in pF. TIMING DIAGRAMS Bus Timing Symbol Parameter Min. Max. Units fSCL SCL Clock Frequency 400 kHz tIN Pulse width Suppression Time at inputs 50 (1) ns tAA SCL LOW to SDA Data Out Valid 0.9 s tBUF Time the bus must be free before a new transmission can start 1.3 s tLOW Clock LOW Time 1.3 s tHIGH Clock HIGH Time 0.6 s tSU:STA Start Condition Setup Time 0.6 s tHD:STA Start Condition Hold Time 0.6 s tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 s tSU:STO Stop Condition Setup Time 0.6 s tDH Data Output Hold Time 50 ns tR SDA and SCL Rise Time 20 +.1Cb (1)(2) 300 ns tF SDA and SCL Fall Time 20 +.1Cb (1)(2) 300 ns Cb Capacitive load for each bus line 400 pF tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DATSCL SDA IN SDA OUT tF tLOW tBUFtAA tR
FN8097 Rev 3.00 Page 6 of 22 May 2, 2006 Write Cycle Timing Power-up Timing Notes: (1) Delays are measured from the time V CC is stable until the specified operation can be initiated. These parameters are not 100% tested. VCC slew rate should be between 0.2mV/µsec and 50mV/µsec. (2) Typical values are for T A = 25°C and VCC = 5.0V Nonvolatile Write Cycle Timing Note: (1) t WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. Symbol Parameter Min. Typ. (2) Max. Units tPUR(1) Time from Power-up to Read 1 ms tPUW(1) Time from Power-up to Write 5 ms Symbol Parameter Min. Typ. (1) Max. Units tWC(1) Write Cycle Time 5 10 ms SCL SDA tWC 8th Bit of Last Byte ACK Stop Condition Start Condition
FN8097 Rev 3.00 Page 8 of 22 May 2, 2006 prior to RTC data output) into a separate latch to avoid time changes during the read operation. The clock continues to run. Alarms occurring during a read are unaffected by the read operation. Writing to the Real Time Clock The time and date may be set by writing to the RTC reg- isters. To avoid changing the current time by an uncom- pleted write operation, the current time value is loaded into a separate buffer at th e falling edge of the clock on the ACK bit before the RTC da ta input bytes, the clock continues to run. The new serial input data replaces the values in the buffer. This new RTC value is loaded back into the RTC Register by a stop bit at the end of a valid write sequence. An invalid write operation aborts the time update procedure and the contents of the buffer are discarded. After a valid write operation the RTC will reflect the newly loaded data beginning with the next “one second clock cycle” after the stop bit is written. The RTC continues to update the time while an RTC register write is in progress and the RTC continues to run during any nonvolatile write sequences. A single byte may be written to the RTC without affecting the other bytes. Accuracy of the Real Time Clock The accuracy of the Real Time Clock depends on the frequency of the quartz crystal that is used as the time base for the RTC. Since the resonant frequency of a crystal is temperature dependent, the RTC perfor-mance will also be dependent upon temperature. The frequency deviation of the crystal is a function of the turnover temperature of the crystal from the crystal’s nominal frequency. For example, a >20ppm frequency deviation translates into an accuracy of >1 minute per month. These parameters are available from the crystal manufacturer. Intersil’s RTC family provides on-chip crystal compensation ne tworks to adjust load- capacitance to tune oscillator frequency from +116 ppm to -37 ppm when using a 12.5 pF load crystal. For more detail information see the Application section. CLOCK/CONTROL REGISTERS (CCR) The Control/Clock Registers are located in an area accessible following a slave byte of “1101111x” and reads or writes to addre sses [0000h:003Fh]. The clock/control memory map has memory addresses from 0000h to 003Fh. The defined addresses are described in the Table 1. Writing to and reading from the undefined addresses are not recommended. CCR access The contents of the CCR can be modified by performing a byte or a page write operation directly to any address in the CCR. Prior to writin g to the CCR (except the sta- tus register), however, the WEL and RWEL bits must be set using a two step process (See section “Writing to the Clock/Control Registers.”) The CCR is divided into 5 sections. These are: 1. Alarm 0 (8 bytes; non-volatile) 2. Alarm 1 (8 bytes; non-volatile) 3. Control (4 bytes; non-volatile) 4. Real Time Clock (8 bytes; volatile) 5. Status (1 byte; volatile) Each register is read and written through buffers. The non- volatile portion (or the counter portion of the RTC) is updated only if RWEL is set and only after a valid write operation and stop bit. A sequential read or page write operation provides access to the contents of only one sec- tion of the CCR per operation. Access to another section requires a new operation. Continued reads or writes, once reaching the end of a section, will wrap around to the start of the section. A read or write can begin at any address in the CCR. It is not necessary to set the RWEL bit prior to writing the status register. Section 5 su pports a single byte read or write only. Continued reads or writes from this section terminates the operation. The state of the CCR can be read by performing a ran- dom read at any address in the CCR at any time. This returns the contents of that register location. Additional registers are read by performing a sequential read. The read instruction latches all Clock registers into a buffer, so an update of the clock does not change the time being read. A sequential read of the CCR will not result in the output of data from the memory array. At the end of a read, the master supplies a stop condition to end the operation and free the bus. After a read of the CCR, the address remains at the previous address +1 so the user can execute a current address read of the CCR and con- tinue reading the next Register. ALARM REGISTERS There are two alarm registers whose contents mimic the contents of the RTC register, but add enable bits and exclude the 24 hour time selection bit. The enable bits specify which registers to use in the comparison between the Alarm and Real Time Registers. For example: – Setting the Enable Month Bit (EMOn*) bit in combina- tion with other enable bits and a specific alarm time, the user can establish an alarm that triggers at the same time once a year. *n = 0 for Alarm 0: N = 1 for Alarm 1
MNAn* registers are set to 9:30PM. These registers depict BCD re presentations of the time. MO (Month) is 1 to 12, YR (Year) is 0 to 99.
24 Hour Time
are not leap years, unless they are also divisible by 400. Clock/Control Registers (CCR). Table 1. Status Register (SR) CC, the device sets this bit to “0”. RWEL and WEL bits to be set in a specific sequence. immediately after the stop condition.
Table 2. Clock/Control Memory Map
0037 RTC (SRAM) Y2K 0 0 Y2K21 Y2K20 Y2K13 0 0 Y2K10 20h
0036 DW 0 0 0 0 0 DY2 DY1 DY0 0-6 00h
0035 YR Y23 Y22 Y21 Y20 Y13 Y12 Y11 Y10 0-99 00h
0034 MO 0 0 0 G20 G13 G12 G11 G10 1-12 00h
0033 DT 0 0 D21 D20 D13 D12 D11 D10 1-31 00h
0032 HR MIL 0 H21 H20 H13 H12 H11 H10 0-23 00h
0031 MN 0 M22 M21 M20 M13 M12 M11 M10 0-59 00h
0030 SC 0 S22 S21 S20 S13 S12 S11 S10 0-59 00h
0013 Control
0012 ATR 0 0 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 00h
0011 INT IM AL1E AL0E 0 0 X X X 00h
0009 MNA1 EMN1 A1M22 A1M21 A1M20 A1M13 A1M12 A1M11 A1M10 0-59 00h
0008 SCA1 ESC1 A1S22 A1S21 A1S20 A1S13 A1S12 A1S11 A1S10 0-59 00h
0007 Alarm0
0006 DWA0 EDW0 0 0 0 0 DY2 DY1 DY0 0-6 00h
0005 YRA0 Unused – Default = RTC Year value – Future expansion
0004 MOA0 EMO0 0 0 A0G20 A0G13 A0G12 A0G11 A0G10 1-12 00h
0003 DTA0 EDT0 0 A0D21 A0D20 A0D13 A0D12 A0D11 A0D10 1-31 00h
0002 HRA0 EHR0 0 A0H21 A0H20 A0H13 A0H12 A0H11 A0H10 0-23 00h
0001 MNA0 EMN0 A0M22 A0M21 A0M20 A0M13 A0M12 A0M11 A0M10 0-59 00h
0000 SCA0 ESC0 A0S22 A0S21 A0S20 A0S13 A0S12 A0S11 A0S10 0-59 00h
during a SR read will contain zeros in these bit locations. and AL0E bits are set to “1”, respectively. alarms respectively, indicate if an alarm has happened. nth hour, or n th date, or for the same day of the week. this pulse will be periodic. error to achieve better accuracy. adjustment and DTR0 gives 20 ppm adjustment. Table 3. Digital Trimming Registers vided to adjust the on-chip loading capacitance range. by a start and ended with a stop). ister Write Enable Latch (RWEL) and the WEL bit.
0 Single Time Event Set By Alarm
1 Repetitive / Recurring Time Event Set By Alarm
FN8097 Rev 3.00 Page 12 of 22 May 2, 2006 are required. (Operation preceeded by a start and ended with a stop). – Write one to 8 bytes to the Clock/Control Registers with the desired clock, alarm, or control data. This sequence starts with a start bit, requires a slave byte of “11011110” and an address within the CCR and is terminated by a stop bit. A write to the CCR changes nonvolatile register values so these initiate a non-vola- tile write cycle and will take up to 10ms to complete. Writes to undefined areas have no effect. The RWEL bit is reset by the completion of a nonvolatile write cycle, so the sequence must be repeated to again initi- ate another change to the CCR contents. If the sequence is not completed for any reason (by sending an incorrect number of bits or sending a start instead of a stop, for example) the RWEL bit is not reset and the device remains in an active mode. – Writing all zeros to the status register resets both the WEL and RWEL bits. – A read operation occurring between any of the previ- ous operations will not interrupt the register write oper- ation. SERIAL COMMUNICATION Interface Conventions The device supports a bidirectional bus oriented proto- col. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data trans- fers, and provides the clock for both transmit and receive operations. Therefore, the devices in this family operate as slaves in all applications. Clock and Data Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 3. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously mo nitors the SDA and SCL lines for the start conditio n and will not respond to any command until this condition has been met. See Figure Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the Standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. See Figure Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will releas e the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 6. The device will respond with an acknowledge after rec- ognition of a start conditi on and if the correct Device Identifier and Select bits are contained in the Slave Address Byte. If a write operation is selected, the device will respond with an acknowle dge after the receipt of each subsequent eight bi t word. The device will acknowledge all incoming data and address bytes, except for: – The Slave Address Byte when the Device Identifier and/or Select bits are incorrect – All Data Bytes of a write when the WEL in the Write Protect Register is LOW – The 2nd Data Byte of a Status Register Write Operation (only 1 data byte is allowed) In the read mode, the device will transmit eight bits of data, release the SDA line, then monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the device will con- tinue to transmit data. Th e device will terminate further data transmissions if an acknowledge is not detected. The master must then issue a stop condition to return the device to Standby mode and place the device into a known state.
write. The contents of the array are not affected. tion, the RWEL bit will be set to 0. Read, Random Read, and Sequential Read. clock cycle and then issue a stop condition. perform a “dummy” write operation. edge, and data transfer sequence. acknowledge and then issuing a stop condition. Figure 9. Current Address Read Sequence
enable very high accuracy timekeeping (<5ppm drift). available today. Table 4 summarizes these parameters.
- For an Epson MC-405 device, for
also include about 2pF of package related capacitance. Table 4. Crystal Parameters Required for Intersil RTC’s Table 5. Crystal Manufacturers Manufacturer Part Number Temp Range +25°C Freq Toler.
note AN154 on Intersil’s website at www.intersil.com. layout for the X1205 SOIC device. Figure 12. Suggested Layout for Intersil RTC in SO-8 pin to ground and the circuit will begin to oscillate. the X2 pin (oscillator output) and observe the waveform. when using the proper crystal and layout). ter, and using a pullup resistor for an open-drain output).
Figure 13. Supercapactor charging circuit the battery will be drained. Table 6. Battery Backup Operation
- Example Application, Vcc=5V, Vback=3.0V
- Example Application, Vcc=3.3V,Vback=3.0V
abled except for the oscillato r and timekeeping circuitry. be needed to get safety agency approval. writes will require higher supplier current. Figure 14. I
FN8097 Rev 3.00 Page 21 of 22 May 2, 2006 Small Outline Package Family (SO) GAUGE PLANE A1 L DETAIL X 4° ±4° SEATING PLANE e H b C 0.010 BM CA0.004 C
0.010 BM CA
B D (N/2)1 E1E NN (N/2)+1 A PIN #1 I.D. MARK h X 45° A SEE DETAIL “X” c 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES N 8 14 16 16 20 24 28 Reference - Rev. L 2/01 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M -1994
FN8097 Rev 3.00 Page 22 of 22 May 2, 2006 X1205 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005-2006. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Thin Shrink Small Outline Plastic Packages (TSSOP) INDEX AREA D N 123 -B- 0.10(0.004) C AM BS e -A- b M -C- A SEATING PLANE 0.10(0.004) c E 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen- sion at maximum material condition. Minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. (Angles in degrees) 0.05(0.002) M8.173
8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE
A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 N8 8 7 0o 8o 0o 8o - Rev. 1 12/00