UPB1009K RENESAS
Document overview
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Technical content
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DESCRIPTION
The µPB1009K is a silicon monolithic IC developed for GPS receiv ers. This IC integrates a full VCO, second IF filter, 4-bit ADC, and digital control interface to reduce cost and mounting space. In addition, its power consumption is low. Moreover, use of a TCXO with frequen cy of 16.368 MHz/16.384 MHz, 14.4 MHz, 19.2 MHz, or 26 MHz switchable with an on-chip divider is possible.
FEATURES
- Double conversion : f REFin = 16.368 MHz, f1stIFin = 61.380 MHz, f2ndIFin = 4.092 MHz Multiple system clocks : On-chip switchable frequency divider (1/N = 100, 3/256, 9/1024, 65/4096) A/D converter : On-chip 4-bit A/D converter High-density RF block : On-chip VCO tank circuit and 2ndIF filter Supply voltage : V CC = 2.7 to 3.3 V Low current consumption : I CC = 26.0 mA TYP. @ VCC = 3.0 V, N = 100 High-density surface mount able : 44-pin plastic QFN
APPLICATIONS
Consumer use GPS receiver of refer ence frequency 16.368 MHz, 2nd IF frequency 4.092 MHz Consumer use GPS receiver of reference frequen cy 14.4, 16.384, 19.2, 26 MHz, 2ndIF frequency 2.556 MHz DATA SHEET Caution Observe precautions when handling because these devices are sensitive to electrostatic discharge. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC Compound Semiconductor Devices representative for availability and additional information. Document No. PU10425EJ01V1DS (1st edition) Date Published September 2004 CP(K) Printed in Japan BIPOLAR ANALOG + DIGITAL INTEGRATED CIRCUIT µPB1009K REFERENCE FREQUENCY 16.368/16.384/19.2/14.4/26 MHz, 2ndIF FREQUENCY 4.092/2.556 MHz RF/IF FREQUENCY DOWN-CONVERTER + PLL FREQUENCY SYNTHESIZER IC FOR GPS RECEIVER The mark shows major revised points. NEC Compound Semiconductor Devices, Ltd. 2003, 2004
ORDERING INFORMATION
Part Number Package Supplying Form µPB1009K-E1 44-pin plastic QFN • 12 mm wide embossed taping
- Pin 1 indicates pull-out direction of tape
- Qty 1.5 kpcs/reel, Dry pack specification Remark To order evaluation samples, contact your nearby sales office. Part number for sample order: µPB1009K Data Sheet PU10425EJ01V1DS 2 µPB1009K
PRODUCT LINE-UP (TA = +25°C, VCC = 3.0 V) Type Part Number Functions (Frequency unit: MHz) VCC (V) ICC (mA) CG (dB) Package Status µPB1009K Pre-amplifier + RF/IF down- converter + PLL synthesizer REF = 16.368 1stIF = 61.380/2ndIF = 4.092 REF = 14.4, 16.384, 19.2, 26 1stIF = 62.980/2ndIF = 2.556 On-chip 4-bit ADC 2.7 to 3.3 26.0 44-pin plastic QFN New DeviceµPB1008K LNA + Pre-amplifier + RF/IF down-converter + PLL synthesizer REF = 27.456 1stIF = 175.164/2ndIF = 0.132 On-chip 2-bit ADC 2.7 to 3.3 18.0 100 to 120 36-pin plastic QFN µPB1007K Pre-amplifier + RF/IF down- converter + PLL synthesizer REF = 16.368 1stIF = 61.380/2ndIF = 4.092 36-pin plastic QFN Clock Frequency Specific 1 chip IC µPB1005K REF = 16.368 1stIF = 61.380/2ndIF = 4.092 2.7 to 3.3 25.0 100 to 120 36-pin plastic QFN Available Remark Typical performance. Please refer to ELECTRICAL CHARACTERISTICS in detail. SYSTEM APPLICATION EXAMPLE GPS receiver RF block diagram PD1 and PD2 in the figure are Power Save Mode control pins. MS1 and MS2 in the figure are TXCO (GPS, W-CDMA, PDC, GSM) control pins. RF =
1575.42 MHz
1st. mix IF SAW 1stLo =
1636.8 MHz
1638.4 MHz
1stIF =
61.38 MHz
62.98 MHz
÷25 Cont. MS1 MS2 PLL TCXO 2nd MIX IF AmpAGC LPF 4bit ADC GPS baseband Para Data AGC cont Samp Clk DC trim IF 2ndIF =
4.092 MHz
2.556 MHz
Caution This diagram schem atically shows only the µPB1009K’s internal functions on the system. This diagram does not present th e actual application circuits. Data Sheet PU10425EJ01V1DS 3 µPB1009K
PIN CONNECTION AND INTERNAL BLOCK DIAGRAM 12345678 9 VDDlogi 1st IFout IFVCC PD2 DCOFFin GNDana 2ndIFout IFGND PLLVCC DCOFFout 2ndIFin PLLGND CLKout 1stIFin LNAVCC PD1 GNDlogi 1stMIXVCC Rext RegGND GND (1st-MIX) PreAMPout MS1 LOVCC VCO1 VCO2 VDDbuf GNDsub AGCout SCKin AGCin 1stMIXin PD 32 31 30 29 28 27 26 25 10 11 24 23 LNAin LNAGND GNDbuf VDDana MS2 Refin CPout LOGND PreAmp 1stMIX CP OSC PLL Fref VGC LPF IFamp Pwdctrl Logic 4bit ADC Data Sheet PU10425EJ01V1DS 4 µPB1009K
No. Pin Name Function and Application Internal Equivalent Circuit 1 PreAMPout Output pin of preamplifier.
2 Rext Connect a resistor for the reference
constant-current power supply to this pin. Ground this pin at 22 kΩ. 3 RegGND Ground pin for regulator. 42 PreAmpV CC Power supply voltage pin for preamplifier. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. 43 PreAmpGND Ground pin of preamplifier. 44 PreAmpin Input pin of preamplifier. Regulator 1 42 343 4 1stMIXin 1stMIX input pin. 5 1stMIXGND Ground pin for first MIX. 40 1stMIXV CC Power supply voltage pin for RF mixer. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. 41 1stIFout Output pin of RF mixer. Insert an IFSAW filter between this pin and pin 37. The VCO oscillation signal can be monitored on this pin. 414 Bias Gibert Cell Data Sheet PU10425EJ01V1DS 5 µPB1009K
No. Pin Name Function and Application Internal Equivalent Circuit MS1 : L MS2 : L TCXO : 16.368,
16.384 MHz
MS1 : L MS2 : H TCXO : 19.2 MHz MS1 : H MS2 : L TCXO : 14.4 MHz MS1 MS2 Low : 0 to 0.3 (V) High : V CC − 0.3 to VCC (V) MS1 : H MS2 : H TCXO : 26 MHz 11 CPout Output pin of charge pump. Connect external R and C to this pin to set a dumping factor and natural angular frequency (Isink = Isource = 0.45 mA). 13 Refin Reference frequency input pin. Connect an external reference transmitter (such as TCXO) to this pin. 14 PLLV CC Power supply voltage pin of PLL. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. 15 PLLGND Ground pin of PLL. 16 CLKout Clock (f TCXO) output pin (IC test pin). Bias Bias Sink SourceBias from divider Data Sheet PU10425EJ01V1DS 6 µPB1009K
No. Pin Name Function and Application Internal Equivalent Circuit 7 LoV CC Power supply voltage pin of VCO. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. VCO1 VCO2 IC test pin. Leave this pin open when the µPB1009K is mounted on board. 10 LoGND Ground pin of VCO. VCO out VCO cont To divider 17 IFGND Ground pin of IF block. 18 2ndIFout Output pin of IF amplifier. 38 1stIFin Input pin of second IF mixer. 39 IFV CC Power supply voltage pin of IF block.
1838 Bias
Data Sheet PU10425EJ01V1DS 7 µPB1009K
No. Pin Name Function and Application Internal Equivalent Circuit 19 2ndIFin Input pin of ADC buffer amplifier.
20 DCOFFout
Output pin of DC trimming OP amplifier.
21 DCOFFin
DC trimming pulse input pin. Connect this pin to pin 20 via a capacitor to convert an input pulse signal into DC. GNDana GNDbuf Ground pin for OP amplifier and ADC power supply.
24 V DDana
Power supply pin for OP amplifier and ADC comparator.
25 V DDbuf
Power supply pin for output driver amplifier of ADC. Connect this pin to the ground pin of the A/D converter via a bypass capacitor to reduce the high-frequency impedance.
26 GNDsub
Ground pin of CMOS substrate. Digital signal output pins. LSB = D0, MSB = D3
31 SCKin
Sampling clock signal input pin.
32 AGCin
AGC control pulse signal input pin.
33 AGCout
AGC control signal output pin. 6.8 kΩ6.8 kΩ 1.8 kΩ 4.7 kΩ PB AY inv 28 Bias32 Data Sheet PU10425EJ01V1DS 8 µPB1009K
No. Pin Name Function and Application Internal Equivalent Circuit
34 V DDlogi Power supply voltage pin for power control
logic. 35 GNDlogi Ground pin for power control logic. PD1 : L PD2 : L Sleep mode (all circuits off). PD1 : H PD2 : L Warm-up mode (PLL on). PD1 : H PD2 : H Calibration mode (PLL + IF + ADC on). PD1 PD2 Low : 0 to 0.3 (V) High : V CC − 0.3 to VCC (V) PD1 : L PD2 : H Active mode (all circuits on). Data Sheet PU10425EJ01V1DS 9 µPB1009K
Parameter Symbol Test Conditions Ratings Unit Supply Voltage V CC T A = +25°C 3.6 V Total Circuit Current I CCTotal T A = +25°C 100 mA Power Dissipation P D T A = +25°C Note 266 mW Operating Ambient Temperature T A −40 to +85 °C Storage Temperature T stg −55 to +125 °C Note Mounted on double-sided copper-clad 50 × 50 × 1.6 mm epoxy glass PWB RECOMMENDED OPERATING RANGE Parameter Symbol MIN. TYP. MAX. Unit Supply Voltage V CC 2.7 3.0 3.3 V Operating Ambient Temperature T A −30 +25 +85 °C RF Input Frequency f RFin − 1 575.42 − MHz 1st LO Oscillating Frequency f 1stLOin − 1 636.8/1 638.4 − MHz 1st IF Input Frequency f 1stIFin − 61.38/62.98 − MHz 2nd LO Input Frequency f 2ndLOin − 65.472/65.536 − MHz 2nd IF Input Frequency f 2ndIFin − 4.092/2.556 − MHz Reference Input/Output Frequency f REFin fREFout − TCXO − MHz Clock mode control voltage (Low Level) VIL1 0 − 0.3 V Clock mode control voltage (High Level) V IH1 V CC − 0.3 − VCC V Power-down control voltage (Low Level) V IL2 0 − 0.3 V Power-down control voltage (High Level) V IH2 V CC − 0.3 − VCC V Data Sheet PU10425EJ01V1DS 10 µPB1009K
The µPB1009K consists of an RF block, an IF block, and a PLL block. By c ontrolling reduction of power to each block (by applying a voltage to the PD1 and PD2 pins), the following four modes can be used. Test Conditions Mode No. Mode Name PD1 PD2 RF Block IF Block (IF + ADC) PLL Block
1 Active mode L H ON ON ON
2 Calibration mode H H OFF ON ON
3 Warm-up mode H L OFF OFF ON
4 Sleep mode L L OFF OFF OFF
Caution To use only the active mode and sleep mode, fi x PD1 to L and select the desired mode with PD2. REFERENCE CLOCK CONTROL MODE The divided frequency can be selected as follows so that it can be shared with the TCXO of each system. Test Conditions TCXO Frequency MS1 MS2 1/N Phase Comparison Frequency
16.368 MHz (GPS)
16.384 MHz (GPS)
L L 1/100 16.368 MHz 19.2 MHz (W-CDMA) L H 3/256 19.2 MHz 14.4 MHz (PDC) H L 9/1024 14.4 MHz
26 MHz (GSM) H H 65/4096 26 MHz
Caution When the reference clock frequency is 16.368 MHz, the 1stIF frequency and 2ndIF frequency are other cases. Data Sheet PU10425EJ01V1DS 11 µPB1009K
ELECTRICAL CHARACTERISTICS (TA = +25°C, VCC = 3.0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Rest current of overall IC in each mode Rest status without input signal, including sampling clock. MS1 = L, MS2 = L Sleep mode Note Is PD1 = L, PD2 = L 1.3 2.2 3.5 mA Warm-up mode I w PD1 = H, PD2 = L 10.5 13.0 15.5 mA Calibration mode I c PD1 = H, PD2 = H 18.0 22.0 25.3 mA Active mode I a PD1 = L, PD2 = H 22.1 26.0 30.0 mA Rest current of PLL block in each clock mode Current of PLL block. Overall current in calibration mode and active mode increases from that in basic mode (MS1 = L, MS2 = L). PD1 = H, PD2 = L. Current when 1/100 divider is used I w1 MS1 = L, MS2 = L 5.3 6.5 7.6 mA Current when 256/3 divider is used I w2 MS1 = L, MS2 = H 9.7 11.3 12.6 mA Current when 1024/9 divider is used I w3 MS1 = H, MS2 = L 10.2 12.1 13.5 mA Current when 4096/65 divider is used I w4 MS1 = H, MS2 = H 10.4 12.3 13.9 mA Maximum mode control pin current H application − − 20 µA 6 pin MS1 L application −20 − − µA H application − − 20 µA 12 pin MS2 L application −20 − − µA H application − − 1 µA 36 pin PD1 L application −1 − − µA H application − − 1 µA 37 pin PD2 L application −1 − − µA <Pre-amplifier> f RFin = 1 575.42 MHz Circuit Current 1 I CC1 No Signals, 1-pin current 1.9 2.3 2.7 mA Power Gain G LNA P RFin = −40 dBm 12.5 15.0 17.5 dB Noise Figure NF LNA f RFin = 1 575 MHz − 3.0 3.5 dB Saturated Output Power P O(SAT)LNA P RFin = −10 dBm −4.0 −2.7 − dBm Input 1dB Compression Level P LNA−1 f RFin = 1 575.42 MHz −25 −21.8 − dBm Input 3rd Order Intercept Point IIP 3LNA f RFin = 1 575.42 MHz, 1 576.42 MHz −12 −9.5 − dBm Input Inpedance Z inLNA − 11.2 − j21.5 − Ω Output Inpedance Z outLNA Calculated from S-parameter where input DC cut capacitance = 1 nF, output load L = 100 n, and DC cut capacitance = 1 nF − 16.4 − j136.6 − Ω Note Most of the current flows into the ADC ladder resistor (V DDana → GNDana) in the sleep mode, and the sleep mode current between other VCC (VDD) and GND is 10 µA maximum. Data Sheet PU10425EJ01V1DS 12 µPB1009K
ELECTRICAL CHARACTERISTICS (TA = +25°C, VCC = 3.0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit <RF mixer> f RF = 1 575.42 MHz, f1stLOin = 1 636.80 MHz, f1stIF = 61.38 MHz Circuit Current 2 I CC2 No Signals, 40 pin current 2.0 2.5 3.0 mA RF Conversion Gain CG RF P RFMIXin = −40 dBm 14.0 16.1 19.0 dB Noise Figure SSBNFRFMIX SSBNF = 10*log (2*DSBNF (Linear value) −1) MHz − 12.8 16.0 dB Maximum IF Output PO (SAT) RFMIX PRFMIXin = −10 dBm −4.0 −0.8 − dBm Input 1dB Compression Level P RFMIX-1 f RFMIXin = 1 575.42 MHz −29.0 −25.5 − dBm Input 3rd Order Intercept Point IIP 3RFMIX f RFMIXin = 1 575.42 MHz, 1 576.42 MHz f1stLO = 1 636.8 MHz −19.0 −17.2 − dBm LO Leakage to IF Pin LO IF − −34.5 −30 dBm LO Leakage to RF Pin LO RF Leakage of 1 636.8 MHz frequency when VCO oscillates correctly. − −54.7 −30 dBm Input Inpedance Z inMIX − 50.1 − j22.3 − Ω Output Inpedance Z outMIX Calculated from S-parameter where input DC cut capacitance = 1 nF and output DC cut capacitance = 1 nF − 57.3 + j2.6 − Ω <IF mixer, LPF, IFamp> f 1stFin = 61.38 MHz, f2ndLOin = 65.472 MHz, ZL = 2 kΩ Circuit Current 3 I CC3 No Signals, 39 pin current 6.3 7.3 8.5 mA VAGC = 0.5 V 66.0 70.3 75.0 dB VAGC = 1.5 V 45.0 51.2 58.0 dB IF Conversion Gain CG (GV) IF VAGC = 2.5 V 19.5 26.4 33.5 dB In Band Gain Fluctuation ∆CG1 3.092 to 5.092 MHz − 0.7 1.0 dB Out Of Band Attenuation ∆CG2 Gain difference at 4.092 MHz and 9.092 MHz, VAGC = 0.5 V 20.0 25.0 − dB Conversion Gain Range CG Range V AGC = 0 to 2.5 V 32.5 43.9 − dB IF ⋅ SSB Noise Figure NF IF V AGC = 0.5 V (at maximum gain) − 13.7 17.5 dB Maximum 2ndIF Output V O (SAT) IF P in = −50 dBm, VAGC = 0.5 V 1.0 1.3 − VPP VAGC = 0.5 V −70.5 −64.4 − dBm VAGC = 1.5 V −53.5 −44.9 − dBm Input 1dB Compression Level P IF-1 f 1stIFin = 61.38 MHz V AGC = 2.5 V −37.0 −30.6 − dBm VAGC = 0.5 V −56.0 −51.3 − dBm VAGC = 1.5 V −38.0 −30.7 − dBm Input 3rd Order Intercept Point IIP 3IF f 1stIFin1 = 61.28 MHz f1stIFin2 = 61.38 MHz f2ndLO = 65.472 MHz VAGC = 2.5 V −27.0 −21.4 − dBm Input Inpedance Z inIF − 69.3 − j4.8 − Ω Output Inpedance Z outIF Calculated from S-parameter where input DC cut capacitance = 1 nF and output DC cut capacitance = 100 nF − 163 + j3.8 − Ω Data Sheet PU10425EJ01V1DS 13 µPB1009K
ELECTRICAL CHARACTERISTICS (TA = +25°C, VCC = 3.0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit <PLL Synthesizer> Circuit Current 4 I CC4 PLL, VCO current, MS1 = L, MS2 = L 8.0 9.5 10.6 mA Icpsink −0.55 −0.45 −0.35 mA Charge Pump Output Current Icpsource V13 pin = VCC/2 0.35 0.45 0.55 mA Loop Filer Output (High Level) VOH V CC−0.3 − − V Loop Filer Output (Low Level) VOL − − 0.2 V Reference Input Level V REFin − 0.2 1.6 V PP VCO Modulation Sensitivity KV Center frequency − 100 − MHz VCO Control Voltage VT When PLL is Locked 0.5 1.3 2.0 V C/N C/N ∆10 kHz 70.0 81.0 − dBc/Hz <A/D Converter> Circuit Current 5 I CC5 3.1 4.1 5.4 mA Resolution ResAD − 4 − bits Sampling Clock fs − − 20 MHz Input Band Width ADBW 5.1 − − MHz Integral Non-linear Error INL DC characteristics − 0.2 1.0 LSB Signal-to-noise Ratio SNR IF = 5.17 MHz, fs = 20.48 MHz 22.0 25.3 − dB Signal-to-noise + Distortion Ratio SINAD IF = 5.17 MHz, fs = 20.48 MHz 20.0 25.1 − dB Number ENOB ENOB = (SINAD −1.763)/6.02 3.0 3.9 − bits Total Harmonic Distortion Ratio THD IF = 5.17 MHz, fs = 20.48 MHz Second-degree to fifth-degree distortion components − −40 −30 dBc Remarks 1. Timing characteristics of ADC during normal operation A buffer amplifier is internally inserted before the ADC core of the µPB1009K. The bias of this buffer amplifier is controlled by the signal input from the DC trim pin, and is used to eliminate the DC offset of the ADC. Because the ladder resistor of the ADC is directly connected between VDDana and GNDana, changes in VDDana affect the resolution of the ADC. Data Sheet PU10425EJ01V1DS 14 µPB1009K
As illustrated in the operation timing chart below, the data of SampleN is pipeline delayed by 1.5 clocks during normal operation, and is output at the rising edge of the sample clock with output delay time Tod. When the operation is changed from normal operation to power-down operation, the status of the output data immediately before the power-down operation is retained (drive status). The following table shows each timi ng parameter for reference purposes. Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Output Delay T od C L = 10 pF, fclk = 19.2 MHz − − 12 ns Pipeline Delay T pld − 1.5 − clock Sampling Delay (Aperture Delay) Tds − 2 − ns Output Hold Time T oh 2 − − ns Data Sheet PU10425EJ01V1DS 15 µPB1009K (a) Normal Operation SampleN SampleN+1 SampleN+2 SampleN+3 SampleN+4 SampleN+5 2ndIFin SCKin D0-D3 N-2 N-1 N N+1 N+2 N+3 : Analog signal sampling timing Tds Tpld Tds Tch Tcl Tclk Toh
Remarks 2. Power-down timing characteristics of ADC The output code of the ADC of the µPB1009K is undefined for 7.5 clocks after the power-down signal is cleared when the ADC returns from the power-down status to normal operation. Note The output data is undefi ned from the start of the power-down operation to the 7.5th clock from the falling edge of the clock at which the power-down operation is cleared. Data Sheet PU10425EJ01V1DS 16 µPB1009K (b) Power-down Operation : Analog signal sampling timing PDB SCKin D0-D3 2ndIFin N N N+1 N+1undefined Note
TYPICAL CHARACTERISTICS (TA = +25°C, VCC = 3.0 V, unless otherwise specified) IC TOTAL CHARACTERISTICS 0 1.0 2.0 3.0 4.0 TA = +85˚C +25˚C –40˚C 0.5 1.5 2.5 3.5 Total Circuit Current ICCTotal (mA) Supply Voltage VCC (V) TOTAL CIRCUIT CURRENT vs. SUPPLY VOLTAGE Remark The graphs indicate nominal characteristics. Data Sheet PU10425EJ01V1DS 17 µPB1009K
PRE-AMPLIFIER BLOCK CHARACTERISTICS –10 –20 –30 –40 300 700100 1 300 1 500 2 000 Power Gain GLNA (dB) Frequency f (MHz) PREAMP GAIN vs. FREQUENCY TA = +85˚C +25˚C –40˚C 500 900 1 100 1 700 1 900 5.0 4.5 3.5 3.0 2.0 1.5 1.0 1 5551 545 1 585 1 595 1 615 Noise Figure NFLNA (dB) Frequency f (MHz) PREAMP NOISE FIGURE vs. FREQUENCY 1 565 1 575 1 605 4.0 2.5 TA = +85˚C +25˚C –40˚C –10 –15 –20 –25 –30 TA = +85˚C +25˚C –40˚C Output Power Pout (dBm) Input Power Pin (dBm) OUTPUT POWER vs. INPUT POWER –10 –20 –30 –40 –70 –80 TA = +85˚C +25˚C –40˚C –35 –25 –20 –50 –60 Output Power Pout (dBm) Input Power Pin (dBm) PREAMP IM CHARACTERISTICS Remark The graphs indicate nominal characteristics. Data Sheet PU10425EJ01V1DS 18 µPB1009K
RF MIX BLOCK CHARACTERISTICS –10 –15 –20 –25 –30 TA = +85˚C +25˚C –40˚C Output Power Pout (dBm) Input Power Pin (dBm) OUTPUT POWER vs. INPUT POWER –10 –20 –30 –40 –70 –80 TA = +85˚C +25˚C –40˚C –40 –30 –25 –50 –60 Output Power Pout (dBm) Input Power Pin (dBm) RF MIX IM CHARACTERISTICS 4030 60 70 90 50 80 TA = +85˚C +25˚C –40˚C Frequency f (MHz) RF CONVERSION GAIN vs. FREQUENCY CHARACTERISTICS RF Conversion Gain CGRF (dB) 4030 60 70 90 50 80 +25˚C –40˚C TA = +85˚C Frequency f (MHz) RF NOISE FIGURE vs. FREQUENCY CHARACTERISTICS RF Noise Fingure SSBNFRFMIX (dB) Remark The graphs indicate nominal characteristics. Data Sheet PU10425EJ01V1DS 19 µPB1009K
IF BLOCK CHARACTERISTICS IF Conversion Voltage Gain CG (GV) IF (dB) 2ndIF Frequency f (MHz) IF CONVERSION VOLTAGE GAIN vs. 2ndIF FREQUENCY 4.5 10.5 206 8 1 2 IF-SSB Noise Figure NFIF (dB) 2ndIF Frequency f (MHz) IF-SSB NOISE FIGURE vs. 2ndIF FREQUENCY 4 10 TA = +85˚C +25˚C –40˚C TA = +85˚C +25˚C –40˚C 0.50 2.0 2.5 3.5 IF Conversion Voltage Gain CG (GV) IF (dB) AGC Voltage VAGC (V) IF CONVERSION VOLTAGE GAIN vs. AGC VOLTAGE 1.0 3.0 TA = +85˚C +25˚C –40˚C 1.5 –10 –15 TA = +85˚C +25˚C –40˚C –65 –60 Output Power Pout (dBm) Input Power Pin (dBm) OUTPUT POWER vs. INPUT POWER –10 –20 –30 –60 –70–75 –55 –50 IF IM CHARACTERISTICS TA = +85˚C +25˚C –40˚C –65 –60 –40 –50 Output Power Pout (dBm) Input Power Pin (dBm) Remark The graphs indicate nominal characteristics. Data Sheet PU10425EJ01V1DS 20 µPB1009K
VCO MODULATION SENSITIVITY CHARACTERISTICS 3.0 2.5 2.0 1.5 1.0 0.5 1 4001 300 1 700 1 800 1 900 VCO Control Voltage VT (V) VCO Frequency fVCO (MHz) VCO CONTROL VOLTAGE vs. VCO FREQUENCY 1 500 1 600 TA = +85˚C +25˚C –40˚C C/N CHARACTERISTICS Ref = –10 dBm Atten 5 dB Mkr1 = 10.0 kHz Noise –81.78 dB/Hz Span 100 kHz Sweep 300 ms (401 pts) Center = 1.637 GHz Res BW 1 kHz VBW 1 kHz Ref = –10 dBm Atten 5 dB Mkr1 = 10.0 kHz Noise –81.92 dB/Hz Span 100 kHz Sweep 300 ms (401 pts) Center = 1.637 GHz Res BW 1 kHz VBW 1 kHz Ref = –10 dBm Atten 5 dB Mkr1 = 10.0 kHz Noise –81.23 dB/Hz Span 100 kHz Sweep 300 ms (401 pts) Center = 1.637 GHz Res BW 1 kHz VBW 1 kHz Remark The graphs indicate nominal characteristics. Data Sheet PU10425EJ01V1DS 21 µPB1009K
SINAD CHARACTERISTICS OF A/D CONVERTOR (IFin = 5.17 MHz, SCLKin = 20.48 MHz) +10 –10 –20 –30 –40 –50 –60 –70 –80 02 468 1 0 1 2 AMPLITUDE (dB) ANALOG INPUT FREQUENCY (MHz) TA = +25˚C SNR = 25.4 dB SINAD = 25.3 dBc SFDR = 42.3 dB ENOB = 3.91 bit THD = –40.9 dBc +10 –10 –20 –30 –40 –50 –60 –70 –80 0 2 468 1 0 1 2 AMPLITUDE (dB) ANALOG INPUT FREQUENCY (MHz) TA = –40˚C SNR = 25.4 dB SINAD = 25.3 dBc SFDR = 41.1 dB ENOB = 3.91 bit THD = –40.4 dBc +10 –10 –20 –30 –40 –50 –60 –70 –80 0 2 468 1 0 1 2 AMPLITUDE (dB) ANALOG INPUT FREQUENCY (MHz) TA = +85˚C SNR = 25.4 dB SINAD = 25.3 dBc SFDR = 43.7 dB ENOB = 3.92 bit THD = –42.1 dBc Remark The graphs indicate nominal characteristics. Data Sheet PU10425EJ01V1DS 22 µPB1009K
3.9 nH 100 nF1 nF VCC 3.9 nH 7 pF1 nF PreAmpin 100 nF 82 pF VCC 1 nF 25 1stIFout 100 nF 82 pFVCC 1 nF 24 1stIFin
23 PD2
22 PD1
100 kΩ 100 kΩ AGCin AGCout SCKin VCC 100 nF 82 pF 100 nF 100 kΩ DCOFFout 13 DCOFFin 100 kΩ 100 nF 2ndIFin 50 Ω 100 nF 2ndIFout 2 kΩ 1 nF CLKout 100 nF82 pF VCC 1 nF REFin 8MS2 750 F
2 PreAmpout
22 kΩ 3 1stMIXin
4 MS1
5 Presin
1 kΩ
6 VCOc
10 kΩ CPout 1.5 kΩ 10 kΩ 8.2 nF 100 nF 1 nF Data Sheet PU10425EJ01V1DS 23 µPB1009K
DESCRIPTION OF PINS OF TEST CIRCUIT Pin No. Pin Function Pin Name Pin No. Pin Function Pin Name
1 Preamplifier Input PreAmpin 14 DC Offset Input DCOFFin
2 Preamplifier Output PreAmpout 15 Digital Signal Output Pin D0
3 RF Mixer Input 1stMIXin 16 D1
4 MS1 MS1 17 D2
5 Prescaler Input Presin 18 D3
6 VCO Power Control Pin VCOc 19 Sampling Signal Input SCKin
7 VT Measurement Pin (Charge Pump
Output) CPout 20 AGC Input AGCin
8 MS2 MS2 21 AGC Control Voltage Output AGCout
9 Reference Clock Input REFin 22 PD1 Output (Default on board : GND) PD1
10 Clock Output CLKout 23 PD1 Output (Default on board : V CC) PD2
11 2ndIF Output 2ndIFout 24 1stIF Input 1stIFin 12 2ndIF Input 2ndIFin 25 1stIF Output 1stIFout
13 DC Offset Output DCOFFout
Data Sheet PU10425EJ01V1DS 24 µPB1009K
4.7 nH 100 nF1 nF VCC 3.9 nH 7 pF 1 nF RFin 100 nF 82 pF VCC 1 nF 100 nF 82 pFVCC 1 nF RFPD2 RFPD1 100 nF 82 pF VCC 100 kΩ AGCout SCLKout VCC 100 nF 82 pF 100 nF 1 nF CLKout 100 nF82 pF VCC 1 nF REFin MS2 500 F 22 kΩ MS1 VCC 100 pF 1 nF 8.2 nF 1.5 kΩ 82 pF 100 nF 100 nF 100 kΩ DCOFF 100 nF 1 pF IFSAW RFSAW 510 Ω 5.6 nH VCC in outAMP 3.9 nH TopSAW 100 nF 10 nF100 nF PD1 PD2 Power-down mode MS1 MS2 TCXO N 0 0 Sleep mode (full off) 0 0 16.368/16.384 MHz 100 1 0 Warm-up mode (PLL on) 0 1 19.2 MHz 256/3 1 1 Calibration mode (PLL on) 1 0 14.4 MHz 1024/9 0 1 Active mode (full on) 1 1 26.0 MHz 4096/65 Data Sheet PU10425EJ01V1DS 25 µPB1009K
44-PIN PLASTIC QFN (UNIT: mm) 6.2±0.2 6.0±0.2 6.2±0.2 6.0±0.2
44 Pin
1 Pin
6.2±0.2 6.0±0.2 6.2±0.2 6.0±0.2 1.0MAX. 0.14+0.10 –0.05 0.18±0.05 0.55±0.2 (Bottom View) 0.4 Caution The island pins located on the corners are need ed to fabricate products in our plant, but do not serve any other function. Consequently the island pins should not be soldered and should remain non-connection pins. Data Sheet PU10425EJ01V1DS 26 µPB1009K
(1) Observe precautions for handling because of electro-static sensitive devices. (2) Form a ground pattern as widely as possible to mi nimize ground impedance (to prevent abnormal oscillation). (3) Keep the wiring length of the gr ound pins as short as possible. (4) Connect a bypass capacitor to the V CC pin. (5) High-frequency signal I/O pins must be coupled with t he external circuit using a coupling capacitor. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your nearby sales office. Soldering Method Soldering Conditions Condition Symbol Infrared Reflow Peak temperature (package surface temperature) : 260 °C or below Time at peak temperature : 10 seconds or less Time at temperature of 220°C or higher : 60 seconds or less Preheating time at 120 to 180°C : 120 ±30 seconds Maximum number of reflow processes : 3 times Maximum chlorine content of rosin flux (% mass) : 0.2%(Wt.) or below IR260 VPS Peak temperature (package surface temperature) : 215 °C or below Time at temperature of 200°C or higher : 25 to 40 seconds Preheating time at 120 to 150°C : 30 to 60 seconds Maximum number of reflow processes : 3 times Maximum chlorine content of rosin flux (% mass) : 0.2%(Wt.) or below VP215 Wave Soldering Peak temperature (molten solder temperature) : 260 °C or below Time at peak temperature : 10 seconds or less Preheating temperature (package surface temperature) : 120 °C or below Maximum number of flow processes : 1 time Maximum chlorine content of rosin flux (% mass) : 0.2%(Wt.) or below WS260 Partial Heating Peak temperature (pin temperature) : 350 °C or below Soldering time (per side of device) : 3 seconds or less Maximum chlorine content of rosin flux (% mass) : 0.2%(Wt.) or below HS350 Caution Do not use different soldering met hods together (except for partial heating). Data Sheet PU10425EJ01V1DS 27 µPB1009K
M8E 00. 4 - 0110 The information in this document is current as of September, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation, NEC Compound Semiconductor Devices, Ltd. and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). Data Sheet PU10425EJ01V1DS 28 µPB1009K
NEC Compound Semiconductor Devices Hong Kong Limited E-mail: ncsd-hk@elhk.nec.com.hk (sales, technical and general) Hong Kong Head Office Taipei Branch Office Korea Branch Office TEL: +852-3107-7303 TEL: +886-2-8712-0478 FAX: +852-3107-7309 FAX: +886-2-2545-3859 NEC Electronics (Europe) GmbH http://www.ee.nec.de/ TEL: +49-211-6503-0 FAX: +49-211-6503-1327 California Eastern Laboratories, Inc. http://www.cel.com/ TEL: +1-408-988-3500 FAX: +1-408-988-0279 0406 NEC Compound Semiconductor Devices, Ltd. http://www.ncsd.necel.com/ E-mail: salesinfo@ml.ncsd.necel.com (sales and general) techinfo@ml.ncsd.necel.com (technical) Sales Division TEL: +81-44-435-1588 FAX: +81-44-435-1579 For further information, please contact µPB1009K