UPB1008K RENESAS

Document overview

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Technical content

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DESCRIPTION

The µPB1008K is a silicon monolithic integrated circuit for GPS receiver. This IC is designed as double conversion RF block integrated Pre-Amplifier + RF/IF down-converter + PLL frequency synthesizer on 1 chip. This IC has IQ recovery function, builds a 2-bit A/D converter in both I channels and Q channels, respectively, and carries them in 36-pin plastic QFN package. This IC is manufactured using our 30 GHz fmax UHS0 (Ultra High Speed Process) silicon bipolar process.

FEATURES

  • Double conversion : f REFin = 27.456 MHz, f1stIFin = 175.164 MHz, f2ndIFin = 132 kHz  Integrated RF block : Pre-Amplifier + RF/IF frequency down-converter + PLL frequency synthesizer : The 2-bit A/D converter is unified to single chip.  Needless to input counter data : fixed division internal prescaler  VCO side division : ÷102 (÷8, ÷12.75 serial prescaler)  Reference division : ÷2  Supply voltage : V CC = 2.7 to 3.3 V  Low current consumption : I CC = 18.0 mA TYP. @ VCC = 3.0 V  Gain adjustable externally : Gain control voltage pin (control voltage up vs. gain down)  Power-save function : Power-save dark current I CC (PD) = 10 µA MAX.  High-density surface mountable : 36-pin plastic QFN

APPLICATIONS

 Consumer use GPS receiver of reference frequency 27.456 MHz, 2nd IF frequency 132 kHz (for general use)

ORDERING INFORMATION

Part Number Package Supplying Form µPB1008K-E1 36-pin plastic QFN • 12 mm wide embossed taping

  • Pin 1 indicates pull-out direction of tape
  • Qty 2.5 kpcs/reel Remark To order evaluation samples, contact your nearby sales office. Part number for sample order: µPB1008K DATA SHEET Caution Observe precautions when handling because these devices are sensitive to electrostatic discharge. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC Compound Semiconductor Devices representative for availability and additional information. Document No. PU10282EJ01V0DS (1st edition) Date Published November 2003 CP(K) Printed in Japan  NEC Compound Semiconductor Devices 2003 BIPOLAR ANALOG + DIGITAL INTEGRATED CIRCUIT µPB1008K REFERENCE FREQUENCY 27.456 MHz, 2ndIF FREQUENCY 132 kHz RF/IF FREQUENCY DOWN-CONVERTER + PLL FREQUENCY SYNTHESIZER IC FOR GPS RECEIVER

PRODUCT LINE-UP (T A = +25°C, VCC = 3.0 V) Type Part Number Functions (Frequency unit: MHz) VCC (V) ICC (mA) CG (dB) Package Status Clock Frequency Specific 1 chip IC µPB1008K Pre-amplifier + RFdown- converter + IQ down-converter + IF amplifier + 2-bit ADC + PLL synthesizer REF = 27.456 1stIF = 175.164/2ndIF = 0.132 On-chip 2-bit ADC 2.7 to 3.3 18.0 100 to 120 36-pin plastic QFN New Device µPB1007K Pre-amplifier + RF/IF down- converter + PLL synthesizer REF = 16.368 1stIF = 61.380/2ndIF = 4.092 2.7 to 3.3 25.0 100 to 120 36-pin plastic QFN Available µPB1005K REF = 16.368 1stIF = 61.380/2ndIF = 4.092 36-pin plastic QFN Available Remark Typical performance. Please refer to ELECTRICAL CHARACTERISTICS in detail. To know the associated products, pleas e refer to their latest data sheets. SYSTEM APPLICATION EXAMPLE GPS receiver RF block diagram Basic frequency in a figure is set to f 0= 1.023 MHz. NE696M01 NF = 1.2 dB G =17 dB RF SAW LNA L/C filter1st Mixer TANK Loop Filter /2 /4 AGC IQ Demod 2-bit ADC BASEBAND IC ISign IMag PLL Frequency Counters 2-bit ADC QSign QMag Reference ClockREFin

27.456 MHz

1 400.256 MHz Caution This diagram schematically shows only the µPB1008K’s internal functions on the system. This diagram does not present th e actual application circuits. Data Sheet PU10282EJ01V0DS 2 µPB1008K

PIN CONNECTION AND INTERNAL BLOCK DIAGRAM 12345678 9 VCCanalog VREF Mixout2 IF-in2 DCoffsetQb GNDbb 2ndIFout-Q PD1 REFin DCoffsetQ 2ndIFout-Qb GNDdig IC Cntl GND analog LNAbias IF-in1 VAGC Mixout1 LNAin VCCrf 1stLO-OSC1 GND LNA 1stLO-OSC2 VCCLO PD out VCCdig Qmag Qsign VCCbb Isign 2ndIFout-I Imag DCoffsetIb DCoffsetI 2ndIFout-lb GND LO 26 25 24 23 22 21 20 19/2 /2PD /8/6/7/2 Vth 2-bit ADC Vth 2-bit ADC Data Sheet PU10282EJ01V0DS 3 µPB1008K

No. Pin Name Function and Application Internal Equivalent Circuit 1 GND LNA Ground pin of LNA. 2 LNAin Input pin of low noise amplifier. It is a single-ended open collector design. Capacitive coupling is required; external matching will improve gain or NF. Regulator Bias VCC 6.5 kΩ

3 V CCrf

Supply voltage pin of LNA, RF mixer and VCO voltage regulator.

4 GND LO

Ground pin of 1stLO oscillator circuit and RF Mixer. 5 1stLO-OSC1 6 1stLO-OSC2 Pin 5 & 6 are base pins of the differential amplifier for 1stLO oscillator. These pins requre an LC (varacator) tank circuit to oscilate at around 1 400 MHz.

7 V CCLO Supply voltage pin of oscillator

circuit for 1stLO oscillator and RF mixer. Regulator Bias VCC 4.4 kΩ 1.8 pF 1.8 pF 4.4 kΩ 400 Ω 400 Ω 410 Ω idc = 941 µ

8 PD out This is a cirrent mode charge

pump output. For connection to a passive RC loop filter for driving external varactor diode of 1stLO oscillator.

9 V CCdig Supply voltage pin of digital

portion of the chip. Source Control Sink Control ESD ESD SourceSink PFD PFD FROM PFD Data Sheet PU10282EJ01V0DS 4 µPB1008K

No. Pin Name Function and Application Internal Equivalent Circuit

10 REFin Input pin of reference frequency

buffer. This pin should be equipped with external 27 MHz oscillator (e.g. TCXO).

11 GNDdig Ground pin of digital portion of

the chip. ESD ESD idc = 22 idc = 9.7 20 kΩ 20 kΩ 500 Ω500 Ω 50 kΩ 5.4 pF 30 kΩ µ µ

12 IQ cntl The voltage on this pin controls

the Q channel IF amplifier gain control of ±2 dB can be achieved for 0 to 3 V. Leave open-circuited if not used. idc = 23.5 7.1 kΩ7.1 kΩ 7.1 kΩ 200 kΩ idc = 23.5 7.1 kΩ 12 kΩ IREF CCCS µ µ

13 PD1

Standby mode control. Low = whole chip OFF & High = Whole chip ON. ESD ESD 28 kΩ VCC Data Sheet PU10282EJ01V0DS 5 µPB1008K

No. Pin Name Function and Application Internal Equivalent Circuit 14 2ndIFout-Q 15 2ndIFout-Qb Differential output pins of quadrature demodulator Q output. Adding a lowpass shunt capacitor between these pins will define the IF bandwidth. idc = 86 2 kΩ idc = 86 2 kΩ ESD ESD ESD ESD 2 kΩ 2 kΩ From 2nd Mixer 15 (26) (27) To channel amp µ µ

16 DCoffsetQ DC offset compensation pin for

C arm. A low pass capacitor shunt to pin 17 is required.

17 DCoffsetQb DC offset compensation pin for

Q-bar arm. A low pass capacitor shunt to pin 16 is required. idc = 84 4 kΩ idc = 84 4 kΩ ESD ESD ESD ESD 150 kΩ 150 kΩ From 2nd Mixer 17 (24) (25) To channel amp 20 kΩ 9 pF µ µ

18 GNDbb Ground pin of CMOS output

driver. 19 Qmag Digitizd Q signal. Magnitude bit of 2-bit ADC output. 20 Qsign Digitizd Q signal. Sign bit of 2- bit ADC output. 21 Isign Digitizd I signal. Magnitude bit of 2-bit ADC output. 22 Imag Digitizd I signal. Magnitude bit of 2-bit ADC output.

23 V CCbb Supply voltage pin of CMOS

output driver. 21.5 Ω 5 kΩ From Comparator 21.5 Ω ESD ESD 19 (20, 21, 22) Data Sheet PU10282EJ01V0DS 6 µPB1008K

No. Pin Name Function and Application Internal Equivalent Circuit

24 DCoffsetlb DC offset compensation pin for

l-bar arm. A low pass capacitor shunt to pin 25 is required.

25 DCoffsetl DC offset compensation pin for

I-bar arm. A low pass capacitor shunt to pin 24 is required. See pin 16 & 17 schematic 26 2ndIFout-Ib 27 2ndIFout-I Differential output pins of quadrature demodulator I output. Adding a lowpass shunt capacitor between these pins will define the IF bandwidth. See pin 14 & 15 schematic

28 V CCanalog Supply voltage pin of analog

portion of the chip.

29 V AGC Gain control voltage pin of IF

amplifier. This voltage performs reverse control, (i.e., VAGC up → gain down). If this pin is left open, then it is default at maximum gain. 300 Ω 3 kΩ ESD ESD 44 kΩ To AGC Amp

30 IF-in1

31 IF-in2

Differential input pins of 1stIF AGC amplifier.

32 GND analog Ground pin of analog portion of

the chip. 4 kΩ 2 kΩ2 kΩ 4 kΩ 40 Ω 1.42 kΩ 1.42 kΩ 4 kΩ4 kΩ From AVGC AVGC ampout Regulator ESD ESD ESD ESD Bias Data Sheet PU10282EJ01V0DS 7 µPB1008K

No. Pin Name Function and Application Internal Equivalent Circuit

33 Mixout2

34 Mixout1

Differential output pins of RF mixer. This is an emitter follower output buffer, provide a 50 Ω output load. 111 Ω 111 Ω 1.67 pF 1.67 pF 4 kΩ 4 kΩ Regulator From Mixer ESD ESD ESD ESD

35 V REF Base-emitter junction voltage

with respect to ground. May be used for biasing an external discrete transistor. PTAT current. Bias 500 Ω 40 kΩ ESD ESD Regulator VCC 36 LNAbias LNA output pin. External bias (VCC ) and matching for gain is required. See pin 2 schematic Data Sheet PU10282EJ01V0DS 8 µPB1008K

Parameter Symbol Test Conditions Ratings Unit Supply Voltage V CC T A = +25°C 3.6 V Total Circuit Current I CCTotal T A = +25°C 100 mA Power Dissipation P D T A = +25°C Note 361 mW Operating Ambient Temperature T A −40 to +85 °C Storage Temperature T stg −55 to +150 °C Note Mounted on double-sided copper-clad 50 × 50 × 1.6 mm epoxy glass PWB RECOMMENDED OPERATING RANGE Parameter Symbol MIN. TYP. MAX. Unit Supply Voltage V CC 2.7 3.0 3.3 V Operating Ambient Temperature T A −40 +25 +85 °C RF Input Frequency f RFin − 1 575.42 − MHz 1st LO Oscillating Frequency f 1stLOin − 1 400.256 − MHz 1st IF Input Frequency f 1stIFin − 175.164 − MHz 2nd LO Input Frequency f 2ndLOin − 175.032 − MHz 2nd IF Input Frequency f 2ndIFin f2ndIFout − 132 − kHz Reference Input Frequency f REFin − 27.456 − MHz POWER DOWN CONTROL (PIN 13) VOLTAGE Parameter Symbol MIN. TYP. MAX. Unit Power Down Voltage (Low Level) V IL 0 − 0.5 V Power Down Voltage (High Level) V IH 2.0 − VCC V AGC CONTROL VOLTAGE Parameter Symbol MIN. TYP. MAX. Unit AGC Control Voltage V AGC 0.5 − 2.5 V Data Sheet PU10282EJ01V0DS 9 µPB1008K

ELECTRICAL CHARACTERISTICS (T A = +25°C, VCC = 3.0 V) CIRCUIT CURRENT Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Total Circuit Current I CCTotal No signal 14.0 18.0 23.5 mA Power-save Dark Current I CC (PD) Pin 13 = 0 V − 1 − µA Reference Block Circuit Current (Pin 3) ICC (rf) No signal 0.4 0.5 0.7 mA VCO Block Circuit Current (Pin 7) ICC (lo) No signal 4.1 5.6 7.2 mA PLL Block Circuit Current (Pin 9) ICC (pll) No signal 2.7 3.6 4.7 mA Baseband Block Circuit Current (Pin 23) I CC (bb) No signal, open load 2.5 3.4 4.3 mA IF Block Circuit Curent (Pin 28) ICC (if) No signal 2.7 3.7 4.7 mA Pre-Amplifier Open Connector Current (Pin 36) I CC (lna) No signal 1.0 1.4 1.8 mA Data Sheet PU10282EJ01V0DS 10 µPB1008K

AC ELECTRICAL CHARACTERISTICS Parameter Symbol Test Conditions MIN. TYP. MAX. Unit RF Block (LNA, RFmixer) fRFin = 1 575.42 MHz, f1stLOin = 1 400.256 MHz, PLO = 0 dBm, f1stIF = 175.164 MHz, Pin15 = 3 V, ZL = Zin = 50 Ω Power conversion gain CG LNA-MIX P RFin = −60 dBm 18 23 28 dB Noise Figure NF LNA-MIX Input matched, DSB − 5 − dB Input 1dB Compression Level Pin (1dB) LNA-MIX Input matched − −38 − dBm Local Signal Leak to IF A LO-IF − −35 − dBm Local Signal Leak to RF A LO-RF − −50 − dBm IF Block (AGC, IQ Mix, IFamp, ADC) f 1stIFin = 175.164 MHz, f2ndLOin = 175.032 MHz, f2ndIFout = 132 kHz, ZL = 2 kΩ, Zin = 600 Ω I ch Magbit Output Pluse Duty Duty-I ch P1stIFin = −80 dBm, VAGC = 0.5 V, VIQ-C = 0 V 50 70 − % Q ch Magbit Output Pluse Duty Duty-Q ch P2ndIFin = −80 dBm, VAGC = 0.5 V, VIQ-C = 2.1 V 50 70 − % Input 1dB Compression Level P in (1dB) AGC AGCamp + IQ MIX − −45 − dBm AGC Control range A AGC 25 45 − dB 2ndLO Isoration (1stIFin) A 2ndLO-1stIF V AGC = 0 V − −90 − dB IQ Balance Control Voltage V IQ-C I ch = Qch − 2.1 2.8 V IQ Balance Control Gain Range A IQ-C Magbit Output Pulse Duty Cycle 50% (Qch) 4.0 6.5 − dB PLL PLL Charge Pump High Side Current I CPOH V CPout = VCC /2 − 200 − µA PLL Charge Pump Low Side Current I CPOL V CPout = VCC /2 − −200 − µA Phase Comparision Frequency f PD − 13.728 − MHz VCO, REF Amp Reference Input Minimum Level V REFin 50 200 − mVpp Input Frequency of Reference Input f REFin − 27.456 − MHz VCO Control Voltage VT PLL Locked 0.8 1.5 2.2 V VCO C/N C/N ∆1 kHz 57 62 − dBc/Hz Data Sheet PU10282EJ01V0DS 11 µPB1008K

TYPICAL CHARACTERISTICS (Unl ess otherwise specified, TA = +25°C, VCC = 3.0 V)  IC TOTAL  0 1.0 2.0 3.0 4.0 TA = +85˚C +25˚C –40˚C 0.5 1.5 2.5 3.5 0 1.0 2.0 3.0 4.0 Total Circuit Current ICCTotal (mA) Supply Voltage V (PS) (V) TOTAL CIRCUIT CURRENT vs. V (PS) 0.5 1.5 2.5 3.5 TA = +85˚C +25˚C –40˚C VCC = 3 V TOTAL CIRCUIT CURRENT vs. SUPPLY VOLTAGE Total Circuit Current ICCTotal (mA) Supply Voltage VCC (V) Remark The graphs indicate nominal characteristics. Data Sheet PU10282EJ01V0DS 12 µPB1008K

 RF BLOCK (LNA + RF down converter)  TA = +85˚C +25˚C –40˚C –10 –20 –30 –40 –50 –70 –60 –30 –20 TA = +85˚C +25˚C –40˚C –10 –20 –30 –40 –50 –70 –60 –30 –20 VCC = 2.7 V 3.0 V 3.3 V –30 –20 VCC = 2.7 V 3.0 V 3.3 V RF : f = 1 575.42 MHz LO : f = 1 400.256 MHz IF : f = 175.164 MHz P in = 0 dBm, TA = +25˚C RF : f = 1 575.42 MHz LO : f = 1 400.256 MHz IF : f = 175.164 MHz P in = 0 dBm, TA = +25˚C RF : f = 1 575.42 MHz LO : f = 1 400.256 MHz IF : f = 175.164 MHz P in = 0 dBm RF : f = 1 575.42 MHz LO : f = 1 400.256 MHz IF : f = 175.164 MHz P in = 0 dBm 1stIF Output Power P1stIFout (dBm) RF Input Power PRFin (dBm) 1stIF OUTPUT POWER vs. RF INPUT POWER 1stIF Output Power P1stIFout (dBm) RF Input Power PRFin (dBm) 1stIF OUTPUT POWER vs. RF INPUT POWER vs. RF INPUT POWER RF CONVERSION GAIN RF Conversion Gain CGRF (dB) RF Input Power PRFin (dBm) vs. RF INPUT POWER RF CONVERSION GAIN RF Conversion Gain CGRF (dB) RF Input Power PRFin (dBm) –10 –20 VCC = 2.7 V 3.0 V 3.3 V RF : f = 1 575.42 MHz LO : f = 1 400.256 MHz IF : f = 175.164 MHz P in = –50 dBm TA = +25˚C RF Conversion Gain CGRF (dB) LO Input Power PLOin (dBm) vs. LO INPUT POWER RF CONVERSION GAIN RF Conversion Gain CGRF (dB) LO Input Power PLOin (dBm) vs. LO INPUT POWER RF CONVERSION GAIN TA = +85˚C +25˚C –40˚C –10 –20 RF : f = 1 575.42 MHz LO : f = 1 400.256 MHz IF : f = 175.164 MHz P in = –50 dBm, VCC = 3.0 V Remark The graphs indicate nominal characteristics. Data Sheet PU10282EJ01V0DS 13 µPB1008K

Local leakage power@RFin (dBm) LO Input Power PLOin (dBm) –10 0 –20 –30 –40 –70 –60 –100 –90 –50 –80 PIFout : VCC = 2.7 V 3.0 V 3.3 V RF : 50 Ω terminate LO : f = 1 400.256 MHz TA = +25˚C 500 1 000 2 000 RF Conversion Gain CGRF (dB) RF Input Frequency fRFin (MHz) vs. RF INPUT FREQUENCY 1 500 VCC = 2.7 V 3.0 V 3.3 V RF : P = –50 dBm LO : Pin = 0 dBm IF : f = 175.164 MHz TA = +25˚ RF CONVERSION GAIN RF : f = 1 575.42 MHz P = –50 dBm LO : P in = 0 dBm TA = +25˚C RF Conversion Gain CGRF (dB) IF Output Frequency fIFout (MHz) 10 100 1 000 VCC = 2.7 V 3.0 V 3.3 V vs. IF OUTPUT FREQUENCY RF CONVERSION GAIN Local leakage power@1stIFout (dBm) –10 0 –20 –30 –40 –70 –60 –100 –90 –50 –80 PIFout : VCC = 2.7 V 3.0 V 3.3 V RF : f = 1 575.42 MHz Pin = –80 dBm LO : f = 1 400.256 MHz T A = +25˚C LO Input Power PLOin (dBm) vs. LO INPUT POWER LOCAL LEAKAGE POWER@1stIFout vs. LO INPUT POWER LOCAL LEAKAGE POWER@RF in Noise Filter NF (DSB) (dB) Supply Voltage VCC (V) 2.7 3.4 +25˚C –40˚C TA = +85˚C 2.8 2.9 3.13.0 RF : f = 1 575 MHz Pin = 0 dBm LO : f = 1 400 MHz IF out : f = 175 MHz NOISE FILTER vs. SUPPLY VOLTAGE Remark The graphs indicate nominal characteristics. Data Sheet PU10282EJ01V0DS 14 µPB1008K

 RF BLOCK (PLL/REF)  200 –100 –200 25 29 30 Charge Pump Output Current Icp ( A) Input Frequency of Reference Input fREFin (MHz) 150 27 28 PREFin = –10 dBm VCC = 3.0 V Vcpout = 1.5 V 100 –50 –150 µ TA = +85˚C +25˚C –40˚C vs. REFERENCE FREQUENCY CHARGE PUMP OUTPUT CURRENT –20 –60 –80 –100 1 100 1 000 Output Power Pout (dBm) Reference Input Minimum Level VREFin (mVPP ) –30 –40 –50 –70 –90 VCC = 2.7 V 3.0 V 3.3 V fREFin = 27.456 MHz fMIXout = 1 400.256 MHz TA = +25˚C vs. REFERENCE INPUT MINIMUM LEVEL OUTPUT POWER –20 –60 –80 –100 1 100 1 000 10 –30 –40 –50 –70 –90 fREFin = 27.456 MHz fMIXout = 1 400.256 MHz VCC = 3.0 V TA = +85˚C +25˚C –40˚C Output Power Pout (dBm) Reference Input Minimum Level VREFin (mVPP ) vs. REFERENCE INPUT MINIMUM LEVEL OUTPUT POWER Remark The graphs indicate nominal characteristics. Data Sheet PU10282EJ01V0DS 15 µPB1008K

 IF BLOCK (AGCamp + IF MIX + IFamp + ADC)  I C H Q C H 100 –85 –80–90 –75 Mag Duty (%) 1stIF Input Power P1stIFin (dBm) MAG DUTY vs. 1stIF INPUT POWER 2ndLO : f = 175.032 MHz 1stIF : f = 175.164 MHz 2ndIF : f = 132 kHz Zin = 600 Ω , ZL = 2 kΩ VAGC = 0.5 V, VCC = 3.0 V VIQ–C = 0 V, TA = +25˚C 100 –90 –85–95 –80 Mag Duty (%) 1stIF Input Power P1stIFin (dBm) 2ndLO : f = 175.032 MHz 1stIF : f = 175.164 MHz 2ndIF : f = 132 kHz Zin = 600 Ω , ZL = 2 kΩ VAGC = 0.5 V, VCC = 3.0 V VIQ–C = 0 V, TA = +25˚C MAG DUTY vs. 1stIF INPUT POWER –20 –30 –40 –50 –90 0.5 2.50 3.0 1stIF Input Power P1stIFin (dBm) AGC Voltage VAGC (V) P1stIFin (MAG DUTY 50%) vs. AGC VOLTAGE –60 –70 –80 2ndLO : f = 175.032 MHz 1stIF : f = 175.164 MHz 2ndIF : f = 132 kHz Zin = 600 Ω , ZL = 2 kΩ VCC = 3.0 V VIQ–C = 0 V 2.01.51.0 TA = +85˚C +25˚C –40˚C –75 –80 –85 –100 0.5 2.50 3.0 1stIF Input Power P1stIFin (dBm) IQ-Ctrl Voltage VIQ-C (V) P1stIFin (MAG DUTY 50%) vs. IQ-CTRL VOLTAGE –90 2ndLO : f = 175.032 MHz 1stIF : f = 175.164 MHz 2ndIF : f = 132 kHz Zin = 600 Ω , ZL = 2 kΩ VCC = 3.0 V VAGC = 0.5 V 2.01.51.0 TA = +85˚C +25˚C –40˚C –95 –75 –80 –85 –100 0.5 2.50 3.0 1stIF Input Power P1stIFin (dBm)) IQ-Ctrl Voltage VIQ-C (V) P1stIFin (MAG DUTY 50%) vs. IQ-CTRL VOLTAGE –90 2ndLO : f = 175.032 MHz 1stIF : f = 175.164 MHz 2ndIF : f = 132 kHz Zin = 600 Ω , ZL = 2 kΩ VCC = 3.0 V VAGC = 0.5 V 2.01.51.0 TA = +85˚C +25˚C –40˚C –95 –20 –30 –40 –50 –100 0.5 2.50 3.0 –60 –70 –80 2ndLO : f = 175.032 MHz 1stIF : f = 175.164 MHz 2ndIF : f = 132 kHz Zin = 600 Ω , ZL = 2 kΩ VCC = 3.0 V VIQ–C = 0 V 2.01.51.0 TA = +85˚C +25˚C –40˚C –90 1stIF Input Power P1stIFin (dBm) AGC Voltage VAGC (V) P1stIFin (MAG DUTY 50%) vs. AGC VOLTAGE Remark The graphs indicate nominal characteristics. Data Sheet PU10282EJ01V0DS 16 µPB1008K

–40 –10–50 10 2ndLO : f = 175.032 MHz 1stIF : f = 175.164 MHz 2ndIF : f = 132 kHz Pin = –86 dBm Zin = 600 Ω , ZL = 2 kΩ VAGC = 0.5 V, VCC = 3.0 V VIQ–C = 0 V, TA = +25˚C –30 –20 0 100 –40 –10–50 10 Mag Duty (%) 2ndLO : f = 175.032 MHz 1stIF : f = 175.164 MHz 2ndIF : f = 132 kHz Pin = –90 dBm Zin = 600 Ω , ZL = 2 kΩ VAGC = 0.5 V, VCC = 3.0 V VIQ–C = 0 V, TA = +25˚C –30 –20 0 100 0 50 200 Mag Duty (%) 1stIF Input Frequency f1stIFin (MHz) 2ndIF : f = 132 kHz PLOin = 0 dBm PIF1stin = –86 dBm Zin = 600 Ω , ZL = 2 kΩ VAGC = 0.5 V, VCC = 3.0 V VIQ–C = 0 V, TA = +25˚C 100 150 100 0 50 200 Mag Duty (%) 2ndIF : f = 132 kHz PLOin = 0 dBm PIF1stin = –90 dBm Zin = 600 Ω , ZL = 2 kΩ VAGC = 0.5 V, VCC = 3.0 V VIQ–C = 0 V, TA = +25˚C 100 150 100 0 1 000 2ndIF : f = 132 kHz PLOin = 0 dBm PIF1stin = –86 dBm Zin = 600 Ω , ZL = 2 kΩ VAGC = 0.5 V, VCC = 3.0 V VIQ–C = 0 V, TA = +25˚C 100 100 0 1 000 2ndIF : f = 132 kHz PLOin = 0 dBm PIF1stin = –90 dBm Zin = 600 Ω , ZL = 2 kΩ VAGC = 0.5 V, VCC = 3.0 V VIQ–C = 0 V, TA = +25˚C 100 Mag Duty (%) LO Input Power PLOin (dBm) MAG DUTY vs. LO INPUT POWER LO Input Power PLOin (dBm) MAG DUTY vs. LO INPUT POWER MAG DUTY vs. 1stIF INPUT FREQUENCY 1stIF Input Frequency f1stIFin (MHz) MAG DUTY vs. 1stIF INPUT FREQUENCY Mag Duty (%) 2ndIF Output Frequency f2ndIFout (MHz) MAG DUTY vs. 2ndIF OUTPUT FREQUENCY Mag Duty (%) 2ndIF Output Frequency f2ndIFout (MHz) MAG DUTY vs. 2ndIF OUTPUT FREQUENCY Remark The graphs indicate nominal characteristics. Data Sheet PU10282EJ01V0DS 17 µPB1008K

Local leakage power (dBm) LO Input Power PLOin (dBm) LOCAL LEAKAGE POWER vs. LO INPUT POWER –10 –20 –30 –40 –70 –60 –100 –90 –50 –80 PIFout : VCC = 2.7 V 3.0 V 3.3 V LO in : f = 1 400.256 MHz TA = +25˚C 2.5 3.0 3.5 DCoffset Voltage (16, 17 pin) (mV) Supply Voltage VCC (dBm) DCOFFSET VOLTAGE (16, 17 pin) vs. SUPPLY VOLTAGE 1.5 1.0 0.5 –1.5 –1.0 –0.5 1stIFin : f = 175.164 MHz Pin = –60 dBm REF in : f = 27.456 MHz Pin = –10 dBm TA = +25˚C 2.5 3.0 3.5 1.5 1.0 0.5 –1.5 –1.0 –0.5 1stIFin : f = 175.164 MHz Pin = –60 dBm REF in : f = 27.456 MHz Pin = –10 dBm TA = +25˚C DCoffset Voltage (24, 25 pin) (mV) Supply Voltage VCC (dBm) DCOFFSET VOLTAGE (24, 25 pin) vs. SUPPLY VOLTAGE Remark The graphs indicate nominal characteristics. Data Sheet PU10282EJ01V0DS 18 µPB1008K

 IF BLOCK (ADC)  ADC OUTPUT WAVE FORM (2ndIFin : f = 132 kHz, Pin (I ch) = −45 dBm, Pin (Q ch) = 49 dBm, VCC = 3.0 V, TA = +25°C) I ch Q ch Sign bit Mega bit Remark The graphs indicate nominal characteristics. Data Sheet PU10282EJ01V0DS 19 µPB1008K

RF BLOCK (LNA + RF MIX) / IF BLOCK (AGCamp + IF MIX + IFamp + ADC) 12345678 9 26 25 24 23 22 21 20 19/2 /2PD /8/6/7/2 Vth 2-bit ADC Vth 2-bit ADC 4 pF 1 nF 100 nF Balun Transformer 1 nF 1 nF 100 nF 8.2 kΩ 100 nF 3.3 kΩ 100 nF VPDout 100 nF 100 nF VIQ-C 150 pF 100 pF 100 nF 100 nF 100 nF 100 nF 150 pF 100 pF

47 Fµ100 nF

Balun Transformer 1:4 1 nF 1 nF1 nF Balun Transformer 1:1 1 nF 1 nF 1 nF100 nF 200 Ω 6.8 nH Data Sheet PU10282EJ01V0DS 20 µPB1008K

PLL LOCK TYPE (C/N, VT) 12345678 9 26 25 24 23 22 21 20 19/2 /2PD /8/6/7/2 Vth 2-bit ADC Vth 2-bit ADC 4 pF 1 nF 100 nF 100 nF 100 nF 100 nF 100 nF 150 pF 100 pF 150 pF 100 pF Balun Transformer 1:4 1 nF 1 nF1 nF Balun Transformer 1:1 1 nF 1 nF 1 nF100 nF 200 Ω 6.8 nH 15 kΩ 18 pF 3.9 nH 15 kΩ 18 pF 3.9 nH 130 Ω 1 nF47 Fµ Data Sheet PU10282EJ01V0DS 21 µPB1008K

36-PIN PLASTIC QFN (UNIT: mm) 6.2±0.2 6.0±0.2 0.22±0.05 0.55±0.2 0.5 (Bottom View) 6.2±0.2 6.0±0.2 1.0MAX. 0.14+0.10 –0.05 6.2±0.2 6.0±0.2 6.2±0.2 6.0±0.2

36 Pin

1 Pin

Caution The island pins located on the corners are needed to fabricate products in our plant, but do not serve any other function. Consequently the island pins should not be soldered and should remain non-connection pins. Data Sheet PU10282EJ01V0DS 22 µPB1008K

(1) Observe precautions for handling because of electro-static sensitive devices. (2) Form a ground pattern as widely as possible to minimize ground impedance (to prevent abnormal oscillation). (3) Keep the wiring length of the ground pins as short as possible. (4) Connect a bypass capacitor to the VCC pin. (5) High-frequency signal I/O pins must be coupled with the external circuit using a coupling capacitor. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your nearby sales office. Soldering Method Soldering Conditions Condition Symbol Infrared Reflow Peak temperature (package surface temperature) : 260°C or below Time at peak temperature : 10 seconds or less Time at temperature of 220°C or higher : 60 seconds or less Preheating time at 120 to 180°C : 120 ±30 seconds Maximum number of reflow processes : 3 times Maximum chlorine content of rosin flux (% mass) : 0.2%(Wt.) or below IR260 VPS Peak temperature (package surface temperature) : 215 °C or below Time at temperature of 200°C or higher : 25 to 40 seconds Preheating time at 120 to 150°C : 30 to 60 seconds Maximum number of reflow processes : 3 times Maximum chlorine content of rosin flux (% mass) : 0.2%(Wt.) or below VP215 Wave Soldering Peak temperature (molten solder temperature) : 260 °C or below Time at peak temperature : 10 seconds or less Preheating temperature (package surface temperature) : 120°C or below Maximum number of flow processes : 1 time Maximum chlorine content of rosin flux (% mass) : 0.2%(Wt.) or below WS260 Partial Heating Peak temperature (pin temperature) : 350 °C or below Soldering time (per side of device) : 3 seconds or less Maximum chlorine content of rosin flux (% mass) : 0.2%(Wt.) or below HS350 Caution Do not use different soldering methods together (except for partial heating). Data Sheet PU10282EJ01V0DS 23 µPB1008K

M8E 00. 4 - 0110 The information in this document is current as of November, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard":Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific":Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation, NEC Compound Semiconductor Devices, Ltd. and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). Data Sheet PU10282EJ01V0DS 24 µPB1008K

NEC Compound Semiconductor Devices Hong Kong Limited E-mail: ncsd-hk@elhk.nec.com.hk (sales, technical and general) Hong Kong Head Office Taipei Branch Office Korea Branch Office TEL: +852-3107-7303 TEL: +886-2-8712-0478 FAX: +852-3107-7309 FAX: +886-2-2545-3859 NEC Electronics (Europe) GmbH http://www.ee.nec.de/ TEL: +49-211-6503-01 FAX: +49-211-6503-487 California Eastern Laboratories, Inc. http://www.cel.com/ TEL: +1-408-988-3500 FAX: +1-408-988-0279 0310 NEC Compound Semiconductor Devices, Ltd. http://www.ncsd.necel.com/ E-mail: salesinfo@ml.ncsd.necel.com (sales and general) techinfo@ml.ncsd.necel.com (technical) 5th Sales Group, Sales Division TEL: +81-44-435-1588 FAX: +81-44-435-1579 For further information, please contact µPB1008K