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U2A

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Renesas microcontroller Rev.1.00 June 16, 2025

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RH850U2A RENESAS

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Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 182

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Page 1 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 Section 1 Overview The RH850/U2A-EVA is an emulation device of RH850/U2A16 (516 pins), RH850/U2A16 (373 pins), RH850/U2A16 (292 pins), RH850/U2A8 (373 pins), RH850/U2A8 (292 pins), RH850/U2A6 (292 pins), RH850/U2A6 (176 pins), RH850/U2A6 (156 pins) and RH850/U2A6 (144 pins) production devices which are the single-chip microcontroller RH850 series from Renesas Electronics. This section describes an overview of the RH850/U2A-EV A (516 pins), RH850/U2A16 (516 pins), RH850/U2A16 (373 pins), RH850/U2A16 (292 pi ns), RH850/U2A8 (373 pi ns), RH850/U2A8 (292 pins), RH850/U2A6 (292 pins), RH850/U2A6 (176 pi ns), RH850/U2A6 (156 pins) and RH850/U2A6 (144 pins).

1.1 Outline

This product is a 32-bit single-chip microcontroller that incorporates mul tiple CPUs of the RH850 Series, code flash, data flash, RAM, DMA controllers, high-speed communication interfaces including CAN, FlexRay, Ethernet, RHSIF, LIN, SENT, PSI5S, PSI5, peripheral functions including A/D converters, timer units and many communication interfaces that are used in the automotive applications. This product also conforms to the Automotive Safety Integrity Level (ASIL) that is highly demanded in the recent automotive field (ASIL D level). (1) Includes multiple RH850 cores This product contains multi RH850G4MH2 cores (each CPU is referred to as CPU0 to CPU3 (U2A8, U2A6: CPU0 to CPU1) hereafter). Each CPU supports RISC-type instruction sets and have significantly improved the instruction execution speed with basic instructions (one clock cycle per instruction) and the optimized 10-stage pipeline configurations. Furthermore, this product also supports multiplication instructions using a 32-bit hardware multiplier, saturated product-sum operation instructions, and bit manipulation instructions as instructions best suited for various fields. In addition, this product also support CPU virtualization function. Two-byte basic instructions and high-level language instructions im prove object code efficiency for the C compiler and reduce the program size. Furthermore, this product is suited for advanced real-time control applications by offering a high-speed response time including the processing time of the on-chip interrupt controller. (2) On-chip code flash and data flash This product incorporates a 16-MB (U2A8: 8MB, U2A6: 6MB) code flash allowing high-speed accesses, which enables each CPU to access this flash memory efficiently. This memory can be reprogrammed while it is placed on an application system. This can shorten the system development period and significantly improve the serviceability after the system is delivered. This product also has a 576-KB (U2A8: 320-KB, U2A6: 256-KB) data flash that is available for storing EEPROM data. (3) Rich peripheral functionality This microcontroller supports common communication interfaces such as SPI (CSI), I2C as well as automotive oriented communication interfaces such as Ethernet, RHSIF, FlexRay, CAN-FD, LIN, CXPI, SENT, PSI5, PSI5S. As internal peripheral modules, this microcontroller have A/D Converter, Long-Term System Counter, Generic Timer Module, timer units and dedicated Peripheral Interconnect module which connects th e functionalities of these peripherals. It also has the global standard on-chip Nexus J TAG as a debug interface. This allows construction of systems without the need to provide these functions externally, which reduces cost, quantity of components, and PCB footprint. Datasheet RH850/U2A Renesas microcontroller

Page 2 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview (4) Functional safety support This product equips several dedicated functionalities including the Dual Core Lock Step configuration for the CPU, the memory protection with ECC, the bus protection with ECC/EDC, the peripheral module protection, and voltage / clock monitors to support the functional safety standard (ISO26262) required in the automotive applications. (5) Security support This product provides various security features and utilizes the Intelligent Cryptographic Unit/Master (ICUMHA) as an on-chip Hardware Security Module (HSM).

Page 3 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview

1.2 Application Fields

 Automotive field (including body control and chassis & safety)

1.3 Ordering Information

Table 1.1 Product Name List (1/2) Name Package On-Chip ROM Operating Temperature (Tj) External Oscillator Maximum Operating Frequency MSPI restriction SVR restriction

3 Note

(RH850/U2A-EVA) Plastic FBGA-516 0.8-mm ball pitch 25 mm × 25 mm (RENESAS code* 2 = PRBG0516GC-A) 16 MB max. 160°C 16/20/24/40 MHz

400 MHz Yes No * 4

(RH850/U2A-EVA) Plastic FBGA-516 0.8-mm ball pitch 25 mm × 25 mm (RENESAS code* 2 = PRBG0516GC-A) 16 MB max. 160°C 16/20/24/40 MHz

400 MHz No No —

(RH850/U2A16) Plastic FBGA-516 0.8-mm ball pitch 25 mm × 25 mm (RENESAS code* 2 = PRBG0516GC-A) 16 MB max. 150°C 16/20/24/40 MHz

400 MHz Yes Yes * 4

(RH850/U2A16) Plastic FBGA-373 0.8-mm ball pitch 21 mm × 21 mm 16 MB max. 150°C 16/20/24/40 MHz

400 MHz Yes Yes *

400 MHz No Yes * 4

(RH850/U2A16) Plastic FBGA-373 0.8-mm ball pitch 21 mm × 21 mm 16 MB max. 150°C 16/20/24/40 MHz

400 MHz No Yes *

(RH850/U2A16) Plastic FBGA-292 0.8-mm ball pitch 17 mm × 17 mm 16 MB max. 160°C 16/20/24/40 MHz (RH850/U2A16) Plastic FBGA-516 0.8-mm ball pitch 25 mm × 25 mm (RENESAS code* 2 = PRBG0516GD-A) 16 MB max. 150°C 16/20/24/40 MHz (RH850/U2A16) Plastic FBGA-373 0.8-mm ball pitch 21 mm × 21 mm 16 MB max. 150°C 16/20/24/40 MHz (RH850/U2A16) Plastic FBGA-292 0.8-mm ball pitch 17 mm × 17 mm 16 MB max. 160°C 16/20/24/40 MHz (RH850/U2A8) Plastic FBGA-373 0.8-mm ball pitch 21 mm × 21 mm 8 MB max. 150°C 16/20/24/40 MHz (RH850/U2A8) Plastic FBGA-292 0.8-mm ball pitch 17 mm × 17 mm 8 MB max. 160°C 16/20/24/40 MHz (RH850/U2A8) Plastic FBGA-373 0.8-mm ball pitch 21 mm × 21 mm 8 MB max. 150°C 16/20/24/40 MHz (RH850/U2A8) Plastic FBGA-292 0.8-mm ball pitch 17 mm × 17 mm 8 MB max. 160°C 16/20/24/40 MHz (RH850/U2A8) Plastic FBGA-373 0.8-mm ball pitch 21 mm × 21 mm 8 MB max. 150°C 16/20/24/40 MHz (RH850/U2A8) Plastic FBGA-292 0.8-mm ball pitch 17 mm × 17 mm 8 MB max. 160°C 16/20/24/40 MHz (RH850/U2A6) Plastic FBGA-292 0.8-mm ball pitch 17 mm × 17 mm 6 MB max. 160°C 16/20/24/40 MHz

Page 4 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview Note 1. Refer to RH850/U2A-EVA Group User’s Manual: Hardware Section 19.8, MSPI restrictions. Note 2. Refer to Section 4.1, Package Outline. Note 3. Refer to RH850/U2A-EVA Group User’s Manual: Hardware Section 10.10, SVR restriction. Note 4. As sales of these products is limited, please contact your sales representative first when considering these products for purchasing and project development. FBGA is hereafter referred to as BGA unless the complete abbreviation is required. The RH850/U2A-EV A series has 21 variants. Select the proper product according to the table below. Note 1. As sales of these products is limited, contac t your sales representative first when considering these products for purchasing and project development. R7F702302FAFK-C (RH850/U2A6) Plastic HLQFP-176 0.5 mm pin pitch 24 mm × 24 mm 6 MB max. 160°C 16/20/24/40 MHz (RH850/U2A6) Plastic LFBGA-156 0.65 mm ball pitch 10 mm × 10 mm 6 MB max. 160°C 16/20/24/40 MHz (RH850/U2A6) Plastic HLQFP-144 0.4 mm pin pitch 16 mm × 16 mm 6 MB max. 160°C 16/20/24/40 MHz Table 1.1 Product Name List (2/2) Name Package On-Chip ROM Operating Temperature (Tj) External Oscillator Maximum Operating Frequency MSPI restriction SVR restriction Table 1.2 RH850/U2A-EVA List Frequency Package FBGA-516 FBGA-373 FBGA-292 HLQFP-176 LFBGA-156 HLQFP-144

400 MHz R7F702Z19AEDBG

(RH850/U2A-EVA)*1 R7F702Z19BFDBG (RH850/U2A-EVA) R7F702300EBBG-C (RH850/U2A16)* R7F702300AEBBC-C (RH850/U2A16)* R7F702300BEBBC-C (RH850/U2A16) R7F702300EBBB-C (RH850/U2A16)*1 R7F702300AEBBB-C (RH850/U2A16)*1 R7F702300BEBBB-C (RH850/U2A16) R7F702301EBBA-C (RH850/U2A8)*1 R7F702301AEBBA-C (RH850/U2A8)*1 R7F702301BEBBA-C (RH850/U2A8) R7F702300EABA-C (RH850/U2A16)* R7F702300AFABA-C (RH850/U2A16)*1 R7F702300BFABA-C (RH850/U2A16) R7F702301EABG-C (RH850/U2A8)*1 R7F702301AFABG-C (RH850/U2A8)*1 R7F702301BFABG-C (RH850/U2A8) R7F702302FABB-C (RH850/U2A6) R7F702302FAF K-C (RH850/ U2A6) R7F702302FAB D-C (RH850/ U2A6) R7F702302FAF M-C (RH850/ U2A6)

Page 5 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview

1.4 Differences in the Specifications of RH850/U2A-EVA Products

The table below lists the differences in the specifications of RH850/U2A-EV A products. (1/3) Product RH850/ U2A-EVA 516 pins RH850/ U2A16 516 pins RH850/ U2A16 373 pins RH850/ U2A16 292 pins RH850/ U2A8 373 pins RH850/ U2A8 292 pins RH850/ U2A6 292 pins RH850/ U2A6 176 pins RH850/ U2A6 156 pins RH850/ U2A6 144 pins CPU Frequency 400 400 400 400 400 400 400 400 400 400 M a i n C o r e 4444222222 L o c k s t e p 4444222222 F P U 4444222222 Instruction Cache per core (for Code Flash) 16 KB (PBS 4w) 16 KB (PBS 4w) 16 KB (PBS 4w) 16 KB (PBS 4w) 16 KB (PBS 4w) 16 KB (PBS 4w) 16 KB (PBS 4w) 16 KB (PBS 4w) 16 KB (PBS 4w) 16 KB (PBS 4w) Data Buffer per core (for Code Flash) 4 lines (256 bit/ line) 4 lines (256 bit/ line) 4 lines (256 bit/ line) 4 lines (256 bit/ line) 4 lines (256 bit/ line) 4 lines (256 bit/ line) 4 lines (256 bit/ line) 4 lines (256 bit/ line) 4 lines (256 bit/ line) 4 lines (256 bit/ line) MPU regions per core 32 32 32 32 32 32 32 32 32 32 I P I R U n i t 1111111111 B A R R U n i t 1111111111 T P T M U n i t 1111111111 RAM Total RAM (Local RAM + Cluster RAM)

3584 KB 3584 KB 3584 KB 3584 KB 1792 KB 1792 KB 768 KB 768 KB 768 KB 768 KB

Local RAM per core 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB Cluster RAM (CRAM) Total Size (Retention RAM included)

3328 KB 3328 KB 3328 KB 3328 KB 1664 KB 1664 KB 640 KB 640 KB 640 KB 640 KB

(included in CRAM)

256 KB 256 KB 256 KB 256 KB 128 KB 128 KB 128 KB 128 KB 128 KB 128 KB

Cluster Emulation RAM 2 MB (1 MB for each cluster 0 & No No No No No 32 KB (cluster 0) 32 KB (cluster 0) 32 KB (cluster 0) 32 KB (cluster 0) Global Emulation RAM 2 MB No No No No No No No No No Instrumentation RAM 96 KB No No No No No No No No No Trace RAM 64 KB No No No No No 32 KB 32 KB 32 KB 32 KB Flash Code Flash 16 MB 16 MB 16 MB 16 MB 8 MB 8 MB 6 MB 6 MB 6 MB 6 MB Data Flash Total Size 576 KB 576 KB

576 KB 576 KB 320 KB 320 KB 256 KB 256 KB 256 KB 256 KB

64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB

DMA sDMAC Channels 32 32 32 32 32 32 32 32 32 32 DTS Channels 128 128 128 128 128 128 128 128 128 128 I/O port 301 301 221 165 221 165 165 129 77 97 Timer ENCA Units 2 2 2 2 2 2 2 1 No 1 O S T M U n i t s 1 01 01 01 08 8 8 8 8 8 W D T B U n i t s 5555333333 LTSC Unit 1 1 1 1 1 1 1 1 1 1 S W D T U n i t 1111111111 G T M U n i t 1111111111 T A P A U n i t s 4444444322 T P B A U n i t s 2222222222 TAUD Units 3 3 3 3 3 3 3 3 3 3 TAUJ Units 4 4 4 4 4 4 4 4 4 4 T S G 3 U n i t s 2222222211 PWM- Diag U n i t s 9 69 69 69 69 69 69 67 65 06 4 R T C A U n i t 1111111111

Page 6 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview Communi cation S C I 3 U n i t s 333333N o N o N o N o RLIN3 Units 24 24 24 12 24 12 12 12 8 10 C X P I U n i t s 444444N o N o N o N o MSPI Units 10 10 9 6 9 6 6 6 6 4 R H S I F U n i t 111111N o N o N o N o RS- CANFD Units [Channels] 2 [16ch] 2 [16ch] 2 [16ch] 2 [16ch] 2 [16ch] 2 [16ch] 2 [12ch] 2 [11ch] 2 [8ch] 2 [7ch] FlexRay Units [Channels] 2 [4ch] 2 [4ch] 2 [4ch] 2 [4ch] 2 [4ch] 2 [4ch] 1 [2ch] 1 [2ch] 1 [2ch] 1 [2ch] Ethernet Channel (100Mb/ 1Gb) 1/1 1/1 1/1 1/1 1/1 1/1 1/0 1/0 No 1/0 ETNB0 (MII/ RMII/SGMII) Yes/Yes/ No Yes/Yes/ No Yes/Yes/ No Yes/Yes/ No Yes/Yes/ No Yes/Yes/ No Yes/Yes/ No Yes/Yes/ No No/No/No Yes/Yes/ No ETNB1 (MII/ RMII/SGMII) Yes/No/ Yes Yes/No/ Yes No/No/ Yes No/No/ Yes No/No/ Yes No/No/ Yes No/No/No No/No/No No/No/No No/No/No R S E N T U n i t s 8888888886 PSI5 Channels 4 4 4 4 4 4 4 4 4 3 P S I 5 S U n i t s 2222222111 R I I C U n i t s 2222222221 e M M C U n i t 11111111N o N o S F M A U n i t 11111111N o N o S a f e t y A S I L l e v e l N / A DDDDDDDDD ECM Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes CRC(KC RC) U n i t s 8888888888 Clock Monitor Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Error injection for self- diagnosis of several safety mechanisms Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes LBIST Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes MBIST Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Bus ECC Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes ADC ADCJ Units 3 3 3 3 3 3 3 3 2 3 ADCJ0/1/2 (Channels) (High accuracy inputs) 20/20/20 20/20/20 20/20/20 20/20/5 20/20/20 20/20/5 20/20/5 14/14/5 8/8/0 10/10/0 ADCJ0/1/2 (Low accuracy inputs) 10/14/10 10/14/10 10/14/10 10/14/10 10/14/10 10/14/10 10/14/10 10/14/7 6/7/0 3/10/6 Total inputs 94 94 94 79 94 79 79 64 29 39 Virtual channels per unit 64 64 64 64 64 64 64 64 64 64 A D C t i m e r s 2222222222 Debug Nexus-JTAG Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Trace I/F (Aurora) 4 lanes No No No No No No No No No Low Pin Debug I/F (4- pin) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Bypass I/F (AUDR) Yes No No No No No No No No No Security Basic Hardware Protection (BHP) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes ICUMHA Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Secure RAM 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB Secure Data Flash 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB Code Flash Protection Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes System Control Temp Sensor Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Voltage Monitor Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes LPS Yes Yes Yes Yes Yes Yes Yes Yes No Yes (2/3) Product RH850/ U2A-EVA 516 pins RH850/ U2A16 516 pins RH850/ U2A16 373 pins RH850/ U2A16 292 pins RH850/ U2A8 373 pins RH850/ U2A8 292 pins RH850/ U2A6 292 pins RH850/ U2A6 176 pins RH850/ U2A6 156 pins RH850/ U2A6 144 pins

Page 7 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview Note 1. For product names, refer to Section 1.3, Ordering Information. BGA373 No No Yes No Yes No No No No No BGA292 No No No Yes No Yes Yes No No No HLQFP176 No No No No No No No Yes No No BGA156 No No No No No No No No Yes No HLQFP144 No No No No No No No No No Yes (3/3) Product RH850/ U2A-EVA 516 pins RH850/ U2A16 516 pins RH850/ U2A16 373 pins RH850/ U2A16 292 pins RH850/ U2A8 373 pins RH850/ U2A8 292 pins RH850/ U2A6 292 pins RH850/ U2A6 176 pins RH850/ U2A6 156 pins RH850/ U2A6 144 pins

Page 8 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview

1.5 Pin Connection Diagram (Top View)

Figure 1.1 Pin Connection Diagram (BGA516 U2A-EVA) 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 22 32 42 52 62 72 82 93 0 A VSS VSS P21_13 VSS P23_0 P23_1 P23_3 P23_5 P23_7 P23_9 P23_11 P23_13 P8_0 P8_1 P8_3 P8_5 P8_7 P8_9 VSS AUDCK AUDRST AUDATA2 AUDATA0 EVTI MSYN P0_1 P0_3 P0_4 VSS VSS A B VSS VSS P20_15 P21_12 VSS E1VCC P23_2 P23_4 P23_6 P23_8 P23_10 P23_12 VSS P8_2 P8_4 P8_6 P8_8 P8_10 VSS VSS AUDSYNC AUDATA3 AUDATA1 EVTO P0_0 P0_2 VSS E0VCC VSS VSS B C P11_0 P11_1 P0_6 P0_5 C D P11_2 P11_3 P0_8 P0_7 D E P11_4 P11_5 P0_10 P0_9 E F P11_6 P11_7 VSS VSS ERROROUT_M VSS P20_12 P20_9 P20_7 P20_5 P20_3 P20_1 P2_15 P2_13 P2_11 SVRDRVSS SVRPGATE SVRNGATE SVRAVSS AWOVCL VSS VSS P0_12 P0_11 F G P11_8 P11_9 VSS P20_14 VSS P20_13 P20_10 P20_8 P20_6 P20_4 P20_2 P20_0 P2_14 P2_12 P2_10 P2_8 SVRDRVCC SVRAVCC P2_2 P2_0 P5_6 VSS VSS A URORESPD G H P11_10 P11_11 P10_0 P10_1 P2_1 P5_4 VSS EMUVCC H J P11_12 P11_13 P10_2 P10_3 VSS P21_4 P21_3 P21_2 P21_1 P21_0 P22_2 P22_4 LVDVCC P2_9 P2_7 P2_5 P2_3 VSS P5_3 P5_2 AURORES1 AURORES2 J K P11_14 P11_15 P10_4 P10_5 P21_5 VSS VCC VSS E1VCC P22_0 P22_1 P22_3 E0VCC VSS P2_6 P2_4 VSS GETH0VCL PWRCTL X1 VSS EMUVDD K L P19_1 P19_0 P10_6 P10_7 P21_6 VSS SYSVCC VMONOUT FLMD0 X 2 VSS VSS L M P19_3 P19_2 P10_8 P10_9 P21_7 VCC VSS VDD VDD VDD VDD VDD VSS GETH0PVCC P3_8 RESET VSS VSS M N P19_5 P19_4 P10_10 P10_11 P17_6 VSS VSS VSS VSS VSS VSS VSS TX_DATAP GETH0RVCC TRST JP0_0 TODP0 TODN0 N P P18_14 P18_15 P10_12 P10_13 P17_5 E1VCC VDD VSS VSS VSS RX_CLKP TX_DATAN RX_DATAP JP0_1 JP0_2 DVDD DVDD P R P18_12 P18_13 P10_14 P17_0 P17_2 VDD VDD VSS VSS VSS VSS VSS RX_CLKN GETH0BVCC RX_DATAN JP0_3 JP0_5 TODP1 TODN1 R T P18_10 P18_11 P17_1 AP2_13 P17_4 P17_3 VDD VSS VSS VSS VSS VSS VSS VDD P3_7 VSS P6_14 P6_13 VSS VSS T U P18_8 P18_9 AP2_10 AP2_11 AP2_14 VCC VDD VSS VSS VSS VSS VSS VSS VDD E0VCC P3_6 P6_10 P6_15 TODP2 TODN2 U V P18_6 P18_7 AP2_8 AP2_9 AP2_15 VSS VSS VSS VSS VSS VSS VSS VSS P6_0 P6_12 P6_9 DVDD DVDD V W P18_4 P18_5 AP2_6 AP2_7 AP3_0 AP3_1 VSS ERAMVDD VDD VDD AWOVCL VSS VDD AP4_1 P6_8 P6_7 TODP3 TODN3 W Y P18_2 P18_3 AP2_4 AP2_5 AP3_2 AP2_12 AP4_0 AP4_2 P6_6 P6_5 VSS VSS Y AA P18_1 E1VCC AP2_2 AP2_3 AP3_3 A0VSS A0VSS AP1_1 AP0_15 AP0_13 E0VCC P24_7 E2VCC P24_9 P24_11 AP4_4 A2VSS AP4_3 P6_4 P6_3 CICREFP CICREFN AA AB P18_0 VSS A1VCC AP2_1 A0VSS AP1_3 AP1_2 AP1_0 AP0_14 AP0_12 P24_4 P24_5 P24_6 P24_8 P24_10 P24_12 P24_13 A2VSS A2VCC P6_2 VSS VSS AB AC P9_8 VSS A1VREFH AP2_0 A2VREFH P6_11 DVCC DVCC AC AD P9_7 P9_6 A1VSS A1VSS A0VSS AP0_0 AP0_2 AP0_4 AP0_6 AP0_8 AP0_10 P3_2 P4_0 P4_4 P4_6 P4_8 P4_10 P4_12 P4_14 P3_4 P3_5 A2VSS AP4_5 AP4_6 AD AE P9_5 P9_4 A1VSS A0VSS A0VREFH A0VCC AP0_1 AP0_3 AP0_5 AP0_7 AP0_9 AP0_11 P3_3 P4_1 P4_5 P4_7 P4_9 P4_11 P4_13 P4_15 A2VSS A2VSS AP4_7 AP4_8 AE AF P9_3 P9_2 AP4_9 AP4_10 AF AG P9_1 P9_0 AP4_11 AP4_12 AG AH A1VCC A1VCC A2VCC A2VCC AH AJ A1VSS A0VSS A0VCC P12_4 P12_2 P12_0 ERAMVCC VSS ERAMVDD P1_0 P1_2 P1_4 P1_6 P1_8 P1_10 P1_12 E0VCC VSS P4_2 P3_14 P3_12 P3_10 P3_1 VSS AP5_3 AP5_1 AP4_ 15 AP4_13 A2VSS A2VSS AJ AK A1VSS A0VSS A0VCC P12_5 P12_3 P12_1 VSS ERA MRESPD ERA MRES2 P1_1 P1_3 P1_5 P1_7 P1_9 P1_11 P1_13 P1_14 P1_15 P4_3 P3_15 P3_13 P3_11 P3_9 P3_0 VSS AP5_2 AP5_0 AP4_14 A2VSS A2VSS AK 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 22 32 42 52 62 72 82 93 0

Page 9 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview Note: The pin location of RX_DATAP, RX_DATAN, TX_DATAP and TX_DATAN is defined by the Option Byte 14. For details, refer to RH850/U2A-EVA Group User's Manual: Hardware Section 51.12.20, OPBT14 — Option Byte 14. Figure 1.2 Pin Connecti on Diagram (BGA516 U2A16) 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 A VSS VSS P21_13 VSS P23_0 P23_1 P23_3 P23_5 P23_7 P23_9 P23_11 P23_13 P8_0 P8_1 P8_3 P8_5 P8_7 P8_9 VSS VSS VSS VSS VSS EVTI VSS P0_1 P0_3 P0_4 VSS VSS A B VSS VSS P20_15 P21_12 VSS E1VCC P23_2 P23_4 P23_6 P23_8 P23_10 P23_12 VSS P8_2 P8_4 P8_6 P8_8 P8_10 VSS VSS VSS VSS VSS EVTO P0_0 P0_2 VSS E0VCC VSS VSS B C P11_0 P11_1 P0_6 P0_5 C D P11_2 P11_3 P0_8 P0_7 D E P11_4 P11_5 P0_10 P0_9 E F P11_6 P11_7 VSS VSS VSS P20_12 P20_9 P20_7 P20_5 P20_3 P20_1 P2_15 P2_13 P2_11 SVRDRVSS SVRAVSS AWOVCL VSS VSS P0_12 P0_11 F G P11_8 P11_9 VSS P20_14 VSS P20_13 P20_10 P20_8 P20_6 P20_4 P20_2 P20_0 P2_14 P2_12 P2_10 P2_8 SVRDRVCC SVRAVCC P2_2 P2_0 P5_6 VSS VSS VSS G H P11_10 P11_11 P10_0 P10_1 P2_1 P5_4 VSS E0VCC J P11_12 P11_13 P10_2 P10_3 VSS P21_4 P21_3 P21_2 P21_1 P21_0 P22_2 P22_4 LVDVCC P2_9 P2_7 P2_5 P2_3 VSS P5_3 P5_2 VSS VSS J K P11_14 P11_15 P10_4 P10_5 P21_5 VSS VCC VSS E1VCC P22_0 P22_1 P22_3 E0VCC VSS P2_6 P2_4 VSS GETH0VCL PWRCTL X1 VSS VDD K L P19_1 P19_0 P10_6 P10_7 P21_6 VSS SYSVCC VMONOUT FLMD0 X 2 VSS VSS L M P19_3 P19_2 P10_8 P10_9 P21_7 VCC VSS VDD VDD VDD VDD VDD VSS GETH0PVCC P3_8 RESET VSS VSS M N P19_5 P19_4 P10_10 P10_11 P17_6 VSS VSS VSS VSS VSS VSS VSS GETH0RVCC TRST JP0_0 VSS VSS N P P18_14 P18_15 P10_12 P10_13 P17_5 E1VCC VDD VSS VSS VSS VSS VDD JP0_1 JP0_2 VDD VDD P R P18_12 P18_13 P10_14 P17_0 P17_2 VDD VDD VSS VSS VSS VSS VSS VSS VDD GETH0BVCC JP0_3 JP0_5 VSS VSS R T P18_10 P18_11 P17_1 AP2_13 P17_4 P17_3 VDD VSS VSS VSS VSS VSS VSS VDD P3_7 VSS P6_14 P6_13 VSS VSS T U P18_8 P18_9 AP2_10 AP2_11 AP2_14 VCC VDD VSS VSS VSS VSS VDD E0VCC P3_6 P6_10 P6_15 VSS VSS U V P18_6 P18_7 AP2_8 AP2_9 AP2_15 VSS VSS VSS VSS VSS VSS VSS VSS P6_0 P6_12 P6_9 VDD VDD V W P18_4 P18_5 AP2_6 AP2_7 AP3_0 AP3_1 VSS VDD VDD VDD AWOVCL VSS VDD AP4_1 P6_8 P6_7 VSS VSS W Y P18_2 P18_3 AP2_4 AP2_5 AP3_2 AP2_12 AP4_0 AP4_2 P6_6 P6_5 VSS VSS Y AA P18_1 E1VCC AP2_2 AP2_3 AP3_3 A0VSS A0VSS AP1_1 AP0_15 AP0_13 E0VCC P24_7 E2VCC P24_9 P24_11 AP4_4 A2VSS AP4_3 P6_4 P6_3 VSS VSS AA AB P18_0 VSS A1VCC AP2_1 A0VSS AP1_3 AP1_2 AP1_0 AP0_14 AP0_12 P24_4 P24_5 P24_6 P24_8 P24_10 P24_12 P24_13 A2VSS A2VCC P6_2 VSS VSS AB AC P9_8 VSS A1VREFH AP2_0 A2VREFH P6_11 AC AD P9_7 P9_6 A1VSS A1VSS A0VSS AP0_0 AP0_2 AP0_4 AP0_6 AP0_8 AP0_10 P3_2 P4_0 P4_4 P4_6 P4_8 P4_10 P4_12 P4_14 P3_4 P3_5 A2VSS AP4_5 AP4_6 AD AE P9_5 P9_4 A1VSS A0VSS A0VREFH A0VCC AP0_1 AP0_3 AP0_5 AP0_7 AP0_9 AP0_11 P3_3 P4_1 P4_5 P4_7 P4_9 P4_11 P4_13 P4_15 A2VSS A2VSS AP4_7 AP4_8 AE AF P9_3 P9_2 AP4_9 AP4_10 AF AG P9_1 P9_0 AP4_11 AP4_12 AG AH A1VCC A1VCC A2VCC A2VCC AH AJ A1VSS A0VSS A0VCC P12_4 P12_2 P12_0 E0VCC VSS VDD P1_0 P1_2 P1_4 P1_6 P1_8 P1_10 P1_12 E0VCC VSS P4_2 P3_14 P3_12 P3_10 P3_1 VSS AP5_3 AP5_1 AP4_15 AP4_ 13 A2VSS A2VSS AJ AK A1VSS A0VSS A0VCC P12_5 P12_3 P12_1 VSS VSS VSS P1_1 P1_3 P1_5 P1_7 P1_9 P1_11 P1_13 P1_14 P1_15 P4_3 P3_15 P3_13 P3_11 P3_9 P3_0 VSS AP5_2 AP5_0 AP4_14 A2VSS A2VSS AK 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 ERROROUT_M SVRPGATE SVRNGATE TX_DATAN TX_DATAP RX_DATAN RX_DATAP H E0VCC E0VCC

Page 10 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview Note: The pin location of RX_DATAP, RX_DATAN, TX_DATAP and TX_DATAN is defined by the Option Byte 14. For details, refer to RH850/U2A-EVA Group User's Manual: Hardware Section 51.12.20, OPBT14 — Option Byte 14. Figure 1.3 Pin Connection Di agram (BGA373 U2A16/U2A8) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A VSS VSS VSS P20_12 P20_7 P20_5 P8_1 P8_3 P8_5 P8_7 P8_9 P2_15 P2_13 P2_11 SVRDRVSS SVRPGATE SVRNGATE SVRAVSS P0_1 VSS AWOVCL P2_1 VSS VSS A B VSS VSS VSS VSS P21_3 P21_1 P20_4 P8_0 P8_2 P8_4 P8_6 P8_8 P2_14 P2_12 P2_10 SVRDRVSS SVRDRVCC SVRAVCC SVRAVSS P0_2 P0_3 P2_2 P2_0 VSS VSS B C P11_1 P11_0 VSS P21_2 P20_9 P20_8 P20_6 P22_0 P21_0 P20_2 P20_3 P20_0 P20_1 P2_9 P2_8 P2_6 SVRDRVCC SVRAVCC P0_0 P0_4 P2_4 P2_3 VSS P0_6 P0_5 C D V C C V D V L 7 _ 2 P 3 _ 2 2 P 4 _ 2 2 P 1 _ 2 2 P 2 _ 2 2 P C C V 1 E C C V 1 E S S V C C V S S VS S V 2 _ 1 1 P 3 _ 1 1 P 7 _ 0 P 8 _ 0 P 6 _ 5 P5 _ 2 P S S V C C V 0 E S S D E P11_5 P11_4 P20_10 P5_4 P0_10 P0_9 E F P11_7 P11_6 P20_14 P20_13 VSS P5_3 P5_2 P0_12 F G P11_9 P11_8 P10_1 P21_4 VSS P0_11 PWRCTL FLMD0 G H P11_11 P11_10 P10_0 P21_5 SYSVCC VMONOUT RESET X1 H J P11_13 P11_12 P10_3 VSS GETH0VCL GETH0PVCC P3_8 X2 J K S S V D D V D D V D D V D D V D D V S S VC C V 6 _ 1 2 P 4 1 _ 1 1 P 5 1 _ 1 1 P GETH0RVCC GETH0BVCC VSS VSS K L S S V S S VD D V S S V S S V S S V S S V S S V D D VS S V 5 _ 0 1 P 4 _ 0 1 P 2 _ 0 1 P TX_DATAN TX_DATAP L M S S V S S VD D V S S V S S V S S V S S V S S V D D VC C V 1 E 6 _ 0 1 P 7 _ 1 2 P 7 _ 0 1 P RX_DATAN RX_DATAP M N S S V S S V S S V 1 _ 0 P JD D V S S V S S V S S V S S V S S V D D VD D V 8 _ 0 1 P 6 _ 7 1 P 9 _ 0 1 P N P 0 _ 0 P J 2 _ 0 P J 3 _ 0 P JD D V S S V S S V S S V S S V S S V D D V2 1 _ 0 1 P 3 1 _ 0 1 P 0 1 _ 0 1 P 1 1 _ 0 1 P TRST P R 3 1 _ 6 P 5 _ 0 P J 4 1 _ 6 P S S VD D V S S V S S V S S V S S V S S V D D V1 _ 7 1 P 3 _ 7 1 P 4 1 _ 0 1 P 5 _ 7 1 P R T 5 1 _ 6 P 7 _ 3 P 0 1 _ 6 P C C V 0 ES S V L C V O W A D D V D D V D D V D D V S S VC C V 4 _ 7 1 P 2 _ 7 1 P 0 _ 7 1 P T U AP2_13 AP2_10 AP2_14 VSS VSS P6_12 P6_9 P3_6 U V AP2_11 AP2_15 AP2_9 AP3_0 VDD P6_5 P6_8 P6_7 V W AP2_8 AP2_6 AP2_4 AP2_5 P6_4 P6_11 P6_6 P6_0 W Y AP2_7 AP3_1 AP2_0 AP2_3 AP4_1 AP4_6 P6_2 P6_3 Y AA AP2_2 AP3_2 AP2_1 AP4_2 AP4_8 AP4_5 AA AB 2 P C C V 2 E 8 _ 4 2 P C C V 0 E S S V 3 1 _ 0 P A 4 1 _ 0 P A 5 1 _ 0 P A 2 _ 0 P A 2 _ 1 P A3 _ 3 P A C C V 1 A C C V 1 A 7 _ 4 P A 9 _ 4 P A 0 1 _ 4 P A0 _ 5 P A 1 _ 5 P A 3 1 _ 4 2 P 2 1 _ 4 2 P 1 1 _ 4 2 P 0 1 _ 4AB AC A1VREFH A1VCC A1VSS A0VSS AP2_12 AP1_3 AP0_0 AP1_0 AP0_8 P24_7 P24_9 P4_11 P4_12 P4_15 P3_5 AP5_2 AP4_4 AP4_0 A2VSS A2VSS AP4_11 AP4_12 AC AD A1VSS A1VSS A0VSS A0VCC A0VCC AP1_1 AP0_4 AP0_6 AP0_9 AP0_11 P3_3 P24_4 P24_6 P4_6 P4_8 P4_10 P4_14 P3_4 AP5_3 AP4_3 AP4_14 A2VCC A2VCC A2VSS A2VSS AD AE A1VSS A0VSS A0VSS A0VREFH A0VCC AP0_1 AP0_3 AP0_5 AP0_7 AP0_12 P4_1 P4_0 P4_5 P4_7 P4_9 P4_13 P3_1 P3_0 AP4_15 AP4_13 A2VCC A2VREFH A2VSS A2VSS AE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AP0_10 P3_2 P24_5 P4_4 ERROROUT_M

Page 11 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview Note: The pin location of RX_DATAP, RX_DATAN, TX_DATAP and TX_DATAN is defined by the Option Byte 14. For details, refer to RH850/U2A-EVA Group User's Manual: Hardware Section 51.12.20, OPBT14 — Option Byte 14. Figure 1.4 Pin Connection Di agram (BGA292 U2A16/U2A8) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 AV S S V S S VSS P20_12 P20_9 P20_7 P20_5 P20_3 P20_1 P2_15 P2_13 P2_11 SVRDRVSS SVRPGATE SVRAVSS AWOVCL VSS VSS A B VSS P20_14 VSS P20_13 P20_10 P20_8 P20_6 P20_4 P20_2 P20_0 P2_14 P2_12 P2_10 P2_8 SVRDRVCC SVRAVCC P2_2 P2_0 P5_6 VSS B C P10_0 P10_1 P2_1 P5_4 C D P10_2 P10_3 VSS P21_4 P21_3 P21_2 P21_1 P21_0 P22_2 P22_4 LVDVCC P2_9 P2_7 P2_5 P2_3 VSS P5_3 P5_2 D E P10_4 P10_5 P21_5 VSS VCC VSS E1VCC P22_0 P22_1 P22_3 E0VCC VSS P2_6 P2_4 VSS GETH0VCL PWRCTL X1 E F P10_6 P10_7 P21_6 VSS SYSVCC VMONOUT FLMD0 X2 F G P10_8 P10_9 P21_7 VCC VSS VDD VDD VDD VDD VDD VSS GETH0 PVCC GETH0 RVCC GETH0 BVCC P3_8 RESET G H P10_10 P10_11 P17_6 VSS VSS VSS VSS VSS VSS VSS TX_DATAN TRST JP0_0 H J P10_12 P10_13 P17_5 E1VCC VDD VSS VSS VSS VSS VDD TX_DATAP JP0_1 JP0_2 J K P10_14 P17_0 P17_2 VDD VDD VSS VSS VSS VSS VSS VSS VDD RX_DATAP JP0_3 JP0_5 K L P17_1 AP2_13 P17_4 P17_3 VDD VSS VSS VSS VSS VSS VSS VDD P3_7 VSS P6_14 P6_13 L M AP2_10 AP2_11 AP2_14 VCC VDD VSS VSS VSS VSS VDD E0VCC P3_6 P6_10 P6_15 M N AP2_8 AP2_9 AP2_15 VSS VSS VSS VSS VSS VSS VSS VSS P6_0 P6_12 P6_9 N P AP2_6 AP2_7 AP3_0 AP3_1 VSS VDD VDD VDD AWOVCL VSS VDD AP4_1 P6_8 P6_7 P R AP2_4 AP2_5 AP3_2 AP2_12 AP4_0 AP4_2 P6_6 P6_5 R T AP2_2 AP2_3 AP3_3 A0VSS A0VSS AP1_1 AP0_15 AP0_13 E0VCC P24_7 E2VCC P24_9 P24_11 AP4_4 A2VSS AP4_3 P6_4 P6_3 T U A1VCC AP2_1 A0VSS AP1_3 AP1_2 AP1_0 AP0_14 AP0_12 P24_4 P24_5 P24_6 P24_8 P24_10 P24_12 P24_13 A2VSS A2VCC P6_2 U V A1VREFH AP2_0 A2VREFH P6_11 V W A1VSS A1VSS A0VSS AP0_0 AP0_2 AP0_4 AP0_6 AP0_8 AP0_10 P3_2 P4_0 P4_4 P4_6 P4_8 P4_10 P4_12 P4_14 P3_4 P3_5 A2VSS W Y A1VSS A0VSS A0VREFH A0VCC AP0_1 AP0_3 AP0_5 AP0_7 AP0_9 AP0_11 P3_3 P4_1 P4_5 P4_7 P4_9 P4_11 P4_13 P4_15 A2VSS A2VSS Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SVRNGATE RX_DATAN ERROROUT_M

Page 12 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview Figure 1.5 Pin Connecti on Diagram (BGA292 U2A6) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 AV S S V S S VSS P20_12 P20_9 P20_7 P20_5 P20_3 P20_1 P2_15 P2_13 P2_11 SVRDRVSS SVRPGATE SVRAVSS AWOVCL VSS VSS A B VSS P20_14 VSS P20_13 P20_10 P20_8 P20_6 P20_4 P20_2 P20_0 P2_14 P2_12 P2_10 P2_8 SVRDRVCC SVRAVCC P2_2 P2_0 P5_6 VSS B C P10_0 P10_1 P2_1 P5_4 C D P10_2 P10_3 VSS P21_4 P21_3 P21_2 P21_1 P21_0 P22_2 P22_4 E0VCC P2_9 P2_7 P2_5 P2_3 VSS P5_3 P5_2 D E P10_4 P10_5 P21_5 VSS VCC VSS E1VCC P22_0 P22_1 P22_3 E0VCC VSS P2_6 P2_4 VSS VSS PWRCTL X1 E F P10_6 P10_7 P21_6 VSS SYSVCC VMONOUT FLMD0 X2 F G P10_8 P10_9 P21_7 VCC VSS VDD VDD VDD VDD VDD VSS E0VCC E0VCC E0VCC P3_8 RESET G H P10_10 P10_11 P17_6 VSS VSS VSS VSS VSS VSS VSS E0VCC TRST JP0_0 H J P10_12 P10_13 P17_5 E1VCC VDD VSS VSS VSS VSS VDD E0VCC JP0_1 JP0_2 J K P10_14 P17_0 P17_2 VDD VDD VSS VSS VSS VSS VSS VSS VDD VSS JP0_3 JP0_5 K L P17_1 AP2_13 P17_4 P17_3 VDD VSS VSS VSS VSS VSS VSS VDD P3_7 VSS P6_14 P6_13 L M AP2_10 AP2_11 AP2_14 VCC VDD VSS VSS VSS VSS VDD E0VCC P3_6 P6_10 P6_15 M N AP2_8 AP2_9 AP2_15 VSS VSS VSS VSS VSS VSS VSS VSS P6_0 P6_12 P6_9 N P AP2_6 AP2_7 AP3_0 AP3_1 VSS VDD VDD VDD AWOVCL VSS VDD AP4_1 P6_8 P6_7 P R AP2_4 AP2_5 AP3_2 AP2_12 AP4_0 AP4_2 P6_6 P6_5 R T AP2_2 AP2_3 AP3_3 A0VSS A0VSS AP1_1 AP0_15 AP0_13 E0VCC P24_7 E2VCC P24_9 P24_11 AP4_4 A2VSS AP4_3 P6_4 P6_3 T U A1VCC AP2_1 A0VSS AP1_3 AP1_2 AP1_0 AP0_14 AP0_12 P24_4 P24_5 P24_6 P24_8 P24_10 P24_12 P24_13 A2VSS A2VCC P6_2 U V A1VREFH AP2_0 A2VREFH P6_11 V W A1VSS A1VSS A0VSS AP0_0 AP0_2 AP0_4 AP0_6 AP0_8 AP0_10 P3_2 P4_0 P4_4 P4_6 P4_8 P4_10 P4_12 P4_14 P3_4 P3_5 A2VSS W Y A1VSS A0VSS A0VREFH A0VCC AP0_1 AP0_3 AP0_5 AP0_7 AP0_9 AP0_11 P3_3 P4_1 P4_5 P4_7 P4_9 P4_11 P4_13 P4_15 A2VSS A2VSS Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SVRNGATE VSS ERROROUT_M

Page 13 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview Note: The Exposed Pad shall be connected to VSS. Figure 1.6 Pin Connection Diagram (QFP176 U2A6) ERROROUT_M VSS VCC P20_13 P20_12 P21_2 P20_10 P21_1 P20_9 P20_8 VDD P20_6 P21_0 P20_7 E1VCC P20_5 P20_4 P20_3 P20_2 P20_1 VDD VDD P2_12 P2_14 P2_13 E0VCC P2_11 P2_8 P2_7 SVRDRVCC SVRPGATE SVRNGATE SVRDRVSS SVRAVSS SVRAVCC P2_6 P2_5 P2_4 P2_0 P2_3 P2_2 P2_1 P5_6 VDD 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 P20_14 1 132 P5_3 P10_0 2 131 P5_4 P10_1 3 130 E0VCC P10_2 4 129 P5_2 P10_3 5 128 VMONOUT P10_4 6 127 PWRCTL P10_5 7 126 AWOVCL P10_6 8 125 SYSVCC VDD 9 124 X1 P10_7 10 123 VSS E1VCC 11 122 X2 P10_8 12 121 VDD P17_6 13 120 FLMD0 P10_9 14 119 RESET P10_10 15 118 TRST P10_11 16 117 JP0_0 P10_12 17 116 JP0_1 VDD 18 115 JP0_2 P17_5 19 114 JP0_3 VCC 20 113 JP0_5 P10_13 21 112 P6_14 P10_14 22 111 P6_13 P17_0 23 110 P6_15 P17_1 24 109 VDD P17_2 25 108 P6_10 P17_3 26 107 E0VCC P17_4 27 106 P3_7 VDD 28 105 P3_6 AP2_13 29 104 P6_12 AP2_11 30 103 P6_9 AP2_10 31 102 P6_7 AP2_9 32 101 P6_8 AP2_8 33 100 VDD AP2_7 34 99 P6_0 AP2_6 35 98 P6_6 AP2_5 36 97 P6_5 AP2_4 37 96 AP4_2 AP2_3 38 95 AP4_1 AP2_2 39 94 AP4_3 AP2_1 40 93 AP4_0 AP2_0 41 92 AP4_4 AP2_12 42 91 A2VREFH A1VREFH 43 90 A2VSS A1VSS 44 89 P6_11 A0VREFH A0VSS AP0_0 AP0_1 AP0_2 AP0_3 AP0_4 AP0_5 AP0_6 AP0_7 AP0_8 AP0_9 AP0_10 AP0_11 AP0_12 AP0_13 VDD P24_4 P24_5 P24_6 VDD P24_7 P24_8 E2VCC P4_5 P4_6 P24_9 P24_10 P4_7 P24_11 P4_8 VDD P24_12 P4_9 P24_13 P4_10 E0VCC VDD P4_11 P4_12 P4_13 P4_14 P4_15 P3_5

Page 14 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview Figure 1.7 Pin Connecti on Diagram (BGA156 U2A6) 123456789 1 0 1 1 1 2 1 3 1 4 A VSS ERROROUT_M VSS P20_13 P20_10 P20_9 P20_8 P20_4 SVRDRVSSSVRPGATESVRNGATE SVRAVSS AWOVCL VSS A B P10_0 VSS P20_14 P21_2 P21_1 P21_0 P20_7 P20_3 P2_14 SVRDRVCC SVRAVCC P2_0 VSS P5_4 B C 3 _ 5 P 6 _ 5 PC C V 0 E S S V D D V C C V 1 E S S V C C V1 _ 0 1 P 2 _ 0 1 P C D P10_4 P10_3 PWRCTL P5_2 D E P10_6 P10_5 E1VCC VSS VDD VDD VDD VDD VSS SYSVCC VMONOUT X1 E F P10_8 P10_7 P10_13 VDD VSS VSS VSS VSS VDD VSS FLMD0 X2 F G P10_11 P10_10 P10_14 VDD VSS VSS VSS VSS VDD JP0_2 TRST RESET G H P17_1 P17_0 VCC VDD VSS VSS VSS VSS VDD JP0_5 JP0_1 JP0_0 H J AP2_7 AP2_6 AP2_5 VDD VSS VSS VSS VSS VDD P6_15 P6_14 JP0_3 J K AP2_4 AP2_2 AP2_3 VSS VDD VDD VDD AWOVCL VSS P6_6 P3_7 P6_13 K L AP2_0 AP2_1 P6_9 P6_10 L M 6 _ 3 P 8 _ 6 PC C V 0 E S S V S S V C C V 2 E C C V 2 E S S VH F E R V 0 A H F E R V 1 A M N A1VSS A0VSS AP0_2 AP0_3 AP0_5 AP0_7 P24_6 P24_8 P24_9 P4_9 P4_12 P4_14 VSS P6_7 N P A0VSS AP0_0 AP0_1 AP0_4 AP0_6 P24_4 P24_5 P24_7 P4_6 P4_7 P4_10 P4_13 P4_15 VSS P 123456789 1 0 1 1 1 2 1 3 1 4

Page 15 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview Note: The Exposed Pad shall be connected to VSS. Figure 1.8 Pin Connection Diagram (QFP144 U2A6) ERROROUT_M VSS VCC P20_13 P20_12 P20_10 P20_9 P20_8 VDD P20_6 P20_7 E1VCC P20_5 P20_4 P20_3 P20_2 P20_1 VDD P2_15 VDD P2_12 P2_14 P2_13 E0VCC P2_11 SVRDRVCC SVRPGATE SVRNGATE SVRDRVSS SVRAVSS SVRAVCC P2_0 P2_2 P5_6 VDD P5_3 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 P20_14 1 108 P5_4 P10_0 2 107 E0VCC P10_1 3 106 P5_2 P10_2 4 105 VMONOUT P10_3 5 104 PWRCTL P10_4 6 103 AWOVCL P10_5 7 102 SYSVCC P10_6 8 101 X1 VDD 9 100 VSS P10_7 10 99 X2 E1VCC 11 98 VDD P10_8 12 97 FLMD0 P10_9 13 96 RESET P10_10 14 95 TRST P10_11 15 94 JP0_0 P10_12 16 93 JP0_1 VDD 17 92 JP0_2 P17_5 18 91 JP0_3 VCC 19 90 JP0_5 P10_13 20 89 P6_14 P10_14 21 88 P6_13 P17_0 22 87 P6_15 P17_1 23 86 VDD VDD 24 85 P6_10 AP2_9 25 84 E0VCC AP2_8 26 83 P3_7 AP2_7 27 82 P3_6 AP2_6 28 81 P6_12 AP2_5 29 80 P6_9 AP2_4 30 79 P6_8 AP2_3 31 78 VDD AP2_2 32 77 P6_6 AP2_1 33 76 P6_5 AP2_0 34 75 P6_4 A1VREFH 35 74 A2VREFH A1VSS 36 73 A2VSS A0VREFH A0VSS AP0_0 AP0_1 AP0_2 AP0_3 AP0_4 AP0_5 AP0_6 AP0_7 AP0_8 AP0_9 VDD P3_2 P3_3 P4_0 VDD P24_7 P24_8 E2VCC P4_5 P4_6 P4_7 P24_11 P4_8 VDD P4_9 P4_10 E0VCC VDD P4_13 P4_14 P4_15 P3_4 P3_5 P6_11

Page 16 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview

1.6 Functional Block Configuration

Figure 1.9 Internal Block Diagram (U2A-EVA 516 pins) Sy stem B us Debug ICU M P-Bus Group1P-Bus Group2H/2LP-Bus Group6H/L IPIR Glo bal FLASH Bu s CRAM Bus Glo bal Em ulation R AM (2MB) P-Bus Group4 P-Bus Group7P-Bus Group8 P-Bus Group0 DM A C ontrolle r sDMAC0,1 DTS WA KE UP GTM Data FLASH INTC2 PSI5S 0,1 RLIN3 (2n, n = 0 to 11 ) RS- CANFD1 ADCJ0 RSENT0-7 Er ror Control Mo dule Flash Controller Clock Mo nitor0-9 Volt age Mo nitor Stand by Controller SINT Clock Controller Reset Controller Tem peratu re Sensor IO po rt Periph eral Bu s(P-Bus) RHSIF0 Deb ugICU M P-Bus Group9 Int er-cluste r Bus(I-Bus) TPTM BARR I-Bus Gro up2 I-Bus Gro up1 I-Bus Gro up0 Cluster0 ERAM (1MB) Loc al FLASH B us LRAM (64KB) Icache CPU0(PE0) Checker Core CRAM (512 KB) CPU1(PE1) Checker Core Cluster #0 LRAM (64KB) Icache Int er-processor eleme nt Bus CRAM controller Cluster1 ERAM (1MB) Loc al FLASH B us LRAM (64KB) Icache CPU2(PE2) CRAM (512 KB) CPU3(PE3) Cluster #1 LRAM (64KB) Icache Int er-processor eleme nt Bus CRAM controller PSI5 0,1,2 ,3 Checker Core Chec ker Core TAUJ2, 3 RTCA0 P-Bus Group3 SCI30, 1,2 KCRC0,2,4, 6MS PI 0, 2, 4 , 6, 8 P-Bus Group5 ENCA0,1 LTSC TAUD0,1,2 TAPA0,1,2 , TAUJ0,1 TSG30,1 PIC1 OSTM0-9 WDTB 0-3 SW DT MSPI 1,3 ,5,7 ,9 ADCJ1 RIIC 0,1 RS- CANFD0 TP BA0,1 KCRC1,3,5, RLIN3 (2n+1 , n = 0 to 11 ) PW M-diag WDTB A LPS CXP I 0, 1 , 2, 3 eM MC ADCJ2 Instrum ent atio n RAM (96KB) CRAM (2MB) CRAM controller Cluster #2 RRAM (256 KB) CRAM controller Cluster #3 PIC20, 1,2 AURORA Code Flash FLI0 (4MB) FLI1 (4MB) Code Flash FLI2 (4MB) FLI3 (4MB) ET NB0 ( S) (Fast Ether) ET NB1 ( S) (Gb Ether) High speed Bus(H-Bus) ET NB0 ( M) (Fast Ether) FlexRay0 SF MA 0 RHSIF0 H-Bus Group0H-Bus Group1 FlexRay1 H-Bus Group2 H-Bus Group3 ET NB 1 ( M) (Gb Ether) MP UFPUMPU CPU pe riph eral INTC1 FPU MPUFPUMPUFPU CPU pe riph eral INTC1 CPU pe riph eral INTC1 CPU pe riph eral INTC1

Page 17 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview Figure 1.10 Internal Block Diagram (U2A16 516 pins) Sy stem B us Debug ICU M P-Bus Group1P-Bus Group2H/2LP-Bus Group6H/L IPIR Glo bal FLASH Bu s CRAM Bus P-Bus Group4 P-Bus Group7P-Bus Group8 P-Bus Group0 DM A C ontrolle r sDMAC0,1 DTS WA KE UP GTM Data FLASH INTC2 PSI5S 0,1 RLIN3 (2n, n = 0 to 11) RS- CANFD1 ADCJ0 RSENT0-7 Er ror Control Mo dule Flash Controller Clock Mo nitor0-9 Volt age Mo nitor Stand by Controller SINT Clock Controller Reset Controller Tem peratu re Sensor IO po rt Periph eral Bu s(P-Bus) RHSIF0 Deb ugICU M P-Bus Group9 Int er-cluste r Bus(I-Bus) TPTM BARR I-Bus Gro up2 I-Bus Gro up1 I-Bus Gro up0 Loc al FLASH B us LRAM (64KB) Icache CPU0(PE0) Checker Core CRAM (512 KB) CPU1(PE1) Checker Core Cluster #0 LRAM (64KB) Icache Int er-processor eleme nt Bus CRAM controller Loc al FLASH B us LRAM (64KB) Icache CPU2(PE2) CRAM (512 KB) CPU3(PE3) Cluster #1 LRAM (64KB) Icache Int er-processor eleme nt Bus PSI5 0,1,2 ,3 Checker Core Chec ker Core TAUJ2, 3 RTCA0 P-Bus Group3 SCI30, 1,2 KCRC 0,2 ,4,6MS PI 0, 2, 4 , 6, 8 P-Bus Group5 ENCA0,1 LTSC TAUD0,1,2 TAPA0,1,2, TAUJ0,1 TSG30,1 PIC1 OSTM0-9 WDTB 0-3 SW DT MSPI 1,3 ,5,7 ,9 ADCJ1 RIIC 0,1 RS- CANFD0 TP BA0,1 KCRC 1,3 ,5,7 RLIN3 (2n+1 , n = 0 to 11) PW M-diag WDTB A LPS CXP I 0, 1 , 2, 3 eM MC ADCJ2 CRAM (2MB) Cluster #2 RRAM (256 KB) Cluster #3 PIC20, 1,2 Code Flash FLI0 (4MB) FLI1 (4MB) Code Flash FLI2 (4MB) FLI3 (4MB) ET NB0 ( S) (Fast Ether) ET NB1 ( S) (Gb Ether) High speed Bus(H-Bus) ET NB0 ( M) (Fast Ether) FlexRay0 SF MA 0 RHSIF0 H-Bus Group0H-Bus Group1 FlexRay1 H-Bus Group2 H-Bus Group3 ET NB 1 ( M) (Gb Ether) CRAM controller CRAM controller CRAM controller MPU CPU pe riph eral INTC1 FPU MPU CPU pe riph eral INTC1 FPU MPU CPU pe riph eral INTC1 FPU MP U CPU pe riph eral INTC1 FPU

Page 18 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview Figure 1.11 Internal Block Diagram (U2A16 373 pins) Sy stem B us Debug ICU M P-Bus Group1P-Bus Group2H/2LP-Bus Group6H/L IPIR Glo bal FLASH Bu s CRAM Bus P-Bus Group4 P-Bus Group7P-Bus Group8 P-Bus Group0 DM A C ontrolle r sDMAC0,1 WA KE UP GTM Data FLASH INTC2 PSI5S 0,1 RLIN3 (2n, n = 0 to 11 ) RS- CANFD1 ADCJ0 RSENT0-7 Er ror Control Mo dule Flash Controller Clock Mo nitor0-9 Volt age Mo nitor Stand by Controller SINT Clock Controller Reset Controller Tem peratu re Sensor IO po rt Periph eral Bu s(P-Bus) RHSIF0 Deb ugICU M P-Bus Group9 Int er-cluste r Bus(I-Bus) TPTM BARR I-Bus Gro up2 I-Bus Gro up1 I-Bus Gro up0 Loc al FLASH B us LRAM (64KB) Icache CPU0(PE0) Checker Core CRAM (512 KB) CPU1(PE1) Checker Core Cluster #0 LRAM (64KB) Icache Int er-processor eleme nt Bus CRAM controller Loc al FLASH B us LRAM (64KB) Icache CPU2(PE2) CRAM (512 KB) CPU3(PE3) Cluster #1 LRAM (64KB) Icache Int er-processor eleme nt Bus CRAM controller PSI5 0,1,2 ,3 Checker Core Chec ker Core TAUJ2, 3 RTCA0 P-Bus Group3 SCI30, 1,2 KCRC0,2,4, 6MS PI 0, 2, 4 , 6, 8 P-Bus Group5 ENCA0,1 LTSC TAUD0,1,2 TAPA0,1,2, TAUJ0,1 TSG30,1 PIC1 OSTM0-9 WDTB 0-3 SW DT MSPI 1,3 ,5,7 ADCJ1 RIIC 0,1 RS- CANFD0 TPBA KCRC1,3,5, RLIN3 (2n+1 , n = 0 to 11 ) PW M-diag WDTB A LPS CXP I 0, 1 , 2, 3 eM MC ADCJ2 CRAM (2MB) CRAM controller Cluster #2 RRAM (256 KB) CRAM controller Cluster #3 PIC20, 1,2 Code Flash FLI0 (4MB) FLI1 (4MB) Code Flash FLI2 (4MB) FLI3 (4MB) ET NB0 ( S) (Fast Ether) ET NB1 ( S) (Gb Ether) High speed Bus(H-Bus) ET NB 0 ( M) (Fast Ether) FlexRay0 SF MA 0 RHSIF0 H-Bus Group0H-Bus Group1 FlexRay1 H-Bus Group2 H-Bus Group3 ET NB 1 ( M) (Gb Ether) DTS MPU CPU pe riph eral INTC1 FPU MPU CPU pe riph eral INTC1 FPU MPU CPU pe riph eral INTC1 FPU MPU CPU pe riph eral INTC1 FPU

Page 19 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview Figure 1.12 Internal Block Diagram (U2A16 292 pins) Sy stem B us Debug ICU M P-Bus Group1P-Bus Group2H/2LP-Bus Group6H/L IPIR Glo bal FLASH Bu s CRAM Bus P-Bus Group4 P-Bus Group7P-Bus Group8 P-Bus Group0 DM A C ontrolle r sDMAC0,1 WA KE UP GTM Data FLASH INTC2 PSI5S 0,1 RLIN3 (2n, n = 0 to 5) RS- CANFD1 ADCJ0 RSENT0-7 Er ror Control Mo dule Flash Controller Clock Mo nitor0-9 Volt age Mo nitor Stand by Controller SINT Clock Controller Reset Controller Tem peratu re Sensor IO po rt Periph eral Bu s(P-Bus) RHSIF0 Deb ugICU M P-Bus Group9 Int er-cluste r Bus(I-Bus) TPTM BARR I-Bus Gro up2 I-Bus Gro up1 I-Bus Gro up0 Loc al FLASH B us LRAM (64KB) Icache CPU0(PE0) Checker Core CRAM (512 KB) CPU1(PE1) Checker Core Cluster #0 LRAM (64KB) Icache Int er-processor eleme nt Bus CRAM controller Loc al FLASH B us LRAM (64KB) Icache CPU2(PE2) CRAM (512 KB) CPU3(PE3) Cluster #1 LRAM (64KB) Icache Int er-processor eleme nt Bus CRAM controller PSI5 0,1,2 ,3 Checker Core Chec ker Core TAUJ2, 3 RTCA0 P-Bus Group3 SCI30, 1,2 KCRC0,2,4, 6MSPI 0,2,4, P-Bus Group5 ENCA0,1 LTSC TAUD0,1,2 TAPA0,1,2, TAUJ0,1 TSG30,1 PIC1 OSTM0-9 WDTB 0-3 SW DT MSPI 1,3,5 ADCJ1 RIIC 0,1 RS- CANFD0 TPBA KCRC1,3,5, RLIN3 (2n+1 , n = 0 to 5) PW M-diag WDTB A LPS CXP I 0, 1 , 2, 3 eM MC ADCJ2 CRAM (2MB) CRAM controller Cluster #2 RRAM (256 KB) CRAM controller Cluster #3 PIC20, 1,2 Code Flash FLI0 (4MB) FLI1 (4MB) Code Flash FLI2 (4MB) FLI3 (4MB) ET NB0 ( S) (Fast Ether) ET NB1 ( S) (Gb Ether) High speed Bus(H-Bus) ET NB 0 ( M) (Fast Ether) FlexRay0 SF MA 0 RHSIF0 H-Bus Group0H-Bus Group1 FlexRay1 H-Bus Group2 H-Bus Group3 ET NB 1 ( M) (Gb Ether) DTS MPU CPU pe riph eral INTC1 FPU MPU CPU pe riph eral INTC1 FPU MPU CPU pe riph eral INTC1 FPU MPU CPU pe riph eral INTC1 FPU

Page 20 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview Figure 1.13 Internal Block Diagram (U2A8 373 pins) Sy stem B us Debug ICU M P-Bus Group1P-Bus Group2H/2LP-Bus Group6H/L IPIR Glo bal FLASH Bu s CRAM Bus P-Bus Group4 P-Bus Group7P-Bus Group8 P-Bus Group0 DM A C ontrolle r sDMAC0,1 WA KE UP GTM Data FLASH INTC2 PSI5S 0,1 RLIN3 (2n, n = 0 to 11) ADCJ0 RSENT0-7 Flash Controller Clock Mo nitor0-7 Volt age Mo nitor Stand by Controller SINT Clock Controller Reset Controller Tem peratu re Sensor IO po rt Periph eral Bu s(P-Bus) Int er-cluste r Bus(I-Bus) TPTM BARR I-Bus Gro up2 I-Bus Gro up1 I-Bus Gro up0 Loc al FLASH B us LRAM (64KB) Icache CPU0(PE0) Checker Core CRAM (512 KB) CPU1(PE1) Checker Core Cluster #0 LRAM (64KB) Icache Int er-processor eleme nt Bus CR AM controller PSI5 0,1,2 ,3 TAUJ2, 3 RTCA0 P-Bus Group3 SCI30, 1,2 KCRC0,2,4, 6MS PI 0, 2, 4 , 6, 8 P-Bus Group5 ENCA0,1 LTSC TAUD0,1,2 TAPA0,1,2, TAUJ0,1 TSG30,1 PIC1 OSTM0- 5,8,9 WDTB 0-1 SW DT MSPI 1,3,5,7 ADCJ1 RIIC 0,1 RS- CANFD0 TP BA0,1 KCRC1,3,5, RLIN3 (2n+1 , n = 0 to 11) PW M-diag WDTB A LPS CXP I 0, 1 , 2, 3 eM MC ADCJ2 CRAM (1MB) CR AM controller Cluster #2 RRAM (128 KB) CR AM controller Cluster #3 PIC20, 1,2 Code Flash FLI0 (4MB) FLI1 (4MB) RHSIF0 Deb ugICU M P-Bus Group9 ET NB 0 ( S) (Fast Ether) High speed Bus(H-Bus) ET NB 0 ( M) (Fast Ether) FlexRay0 SF MA 0 RHSIF0 H-Bus Group0H-Bus Group1 FlexRay1 H-Bus Group2 H-Bus Group3 RS- CANFD1 Er ror Control Mo dule DTS ET NB 1 ( M) (Gb Ether) ET NB 1 ( S) (Gb Ether) MPU CPU pe riph eral INTC1 FPU MPU CPU pe riph eral INTC1 FPU

Page 21 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview Figure 1.14 Internal Block Diagram (U2A8 292 pins) Sy stem B us Debug ICU M P-Bus Group1P-Bus Group2H/2LP-Bus Group6H/L IPIR Glo bal FLASH Bu s CRAM Bus P-Bus Group4 P-Bus Group7P-Bus Group8 P-Bus Group0 DM A C ontrolle r sDMAC0,1 WA KE UP GTM Data FLASH INTC2 PSI5S 0,1 RLIN3 (2n, n = 0 to 5) ADCJ0 RSENT0-7 Flash Controller Clock Mo nitor0-7 Volt age Mo nitor Stand by Controller SINT Clock Controller Reset Controller Tem peratu re Sensor IO po rt Periph eral Bu s(P-Bus) Int er-cluste r Bus(I-Bus) TPTM BARR I-Bus Gro up2 I-Bus Gro up1 I-Bus Gro up0 Loc al FLASH B us LRAM (64KB) Icache CPU0(PE0) Checker Core CRAM (512 KB) CPU1(PE1) Checker Core Cluster #0 LRAM (64KB) Icache Int er-processor eleme nt Bus CR AM controller PSI5 0,1,2 ,3 TAUJ2, 3 RTCA0 P-Bus Group3 SCI30, 1,2 KCRC0,2,4, 6MSPI 0,2,4 P-Bus Group5 ENCA0,1 LTSC TAUD0,1,2 TAPA0,1,2, TAUJ0,1 TSG30,1 PIC1 OSTM0- 5,8,9 WDTB 0-1 SW DT MSPI 1,3,5 ADCJ1 RIIC 0,1 RS- CANFD0 TP BA0,1 KCRC1,3,5, RLIN3 (2n+1 , n = 0 to 5) PW M-diag WDTB A LPS CXP I 0, 1 , 2, 3 eM MC ADCJ2 CRAM (1MB) CR AM controller Cluster #2 RRAM (128 KB) CR AM controller Cluster #3 PIC20, 1,2 Code Flash FLI0 (4MB) FLI1 (4MB) RHSIF0 Deb ugICU M P-Bus Group9 ET NB 0 ( S) (Fast Ether) High speed Bus(H-Bus) ET NB0 ( M) (Fast Ether) FlexRay0 SF MA 0 RHSIF0 H-Bus Group0H-Bus Group1 FlexRay1 H-Bus Group2 H-Bus Group3 RS- CANFD1 Er ror Control Mo dule DTS ET NB 1 (S ) (Gb Ether) ET NB 1 ( M) (Gb Ether) MPU CPU pe riph eral INTC1 FPUMPU CPU pe riph eral INTC1 FPU

Page 22 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview Figure 1.15 Internal Block Diagram (U2A6 292 pins) System Bus Debug ICUM P-Bus Group1P-Bus Group2H/2LP-Bus Group6H/L IPIR Global FLASH Bus CRAM Bus P-Bus Group4 P-Bus Group7P-Bus Group8 P-Bus Group0 DMA Controller sDMAC0,1 WAKE UP GT M Data FLASH INTC2 PSI5S0,1 RLIN3 (2n, n = 0 to 5) ADCJ0 RSENT0-7 Flash Controller Clock Monitor0-7 Vo ltage Monitor Stan db y Controller SINT Clock Controller Reset Controller Temperat ure Se nsor IO port Pe rip her al Bu s(P-Bu s) Inter-cluster Bus(I-Bus) TPTM BARR I-Bus Group2 I-Bus Group1 I-Bus Group0 Local FLASH Bus LRAM (64KB) Icache CPU0(PE0) Checker Core CRAM (512KB) CPU1(PE1) Checker Core Cluster #0 LRAM (64KB) Icache Inter-pr ocessor el ement Bus TAUJ2, 3 RTCA0 P-Bus Group3 KCRC0,2,4, 6MSPI 0,2,4 P-Bus Group5 ENCA0,1 LTSC TAUD0,1,2 TAPA0,1,2, TAUJ0,1 TSG30,1 PIC1 OSTM0- 5,8,9 WDTB0-1 SW DT MSPI 1,3,5 ADCJ1 RIIC0,1 RS- CANFD0 TPBA0,1 KCRC1,3,5, RLIN3 (2n+1, n = 0 to 5) PW M-di ag WDTBA LPS eMMC ADCJ2 RRAM (128KB) Cluster #3 PIC20,1,2 Code Flash FLI0 (3MB) FLI1 (3MB) DebugICUM P-Bus Group9 ETNB0 (S) (Fast Ether) High speed Bus(H-Bus) ETNB0 (M) (Fast Ether) FlexRay0 SFMA0 H-Bus Group1 H-Bus Group3 RS- CANFD1 PSI50,1,2,3 DTS Error Control Module CRAM controller CRAM controller MPU CPU peripheral INTC1 FPU MPU CPU peripheral INTC1 FPU Cluster0 ERAM (32KB)

Page 23 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview Figure 1.16 Internal Block Diagram (U2A6 176 pins) Sy stem B us Debug ICU M P-Bus Group1P-Bus Group2H/ 2LP-Bus Group6H/ L IPIR Glo bal FLASH Bu s CRAM Bus P-Bus Group4 P-Bus Group7P-Bus Group8 P-Bus Group0 DM A C ontrolle r sDMAC0,1 WA KE UP GTM Data FLASH INTC2 PSI5S 1 RLIN3 (2n, n = 0 to 5) ADCJ0 RSENT0-7 Flash Controller Clock Mo nitor0-7 Volt age Mo nitor Stand by Controller SINT Clock Controller Reset Controller Tem peratu re Sensor IO po rt Periph eral Bu s(P-Bus) Int er-cluste r Bus(I-Bus) TPTM BA RR I-Bus Gro up2 I-Bus Gro up1 I-Bus Gro up0 Loc al FLASH B us LRAM (64KB) Icache CPU0(PE0) Chec ker Core CRAM (512 KB) CPU1(PE1) Chec ker Core Cluster #0 LRAM (64KB) Icache Int er-processor eleme nt Bus TAUJ2, 3 RTCA0 P-Bus Group3 KCRC0,2,4, 6MSPI 0,2,4 P-Bus Group5 ENCA1 LTSC TAUD0,1,2 TAPA0,2,3 TAUJ0,1 TSG30,1 PIC1 OSTM0- 5,8 ,9 WDTB 0-1 SW DT MSPI 1,3,5 ADCJ1 RIIC 0,1 RS- CANFD0 TP BA0,1 KCRC1,3,5, RLIN3 (2n+1 , n = 0 to 5) PWM-diag WDTB A LPS eM MC ADCJ2 RRAM (128 KB) Cluster #3 PIC20, 1,2 Code Flash FLI0 (3MB) FLI1 (3MB) DebugICU M P-Bus Group9 ET NB 0 ( S) (Fast Ether) High spe ed Bus(H-Bus) ET NB 0 ( M) (Fast Ether) FlexRay0 SF MA 0 H-Bus Group1 H-Bus Group3 RS- CANFD1 PSI5 0,1,2 ,3 DTS Er ror Control Mo dule CR AM con tro lle r CR AM con tro lle r MPU CPU pe riph eral INTC1 FPU MPU CPU pe riph eral INTC1 FPU Cluster0 ERAM (32KB)

Page 24 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview Figure 1.17 Internal Block Diagram (U2A6 156 pins) Sy stem B us Debug ICU M P-Bus Group1P-Bus Group2H/ 2LP-Bus Group6H/L IPIR Glo bal FLASH Bu s CRAM Bus P-Bus Group4 P-Bus Group7P-Bus Group8 P-Bus Group0 DM A C ontrolle r sDMAC0,1 WA KE UP GTM Data FLASH INTC2 PS I5S 1 RLIN3 (2n, n = 0 , 2, 4, 5) ADCJ0 RSENT0-7 Fl as h Controller Clock Mo nitor0-7 Volt age Mo nitor Stand by Controller SINT Clock Controller Reset Controller Temperature Sensor IO po rt Periph eral Bu s(P-Bus) Inter-cl uster Bus(I-Bus) TPTM BA RR I-Bus Gro up2 I-Bus Gro up1 I-Bus Gro up0 Lo ca l FLASH Bu s LRAM (64KB) Icache CPU0(PE0) Chec ker Core CRAM (512 KB) CPU1(PE1) Chec ker Core Cluster #0 LRAM (64KB) Icache Int er-processor eleme nt Bus TAUJ2, 3 RTCA0 P-Bus Group3 KCRC0,2,4, 6MSPI 0,2,4 P-Bus Group5 LTSC TAUD0,1,2 TA PA0,3 TAUJ0,1 TSG31 PIC1 OSTM0- 5,8 ,9 WDTB 0-1 SW DT MSPI 1,3,5 ADCJ1 RIIC 0,1 RS- CANFD0 TP BA0,1KCRC1,3,5, RLIN3 (2n+1 , n = 1, 2, 4, 5) PWM-diag WDTB A RRAM (128 KB) Cluster #3 PIC20, 1,2 Code Flash FLI0 (3MB) FLI1 (3MB) DebugICU M P-Bus Group9 High spe ed Bus(H-Bus) FlexRay0 H-Bus Group1 RS- CANFD1 PSI5 0,1,2 ,3 DTS Er ror Control Mo dule CR AM con tro lle r CR AM con tro lle r MPU CPU pe riph eral INTC1 FPU MPU CPU pe riph eral INTC1 FPU Cluster0 ERAM (32KB)

Page 25 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 1 Overview Each CPU has its own set of CPU peripherals. These CPU peripherals are assigned to the common address: CPU peripheral (self), separately from their respective address. For example, access by CPU0 to a register of a CPU peripheral (self) is to the register in the CPU peripheral of CPU0; access by CPU1 to a register of a CPU peripheral (self) is to the register in the CPU peripheral of CPU1. Figure 1.18 Internal Block Diagram (U2A6 144 pins) System Bus Debug ICUM P-Bus Group1P-Bus Group2H/2LP-Bus Group6H/L IPIR Global FLASH Bus CRAM Bus P-Bus Group4 P-Bus Group7P-Bus Group8 P-Bus Group0 DMA Controller sDMAC0,1 WAKE UP GT M Data FLASH INTC2 PSI5S1 RLIN3 (2n, n = 0, 1, 2, 4, 5) ADCJ0 RSENT0-5 Flash Controller Clock Monitor0-7 Voltage Monitor Standby Controller SINT Clock Controller Reset Controller Temperat ure Sensor IO port Pe rip her al Bu s(P-Bu s) Inter-cluster Bus(I-Bus) TPTM BARR I-Bus Group2 I-Bus Group1 I-Bus Group0 Local FLASH Bus LRAM (64KB) Icache CPU0(PE0) Checker Core CRAM (512KB) CPU1(PE1) Checker Core Cluster #0 LRAM (64KB) Icache Inter-pr ocessor el ement Bus TAUJ2, 3 RTCA0 P-Bus Group3 KCRC0,2,4, 6MSPI 0,2 P-Bus Group5 ENCA1 LTSC TAUD0,1,2 TAPA0,3 TAUJ0,1 TSG31 PIC1 OSTM0- 5,8,9 WDTB0-1 SW DT MSPI 1,3 ADCJ1 RIIC0 RS- CANFD0 TPBA0,1 KCRC1,3,5, RLIN3 (2n+1, n = 1 to 5) PW M-di ag WDTBA LPS ADCJ2 RRAM (128KB) Cluster #3 PIC20,1,2 Code Flash FLI0 (3MB) FLI1 (3MB) DebugICUM P-Bus Group9 ETNB0 (S) (Fast Ether) High speed Bus(H-Bus) ETNB0 (M) (Fast Ether) FlexRay0 H-Bus Group1 RS- CANFD1 PSI50,2,3 DTS Error Control Module CRAM controller CRAM controller MPU CPU peripheral INTC1 FPU MPU CPU peripheral INTC1 FPU Cluster0 ERAM (32KB)

Page 26 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions Section 2 Pin Functions

2.1 Pin List

2.1.1 Pin List and Function assignment

For detailed information, refer to Appendix “E02_01_List_of_Pin_Assignment.xlsx”.

Page 27 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions

2.1.2 Pin Function name

Table 2.1 Pin Function Name Definition (1/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144) Port JP0_0 IO Port of JTAG port group 0 P0_0 IO Port of port group 0 √√√ √ P1_0 IO Port of port group 1 √√ P1_1 IO √√ P1_2 IO √√ P1_3 IO √√ P1_4 IO √√ P1_5 IO √√ P1_6 IO √√ P1_7 IO √√ P1_8 IO √√ P1_9 IO √√ P1_10 IO √√ P1_11 IO √√ P1_12 IO √√ P1_13 IO √√ P1_14 IO √√ P1_15 IO √√

Page 28 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions Port P2_9 IO Port of port group 2 √√√√√√√ P3_0 IO Port of port group 3 √√√ √ P3_9 IO √√ P3_10 IO √√ P3_11 IO √√ P3_12 IO √√ P3_13 IO √√ P3_14 IO √√ P3_15 IO √√ P4_2 IO √√ P4_3 IO √√ Table 2.1 Pin Function Name Definition (2/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 29 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions P8_0 IO Port of port group 8 √√√ √ P8_10 IO √√ P9_0 IO Port of port group 9 √√ P9_1 IO √√ P9_2 IO √√ P9_3 IO √√ P9_4 IO √√ P9_5 IO √√ P9_6 IO √√ P9_7 IO √√ P9_8 IO √√ P10_0 IO Port of port group Table 2.1 Pin Function Name Definition (3/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 30 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions Port P10_10 IO Port of port group P11_0 IO Port of port group 11 √√√ √ P12_0 IO Port of port group P12_1 IO √√ P12_2 IO √√ P12_3 IO √√ P12_4 IO √√ P12_5 IO √√ P17_0 IO Port of port group P18_0 IO Port of port group P18_1 IO √√ P18_2 IO √√ P18_3 IO √√ P18_4 IO √√ P18_5 IO √√ P18_6 IO √√ P18_7 IO √√ P18_8 IO √√ P18_9 IO √√ P18_10 IO √√ Table 2.1 Pin Function Name Definition (4/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 31 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions Port P18_11 IO Port of port group P18_12 IO √√ P18_13 IO √√ P18_14 IO √√ P18_15 IO √√ P19_0 IO Port of port group P19_1 IO √√ P19_2 IO √√ P19_3 IO √√ P19_4 IO √√ P19_5 IO √√ P20_0 IO Port of port group P20_15 IO √√ P21_0 IO Port of port group P21_12 IO √√ P21_13 IO √√ P22_0 IO Port of port group P23_0 IO Port of port group P23_1 IO √√ P23_2 IO √√ P23_3 IO √√ Table 2.1 Pin Function Name Definition (5/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 32 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions Port P23_4 IO Port of port group P23_5 IO √√ P23_6 IO √√ P23_7 IO √√ P23_8 IO √√ P23_9 IO √√ P23_10 IO √√ P23_11 IO √√ P23_12 IO √√ P23_13 IO √√ P24_4 IO Port of port group AP0_0 IO Port of analog port group 0 AP1_0 IO Port of analog port group 1 AP2_0 IO Port of analog port group 2 Table 2.1 Pin Function Name Definition (6/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 33 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions Port AP2_5 IO Port of analog port group 2 AP3_0 IO Port of analog port group 3 AP4_0 IO Port of analog port group 4 AP5_0 IO Port of analog port group 5 √√√ √ Table 2.1 Pin Function Name Definition (7/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 34 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions Interrupt s NMI I Non maskable interrupt INTP0 I Maskable external interrupt INTP9 I Maskable external interrupt INTP38 I √√√ √ INTP39 I √√√ √ Table 2.1 Pin Function Name Definition (8/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 35 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions System Control FLMD0 I Operating mode select pin X1 I Main oscillator resonator connections EXTCLK0O O Clock controller output PWRCTL O ISOVDD power control output signal SVRPGATE O SVR gate drive for the high-side PMOSFET SVRNGATE O SVR gate drive for the low-side NMOSFET VMONOUT O Voltage monitor error detection output signal LPS DPO O Port output signal for digital input APO O Port output signal for analog input SELDP0 O External multiplexer select output signal for digital port DPIN0 I Digital port input signal DPIN3 I √√√ √ DPIN4 I √√√ √ DPIN5 I √√√ √ DPIN6 I √√√ √ DPIN7 I √√√ √ DPIN8 I √√√ √ DPIN9 I √√√ √ DPIN10 I √√√ √ DPIN13 I √√√ √ DPIN14 I √√√ √ DPIN15 I √√ DPIN16 I √√ DPIN17 I √√ DPIN18 I √√ DPIN19 I √√ Table 2.1 Pin Function Name Definition (9/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 36 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions LPS DPIN20 I Digital port input signal DPIN21 I √√ DPIN22 I √√ DPIN23 I √√ SFMA0IO0 IO SFMA0 master data input / output MMCA0CMD IO MMCA0 command / response MSPI MSPI0SC IO MSPI0 serial clock input/output MSPI0SI I MSPI0 receive data input MSPI0SO O MSPI0 transmit data output MSPI0SSI I MSPI0 serial peripheral chip select input signal MSPI0CSS0 O MSPI0 serial peripheral chip select output signal MSPI0DCS I MSPI0 data consistency check signal MSPI0_SCKP IO MSPI0 serial clock differential input/ output MSPI0_SOP O MSPI0 transmit data differential output MSPI0_SIP I MSPI0 receive data differential input MSPI1SC IO MSPI1 serial clock input/output Table 2.1 Pin Function Name Definition (10/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 37 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions MSPI MSPI1SI I MSPI1 receive data input MSPI1SO O MSPI1 transmit data output MSPI1SSI I MSPI1 serial peripheral chip select input signal MSPI1CSS0 O MSPI1 serial peripheral chip select output signal MSPI1DCS I MSPI1 data consistency check signal MSPI1_SCKP IO MSPI1 serial clock differential input/ output MSPI1_SOP O MSPI1 transmit data differential output MSPI1_SIP I MSPI1 receive data differential input MSPI2SC IO MSPI2 serial clock input/output MSPI2SI I MSPI2 receive data input MSPI2SO O MSPI2 transmit data output MSPI2SSI I MSPI2 serial peripheral chip select input signal MSPI2CSS0 O MSPI2 serial peripheral chip select output signal MSPI2CSS4 O MSPI2 serial peripheral chip select output signal MSPI2DCS I MSPI2 data consistency check signal MSPI3SC IO MSPI3 serial clock input/output MSPI3SI I MSPI3 receive data input MSPI3SO O MSPI3 transmit data output Table 2.1 Pin Function Name Definition (11/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 38 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions MSPI MSPI3SSI I MSPI3 serial peripheral chip select input signal MSPI3CSS0 O MSPI3 serial peripheral chip select output signal MSPI3DCS I MSPI3 data consistency check signal MSPI4SC IO MSPI4 serial clock input/output MSPI4SI I MSPI4 receive data input MSPI4SO O MSPI4 transmit data output MSPI4SSI I MSPI4 serial peripheral chip select input signal MSPI4CSS0 O MSPI4 serial peripheral chip select output signal MSPI4DCS I MSPI4 data consistency check signal MSPI5SC IO MSPI5 serial clock input/output MSPI5SI I MSPI5 receive data input MSPI5SO O MSPI5 transmit data output MSPI5SSI I MSPI5 serial peripheral chip select input signal MSPI5CSS0 O MSPI5 serial peripheral chip select output signal MSPI5CSS1 O MSPI5 slave select signal output MSPI5DCS I MSPI5 data consistency check signal MSPI6SC IO MSPI6 serial clock input/output √√√ √ Table 2.1 Pin Function Name Definition (12/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 39 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions MSPI MSPI6SI I MSPI6 receive data input √√√ √ MSPI6SO O MSPI6 transmit data output √√√ √ MSPI6SSI I MSPI6 serial peripheral chip select input signal √√√ √ MSPI6CSS0 O MSPI6 serial peripheral chip select output signal √√√ √ MSPI6CSS1 O √√√ √ MSPI6CSS2 O √√√ √ MSPI6CSS3 O √√√ √ MSPI6DCS I MSPI6 data consistency check signal √√√ √ MSPI7SC IO MSPI7 serial clock input/output √√√ √ MSPI7SI I MSPI7 receive data input √√√ √ MSPI7SO O MSPI7 transmit data output √√√ √ MSPI7SSI I MSPI7 serial peripheral chip select input signal √√√ √ MSPI7CSS0 O MSPI7 serial peripheral chip select output signal √√√ √ MSPI7CSS1 O √√√ √ MSPI7CSS2 O √√√ √ MSPI7CSS3 O √√√ √ MSPI7DCS I MSPI7 data consistency check signal √√√ √ MSPI8SC IO MSPI8 serial clock input/output √√√ √ MSPI8SI I MSPI8 receive data input √√√ √ MSPI8SO O MSPI8 transmit data output √√√ √ MSPI8SSI I MSPI8 serial peripheral chip select input signal √√√ √ MSPI8CSS0 O MSPI8 serial peripheral chip select output signal √√√ √ MSPI8CSS1 O √√√ √ MSPI8CSS2 O √√√ √ MSPI8CSS3 O √√√ √ MSPI8DCS I MSPI8 data consistency check signal √√√ √ MSPI9SC IO MSPI9 serial clock input/output MSPI9SI I MSPI9 receive data input MSPI9SO O MSPI9 transmit data output MSPI9SSI I MSPI9 serial peripheral chip select input signal Table 2.1 Pin Function Name Definition (13/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 40 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions MSPI MSPI9CSS0 O MSPI9 serial peripheral chip select output signal MSPI9CSS1 O √√ MSPI9CSS2 O √√ MSPI9CSS3 O √√ MSPI9DCS I MSPI9 data consistency check signal SCI3 SCI30RXD I SCI30 data input signal SCI30TXD O SCI30 data output signal SCI30SCK IO SCI30 serial clock input/output SCI31RXD I SCI31 data input signal SCI31TXD O SCI31 data output signal SCI31SCK IO SCI31 serial clock input/output SCI32RXD I SCI32 data input signal SCI32TXD O SCI32 data output signal SCI32SCK IO SCI32 serial clock input/output RLIN3 RLIN30RX I RLIN30 receive data input RLIN30TX O RLIN30 transmit data output RLIN31RX I RLIN31 receive data input RLIN31TX O RLIN31 transmit data output RLIN32RX I RLIN32 receive data input RLIN32TX O RLIN32 transmit data output RLIN33RX I RLIN33 receive data input RLIN33TX O RLIN33 transmit data output RLIN34RX I RLIN34 receive data input RLIN34TX O RLIN34 transmit data output RLIN35RX I RLIN35 receive data input RLIN35TX O RLIN35 transmit data output RLIN36RX I RLIN36 receive data input RLIN36TX O RLIN36 transmit data output RLIN37RX I RLIN37 receive data input Table 2.1 Pin Function Name Definition (14/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 41 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions RLIN3 RLIN37TX O RLIN37 transmit data output RLIN38RX I RLIN38 receive data input RLIN38TX O RLIN38 transmit data output RLIN39RX I RLIN39 receive data input RLIN39TX O RLIN39 transmit data output RLIN310RX I RLIN310 receive data input RLIN310TX O RLIN310 transmit data output RLIN311RX I RLIN311 receive data input RLIN311TX O RLIN311 transmit data output RLIN312RX I RLIN312 receive data input √√√ √ RLIN312TX O RLIN312 transmit data output √√√ √ RLIN313RX I RLIN313 receive data input √√√ √ RLIN313TX O RLIN313 transmit data output √√√ √ RLIN314RX I RLIN314 receive data input √√√ √ RLIN314TX O RLIN314 transmit data output √√√ √ RLIN315RX I RLIN315 receive data input √√√ √ RLIN315TX O RLIN315 transmit data output √√√ √ RLIN316RX I RLIN316 receive data input √√√ √ RLIN316TX O RLIN316 transmit data output √√√ √ RLIN317RX I RLIN317 receive data input √√√ √ RLIN317TX O RLIN317 transmit data output √√√ √ RLIN318RX I RLIN318 receive data input √√√ √ RLIN318TX O RLIN318 transmit data output √√√ √ RLIN319RX I RLIN319 receive data input √√√ √ RLIN319TX O RLIN319 transmit data output √√√ √ RLIN320RX I RLIN320 receive data input √√√ √ RLIN320TX O RLIN320 transmit data output √√√ √ RLIN321RX I RLIN321 receive data input √√√ √ Table 2.1 Pin Function Name Definition (15/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 42 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions RLIN3 RLIN321TX O RLIN321 transmit data output √√√ √ RLIN322RX I RLIN322 receive data input √√√ √ RLIN322TX O RLIN322 transmit data output √√√ √ RLIN323RX I RLIN323 receive data input √√√ √ RLIN323TX O RLIN323 transmit data output √√√ √ RS- CANFD CAN0RX I CAN0 receive data input CAN0TX O CAN0 transmit data output CAN1RX I CAN1 receive data input CAN1TX O CAN1 transmit data output CAN2RX I CAN2 receive data input CAN2TX O CAN2 transmit data output CAN3RX I CAN3 receive data input CAN3TX O CAN3 transmit data output CAN4RX I CAN4 receive data input CAN4TX O CAN4 transmit data output CAN5RX I CAN5 receive data input CAN5TX O CAN5 transmit data output CAN6RX I CAN6 receive data input CAN6TX O CAN6 transmit data output CAN7RX I CAN7 receive data input CAN7TX O CAN7 transmit data output CAN8RX I CAN8 receive data input CAN8TX O CAN8 transmit data output CAN9RX I CAN9 receive data input CAN9TX O CAN9 transmit data output CAN10RX I CAN10 receive data input Table 2.1 Pin Function Name Definition (16/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 43 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions RS- CANFD CAN10TX O CAN10 transmit data output CAN11RX I CAN11 receive data input CAN11TX O CAN11 transmit data output CAN12RX I CAN12 receive data input CAN12TX O CAN12 transmit data output CAN13RX I CAN13 receive data input CAN13TX O CAN13 transmit data output CAN14RX I CAN14 receive data input CAN14TX O CAN14 transmit data output CAN15RX I CAN15 receive data input CAN15TX O CAN15 transmit data output FLXA FLXA0RXDA I FLXA0 channel A receive data input FLXA0TXDA O FLXA0 channel A transmit data output FLXA0TXENA O FLXA0 channel A transmit enable FLXA0RXDB I FLXA0 channel B receive data input FLXA0TXDB O FLXA0 channel B transmit data output FLXA0TXENB O FLXA0 channel B transmit enable FLXA0STPWT I FLXA0 stop watch trigger input FLXA1RXDA I FLXA1 channel A receive data input FLXA1TXDA O FLXA1 channel A transmit data output FLXA1TXENA O FLXA1 channel A transmit enable FLXA1RXDB I FLXA1 channel B receive data input FLXA1TXDB O FLXA1 channel B transmit data output FLXA1TXENB O FLXA1 channel B transmit enable FLXA1STPWT I FLXA1 stop watch trigger input Table 2.1 Pin Function Name Definition (17/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 44 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions ETNB ETNB0TXCLK I MII transmit clock √√√√√√√√ √ ETNB0TXEN O MII/RMII transmit data enable ETNB0TXD0 O MII/RMII transmit data ETNB0TXER O MII transmit data error ETNB0RXDV I MII receive data valid ETNB0RXD0 I MII/RMII receive data ETNB0RXER I MII/RMII receive data error ETNB0REFCL K I RMII reference clock ETNB0CRS_ DV I RMII receive data valid ETNB0MDC O PHY management clock ETNB0MDIO IO PHY management transfer data ETNB0LINKS TA ETNB0WOL O Wake-On-LAN (Magic Packet detection) TX_DATAN O SGMII transmit serial data differential output RX_CLKN I SGMII receive ddr clock differential input RX_CLKP I √ RX_DATAN I SGMII receive serial data differential input ETNB1REFCL K I SGMII reference clock ETNB1TXCLK I MII transmit clock √√ ETNB1RXCLK I MII receive clock √√ ETNB1TXEN O MII transmit data enable ETNB1TXD0 O MII transmit data √√ ETNB1TXD1 O √√ ETNB1TXD2 O √√ ETNB1TXD3 O √√ ETNB1TXER O MII transmit data error ETNB1RXDV I MII receive data valid Table 2.1 Pin Function Name Definition (18/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 45 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions ETNB ETNB1RXD0 I MII receive data √√ ETNB1RXD1 I √√ ETNB1RXD2 I √√ ETNB1RXD3 I √√ ETNB1RXER I MII receive data error ETNB1MDC O PHY management clock ETNB1MDIO IO PHY management transfer data ETNB1LINKS TA I PHY link status signal ETNB1PHYIN T I PHY interrupt information ETNB1WOL O Wake-On-LAN signal (Magic Packet detection) RSENT RSENT0RX I RSENT0 receive data input RSENT0SPC O O RSENT0 SPC extension output RSENT1RX I RSENT1 receive data input RSENT1SPC O O RSENT1 SPC extension output RSENT2RX I RSENT2 receive data input RSENT2SPC O O RSENT2 SPC extension output RSENT3RX I RSENT3 receive data input RSENT3SPC O O RSENT3 SPC extension output RSENT4RX I RSENT4 receive data input RSENT4SPC O O RSENT4 SPC extension output RSENT5RX I RSENT5 receive data input RSENT5SPC O O RSENT5 SPC extension output RSENT6RX I RSENT6 receive data input RSENT6SPC O O RSENT6 SPC extension output RSENT7RX I RSENT7 receive data input RSENT7SPC O O RSENT7 SPC extension output Table 2.1 Pin Function Name Definition (19/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 46 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions PSI5 PSI50RX I PSI50 receive data input PSI50TX O PSI50 transmit data output PSI51RX I PSI51 receive data input PSI51TX O PSI51 transmit data output PSI52RX I PSI52 receive data input PSI52TX O PSI52 transmit data output PSI53RX I PSI53 receive data input PSI53TX O PSI53 transmit data output RHSIF HSIF0_REFC LK IO RHSIF0 reference clock input/output HSIF0_RXDN I RHSIF0 receive data differential input HSIF0_TXDN O RHSIF0 transmit data differential output CXP1 CXP10RX I CXP10 receive data input CXP10TX O CXP10 transmit data output CXP11RX I CXP11 receive data input CXP11TX O CXP11 transmit data output CXP12RX I CXP12 receive data input CXP12TX O CXP12 transmit data output CXP13RX I CXP13 receive data input CXP13TX O CXP13 transmit data output Table 2.1 Pin Function Name Definition (20/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 47 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions TAUD TAUD0I0 I TAUD0 channel input TAUD0O0 O TAUD0 channel output TAUD1I0 I TAUD1 channel input Table 2.1 Pin Function Name Definition (21/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 48 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions TAUD1O0 O TAUD1 channel output TAUD1O12 O TAUD1 channel output TAUD2I0 I TAUD2 channel input Table 2.1 Pin Function Name Definition (22/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 49 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions TAUD TAUD2O0 O TAUD2 channel output TAUJ TAUJ0I0 I TAUJ0 channel input TAUJ0O0 O TAUJ0 channel output TAUJ1I0 I TAUJ1 channel input TAUJ1O0 O TAUJ1 channel output TAUJ2I0 I TAUJ2 channel input TAUJ2O0 O TAUJ2 channel output Table 2.1 Pin Function Name Definition (23/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 50 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions TAUJ TAUJ3I0 I TAUJ3 channel input TAUJ3O0 O TAUJ3 channel output TSG3 TSG30O0 O TSG30 timer up / down status output TSG30PTSI0 I TSG30 hall sensor input TSG30CLKI I TSG30 external clock input enable TSG31O0 O TSG31 timer up / down status output TSG31PTSI0 I TSG31 hall sensor input TSG31CLKI I TSG31 external clock input enable TPBA TPBA0O O TPBA0 timer pattern buffer output TPBA1O O TPBA1 timer pattern buffer output GTM GTM0I0 I GTM0 timer input signals for TIM0 Table 2.1 Pin Function Name Definition (24/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 51 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions GTM GTM1I0 I GTM0 timer input signals for TIM1 GTM2I0 I GTM0 timer input signals for TIM2 GTM3I0 I GTM0 timer input signals for TIM3 GTMAT0O0 O GTM0 timer output signals for ATOM0 GTMAT1O0 O GTM0 timer output signals for ATOM1 Table 2.1 Pin Function Name Definition (25/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 52 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions GTM GTMAT2O0 O GTM0 timer output signals for ATOM2 GTMAT3O0 O GTM0 timer output signals for ATOM3 GTMAT0O0N O GTM0 Inverted timer output signals for ATOM0 GTMAT1O0N O GTM0 Inverted timer output signals for ATOM1 GTMAT2O0N O GTM0 Inverted timer output signals for ATOM2 GTMAT3O0N O GTM0 Inverted timer output signals for ATOM3 Table 2.1 Pin Function Name Definition (26/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 53 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions GTM GTMAT3O5N O GTM0 Inverted timer output signals for ATOM3 GTMECLK0 O GTM0 external clock RTCA RTCA0OUT O RTCA0 1-Hz pulse output ENCA ENCA0E0 I ENCA0 encoder input ENCA0EC I ENCA0 encoder clear input ENCA0TIN0 I ENCA0 capture trigger input ENCA1E0 I ENCA1 encoder input ENCA1EC I ENCA1 encoder clear input ENCA1TIN0 I ENCA1 capture trigger input PIC TAPA0UN O Motor control output U phase (negative) TAPA0UP O Motor control output U phase (positive) TAPA0VN O Motor control output V phase (negative) TAPA0VP O Motor control output V phase (positive) TAPA0WN O Motor control output W phase (negative) TAPA0WP O Motor control output W phase (positive) TAPA0ESO I TAUD0/TSG30 emergency shut-off TAPA1ESO I TAUD1/TSG31 emergency shut-off ESO0 I ATOM emergency shut-off PWM- Diag Table 2.1 Pin Function Name Definition (27/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 54 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions PWM- Diag Table 2.1 Pin Function Name Definition (28/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 55 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions PWM- Diag Table 2.1 Pin Function Name Definition (29/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 56 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions ADCJ ADCJ0I0 I ADCJ0 input channel with high accuracy ADCJ0I10 I ADCJ0 input channel with high accuracy ADCJ0I0S I ADCJ0 input channel with low accuracy ADCJ0SEL0 O ADCJ0 external analog multiplexer (MPX) output ADCJ0TRG0 I ADCJ0 external trigger ADCJ0CNV0 O ADCJ0 conversion timing monitor A0VREFH I ADCJ0 reference voltage pin for the analog part Table 2.1 Pin Function Name Definition (30/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 57 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions ADCJ ADCJ1I0 I ADCJ1 input channel with high accuracy ADCJ1I11 I ADCJ1 input channel with high accuracy ADCJ1I0S I ADCJ1 input channel with low accuracy ADCJ1SEL0 O ADCJ1 external analog multiplexer (MPX) output ADCJ1TRG0 I ADCJ1 external trigger Table 2.1 Pin Function Name Definition (31/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 58 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions ADCJ ADCJ1CNV0 O ADCJ1 conversion timing monitor A1VREFH I ADCJ1 reference voltage pin for the analog part ADCJ2I0 I ADCJ2 input channel with high accuracy ADCJ2I5 I √√√ √ ADCJ2I6 I √√√ √ ADCJ2I7 I √√√ √ ADCJ2I8 I ADCJ2 input channel with high accuracy √√√ √ ADCJ2I9 I √√√ √ ADCJ2I10 I √√√ √ ADCJ2I11 I √√√ √ ADCJ2I12 I √√√ √ ADCJ2I13 I √√√ √ ADCJ2I14 I √√√ √ ADCJ2I15 I √√√ √ ADCJ2I16 I √√√ √ ADCJ2I17 I √√√ √ ADCJ2I18 I √√√ √ ADCJ2I19 I √√√ √ ADCJ2I0S I ADCJ2 input channel with low accuracy ADCJ2SEL0 O ADCJ2 external analog multiplexer (MPX) output ADCJ2TRG0 I ADCJ2 external trigger Table 2.1 Pin Function Name Definition (32/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 59 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions ADCJ ADCJ2CNV0 O ADCJ2 conversion timing monitor A2VREFH I ADCJ2 reference voltage pin for the analog part ECM ERROROUT_ M O Error output master signal ERROROUT_ C O Error output checker signal ERRORIN0 I External error input signal ERRORIN2 I √√√√ ERRORIN3 I √√√√ FLASH FPDT O Transmit data output (2-wire UATR, CSI) FPDR I Receive data input (2-wire UATR, CSI) FPCK I Serial clock input (CSI) TMS I Test mode select input EVTI I Event trigger input √√ EVTO O Even trigger output √√ LPDCLKO O LPD 4 pin clock output LPDO O LPD 4 pin data output LPDCLKI I LPD 4 pin clock input AUDR AUDRST I AUDR reset signal √ AUDSYNC I AUDR synchronous signal AUDCK I AUDR clock signal √ AUDATA0 IO AUDR data signal √ AUDATA1 IO √ AUDATA2 IO √ AUDATA3 IO √ Table 2.1 Pin Function Name Definition (33/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 60 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions Aurora CICREFP I Trace I/F clock pos √ CICREFN I Trace I/F clock neg √ TODP0 O Trace I/F data pos 0 √ TODN0 O Trace I/F data neg 0 √ TODP1 O Trace I/F data pos 1 √ TODN1 O Trace I/F data neg 1 √ TODP2 O Trace I/F data pos 2 √ TODN2 O Trace I/F data neg 2 √ TODP3 O Trace I/F data pos 3 √ TODN3 O Trace I/F data neg 3 √ MSYN IT r a c e I / F Synchronization request AURORES1 I EMUVDD domain reset signal AURORES2 I EMUVDD domain core signal isolation AURORESPD I Core domain EMUVDD signal isolation ERAM ERAMRESPD I Core domain ERAMVDD signal isolation ERAMRES2 I ERAMVDD domain core signal isolation Power SYSVCC - Power supply for System Logic, Internal voltage regulator and SVR power VCC - Power supply for FLASH VDD - Power supply terminal for core SVRAVCC - Power supply for SVR AWOVCL - External buffer capacitance of regulator Table 2.1 Pin Function Name Definition (34/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 61 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 2 Pin Functions Power E0VCC - Power supply for I/O port LVDVCC - Power supply for LVDS A0VCC - Power supply for A/ D converters A0VSS - Ground for A/D converters GETH0PVCC - Power supply for Ethernet DVCC - Power supply for Aurora DVDD - √ EMUVCC - √ EMUVDD - √ ERAMVDD - Power supply for ERAM ERAMVCC - √ ICUMH A ICUMGPIO0 O ICUMHA GPIO control Table 2.1 Pin Function Name Definition (35/35) Category Function name I/O Explanation RH850/ U2A-EVA (BGA516) RH850/ U2A16 (BGA516) RH850/ U2A16 (BGA373) RH850/ U2A16 (BGA292) RH850/ U2A8 (BGA373) RH850/ U2A8 (BGA292) RH850/ U2A6 (BGA292) RH850/ U2A6 (QFP176) RH850/ U2A6 (BGA156) RH850/ U2A6 (QFP144)

Page 62 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Section 3 Electrical Characteristics The specifications in this section are for devices operating under the conditions shown in Section 3.2.1.1, Supply Voltage Characteristics. Where a special condition is required for a given specification, the condition will be indicated. Furthermore, the specifications in this section are not guaranteed unless the conditions listed below are met.

3.1 Absolute Maximum Ratings

Conditions:  VSS = SVRDRVSS = SVRA VSS = AnVSS  Reference ground potential: VSS = 0 V . Table 3.1 Absolute Maximum Ratings (1/2) Item Symbol Condition MIN. TYP. MAX. Unit Power Voltage V AMRSYSVCC SYSVCC –0.5 6.5*10 V VAMRVCC VCC –0.5 6.5*10 V VAMRVDD VDD –0.5 1.42*11 V VAMRE0VCC E0VCC –0.5 6.5*10 V VAMRE1VCC E1VCC –0.5 6.5*10 V VAMRE2VCC E2VCC –0.5 6.5*10 V VAMRLVDVCC LVDVCC –0.5 6.5*10 V VAMRA0VCC A0VCC –0.5 6.5*10 V VAMRA1VCC A1VCC –0.5 6.5*10 V VAMRA2VCC A2VCC –0.5 6.5*10 V VAMRSVRDRVCC SVRDRVCC –0.5 6.5*10 V VAMRSVRAVCC SVRAVCC –0.5 6.5*10 V VAMRDVCC DVCC –0.5 4.6*12 V VAMRDVDD DVDD –0.5 1.42*11 V VAMREMUVCC EMUVCC –0.5 4.6*12 V VAMREMUVDD EMUVDD –0.5 1.42*11 V VAMRERAMVCC ERAMVCC –0.5 4.6*12 V VAMRERAMVDD ERAMVDD –0.5 1.42*11 V VAMRGETH0RVCC GETH0RVCC –0.5 6.5*10 V VAMRGETH0BVCC GETH0BVCC –0.5 4.6*12 V VAMRGETH0PVCC GETH0PVCC –0.5 6.5*10 V Input Voltage VAMRI E0VCC pin*1 –0.5 E0VCC + 0.5 V E1VCC pin*2 –0.5 E1VCC + 0.5 V E2VCC pin*3 –0.5 E2VCC + 0.5 V RESET, FLMD0, X1, X2 PWRCTL pin –0.5 SYSVCC + 0.5 V CICREFN, CICREFP , –0.5 DVDD+0.3 *9 V AURORES1, AURORES2 –0.5 EMUVCC + 0.5 V MSYN, AURORESPD, EVTI, EVTO, AUDR I/F*4, VMONOUT –0.5 E0VCC + 0.5 V

Page 63 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Note 1. JP0, P0, P1, P2, P3 (except P3_8 [For U2A-EVA, U2A16 and U2A8 Only]), P4, P5, P6, P8 Note 2. P9, P10, P11, P12, P18, P19, P20, 21, P22, P23 Note 3. P24 Note 4. AUDRST , AUDSYNC, AUDCK, AUDATA0-AUDATA3 Note 5. RHSIF: HSIF0_TXDP, HSIF 0_TXDN, HSIF0_RXDP, HSIF0_RXDN MSPI: MSPI0_SOP, MSPI0_SON, MSPI0_SIP, MSPI0_SIN, MSPI0_SCKP, MSPI0_SCKN Note 6. RX_CLKN, RX_CLKP, RX_DATAN, RX_DATAP , TX_DATAN, TX_DATAP and REFCLK. Note 7. Given specification includes injected currents. Note 8. After mounting Note 9. Do not exceed maximum 1.42 V. to 5.8 V is permissible, cumulative time is less than 100 h. Note 11. Voltage overshoot 1.205 V to 1.42 V is permissib le, cumulative time is less than 2 h. Voltage overshoot 1.155 V to 1.205 V is permissible, cumulative time is less than 100 h. to 3.9 V is permissible, cumulative time is less than 100 h. Input Voltage V AMRI ERAMRESPD –0.5 E1VCC + 0.5 V ERAMRES2 –0.5 ERAMVCC + 0.5 V RHSIF, MSPI*5 –0.5 LVDVCC + 0.5 V SGMII I/F*6 –0.5 GETH0BVCC + 0.5 V P3_8 [For U2A-EVA, U2A16 and U2A8 Only] –0.5 GETH0RVCC + 0.5 V Analogue reference voltage VAMRAVREF A0VREFH –0.5 A0VCC + 0.5 V A1VREFH –0.5 A1VCC + 0.5 V A2VREFH –0.5 A2VCC + 0.5 V Analogue input voltage VAMRIAN A0VCC pins –0.5 A0VCC + 0.5 V A1VCC pins –0.5 A1VCC + 0.5 V A2VCC pins –0.5 A2VCC + 0.5 V VSS differential voltage V VSSDIFF –0.1 0.1 V Injection current per digital input I INJ_DIN *13 –25 25 mA Injection current per analog input IINJ_AIN *13 –25 25 mA Total Injection current of the device INJ_TOT|* 13 120 mA Output low current*7 IOL1p per pin 10 mA IOLall Sum of all output low currents of all EnVCC/ AnVCC pins 200 mA Output high current*7 IOH1p per pin –10 mA IOHall Sum of all output high currents of all EnVCC/ AnVCC pins –200 mA Junction temperature T j U2A16 BGA516 U2A16 BGA373 U2A8 BGA373 –40 150 °C Other than above –40 160 °C Storage temperature *8 Tstg U2A16 BGA516 U2A16 BGA373 U2A8 BGA373 –55 150 °C Other than above –55 160 °C Table 3.1 Absolute Maximum Ratings (2/2) Item Symbol Condition MIN. TYP. MAX. Unit

Page 64 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Note 13. Input voltage must be kept within -0.8 V ≤ Vin ≤ 6.5 V. Power supply voltage must be kept within rated values. Injection current must be kept within rated values on all states include ramp-up/down, and power- on/off. Injection current effects power dissipation in the package for thermal characteristics. CAUTION

Even momentarily exceeding the absolute maximum rating for just one item creates a threat of failure in the reliability of the products. That is, the absolute maximum ratings are the levels that raise a threat of physical damage to the products. Be sure to use the products only under conditions that do not exceed the ratings. The quality and normal operation of the product are guaranteed under the standards and conditions given as DC and AC characteristics.
Input voltage, analog reference voltage and analog input voltage must not exceed 6.5 V.
Even in case when input voltage does not meet the specified characteristics, it is accepted if the injected current characteristics specified in Section 3.2.7 are met.

Page 65 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.2 General & DC Characteristics

3.2.1 Operational Condition

3.2.1.1 Supply Voltage Characteristics

Conditions:  Temperature range: Tj (min) to Tj (max)  VSS = SVRDRVSS = SVRA VSS = AnVSS  Reference ground potential: VSS = 0 V Table 3.2 Supply Voltage Characteristics (1/2)*1 Item Symbol Condition MIN. TYP. MAX. Unit System control supply voltage*6 VSYSVCC SVR unused*2 3.0 5.5 V SVR used*2 3.0 3.6 V 4.5 5.5 V Regulator supply voltage VVCC SVR unused 3.0 5.5 V SVR used 3.0 3.6 V 4.5 5.5 V Core supply voltage VVDD 1.025 1.09 1.155 V IO supply voltage VE0VCC 3.0 5.5 V VE1VCC VE2VCC RHSIF/MSPI LVDS supply voltage V LVDVCC 3.0 3.6 V 4.5 5.5 V ADC supply voltage VA0VCC 3.0 5.5 V VA1VCC VA2VCC ADC reference voltage supply VA0VREFH 3.0 5.5 V VA1VREFH VA2VREFH SVR supply voltage VSVRDRVCC *3 3.0 3.6 V 4.5 5.5 V VSVRAVCC 3.0 3.6 V 4.5 5.5 V Aurora I/F supply voltage (Analog) V DVCC 3.0 3.6 V Aurora I/F supply voltage (Digital) V DVDD Aurora used 1.04 1.09 1.14 V Aurora unused 1.025 1.09 1.155 V Aurora control IO supply voltage VEMUVCC 3.0 3.6 V Aurora control core supply voltage V EMUVDD Aurora used 1.04 1.09 1.14 V Aurora unused 1.025 1.09 1.155 V ERAM IO supply voltage*7 VERAMVCC 3.0 3.6 V ERAM core supply voltage*7 VERAMVDD Aurora used 1.04 1.09 1.14 V Aurora unused 1.025 1.09 1.155 V

Page 66 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Note 1. Use this device with the following conditions. [For U2A-EVA, U2A16 and U2A8 Only] SVRDRVCC ≥ SYSVCC = VCC = SVRAVCC A0VCC ≥ A0VREFH ≥ VCC A0VCC ≥ A0VREFH ≥ E0VCC = LVDVCC A1VCC ≥ A1VREFH A2VCC ≥ A2VREFH GETH0RVCC = GETH0PVCC = GETH0BVCC, when SGMII use. [For U2A6 Only] SVRDRVCC ≥ SYSVCC = VCC = SVRAVCC A0VCC = A0VREFH ≥ VCC A0VCC = A0VREFH ≥ E0VCC A1VCC = A1VREFH A2VCC = A2VREFH Note 2. SYSVCC is monitored by POC, see Section 3.2.13, Voltage Detector (POC, VLVI) Characteristics. Note 3. Maximum allowable noise for SVRDRVCC is 500mV peak to peak. Note 4. Input 3.0V to 3.6V voltage or connect to VSS with 1 k Ω or more pull-down resistance. Note 5. Maximum allowable noise for SGMII power is 50mV peak to peak. Note 6. Maximum allowable noise for SYSVCC is 100mV peak to peak.When MainOSC is used as the clock source of SGMII, allowable noise for SYSVCC will be 50mV peak to peak. Note 7. U2A6 has only ERAM core and its supply voltage is V VDD. CAUTION During operations, supply the specified voltages to all power lines. When stopping operation, turn off all of the power supplies. SGMII supply voltage*5 VGETH0RVCC SGMII used 3.14 3.3 3.46 V SGMII unused 3.0 5.5 V VGETH0PVCC SGMII used 3.14 3.3 3.46 V SGMII unused 3.0 5.5 V VGETH0BVCC SGMII used 3.14 3.3 3.46 V SGMII unused *4 V Table 3.2 Supply Voltage Characteristics (2/2)*1 Item Symbol Condition MIN. TYP. MAX. Unit

Page 67 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.2.1.2 Main Oscillator Characteristics

Conditions:

Supply voltage range: Refer to Section 3.2.1.1, Supply Voltage Characteristics. Table 3.3 Main Oscillator Characteristics (1/3) Item Symbol Condition MIN. TYP . MAX. Unit MainOSC frequency f MOSC *1,*2 Crystal/Ceramic 16 – 1% 40 + 1% MHz Crystal*5 20 – 100 ppm 20 + 100 ppm MHz MainOSC oscillation operating point VMOSCOP Crystal/Ceramic 1.217 V MainOSC oscillation amplitude V MOSCAMP Crystal/Ceramic 0.9 V MainOSC oscillation stabilization time tMSTB Crystal/Ceramic 5 ms MainOSC oscillation amplifier reaction time tMOSCAMP Crystal/Ceramic 200 μs Internal Capacitor size selectable by MOSC_CAP_SEL setting (OPBT10 setting) C capsel MOSC_CAP_SE L [3:0] = 0000 B = 0001B = 0010B = 0011B = 0100B = 0101B = 0110B = 0111B = 1000B = 1001B = 1010B *4 10 (13.5), 10 (15.0) *4 pF Internal damping resistor size selectable by MOSC_RD_SEL_A and MOSC_RD_SEL_B setting (OPBT10 setting) Rrdsel MOSC_RD_SEL _A [2:0] MOSC_RD_SEL _B [2:0] [U2A-EVA only] = 000 B 169 338 608 Ω = 001B 718 1435 2440 Ω = 010B 1267 2533 4306 Ω = 011B 1711 3422 5475 Ω = 100B 1711 3422 5475 Ω = 101B 1711 3422 5475 Ω = 110B 1711 3422 5475 Ω = 111B 1711 3422 5475 Ω Rrdsel MOSC_RD_SEL _A [2:0] MOSC_RD_SEL _B [2:0] U2A16, U2A8 and U2A6] = 000 B 238 340 578 Ω = 001B 378 540 1026 Ω = 010B 574 820 1435 Ω = 011B 756 1080 1782 Ω = 100B 959 1370 2124 Ω = 101B 1764 2520 3402 Ω = 110B 1764 2520 3402 Ω = 111B 1764 2520 3402 Ω

Page 68 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Trans conductance size (gm) and Output conductance size (gds) selectable by MOSC_SHTSTBY_A, MOSC_AMPSEL_A, MOSC_SHTSTBY_B and, MOSC_AMPSEL_B setting (OPBT10 setting) gm, gds {MOSC_SHTSTB Y_A, MOSC_AMPSEL _A [2:0]} or {MOSC_SHTSTB Y_B, MOSC_AMPSEL _B [2:0]} SYSVCC = 3.0 V to 3.6 V = 0000 Trans conductance size (gm) and Output conductance size (gds) selectable by MOSC_SHTSTBY_A, MOSC_AMPSEL_A, MOSC_SHTSTBY_B and MOSC_AMPSEL_B setting (OPBT10 setting) gm, gds {MOSC_SHTSTB Y_A, MOSC_AMPSEL _A [2:0]} or {MOSC_SHTSTB Y_B, MOSC_AMPSEL _B [2:0]} SYSVCC = 4.5 V to 5.5 V = 0000 X1 clock Input frequency f EX *1 EXCLK mode 15.8 40.0 MHz X1 clock Input cycle time t EXCYC EXCLK mode 25.0 63.1 ns X1 High level Input voltage V IH 0.8 × SYSVCC SYSVCC + 0.3 V X1 Low level Input voltage V IL –0.3 0.2 × SYSVCC V X1 Input leakage current I LIH Vl = SYSVCC 0.5 μA ILIL Vl = 0 V –0.5 μA X1 clock Input low level pulse width tEXL EXCLK mode f EX = 16 MHz 26 ns fEX = 20 MHz 20 ns fEX = 24 MHz 16 ns fEX = 40 MHz 10 ns Table 3.3 Main Oscillator Characteristics (2/3) Item Symbol Condition MIN. TYP . MAX. Unit

Page 69 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Note 1. To reach internal usable clocks only following 4 frequencies are supported: 16MHz, 20MHz, 24MHz and 40MHz. Tolerance of external quartz crystal is assumed as +/–1%. Note 2. The StartUp is supported without external components under following conditions:

See RH850/U2A-EVA Group User's Manual: Hardware Section 51.12.16, OPBT10 — Option Byte 10 for default values of drivability, damping resistance and internal capacitance.
Specification covers a maximum external stray capacitance of up to 6pF to each pin X1 and X2.
After StartUp drivability and capacitance will be configured by OPBT10
A possible exceeding of the recommended maximum drive level for a crystal for all start-up phases has to be agreed with the crystal manufacturers separately. Note 3. Ccapsel_x1 (Ccapsel_x1 including parasitic capacitance to ground at the X1 side), Ccapsel_x2 (Ccapsel_x2 including parasitic capacitance to ground at the X2 side). Note 4. The capacitor tolerance is ±15%. Note 5. The clock source of SGMII used. Ethernet gr ade crystal is mandatory. Example: CX3225GA(KYOCERA) Note 6. 12 kHz to 20 MHz rms jitter = 3 ps. CAUTION Oscillation stabilization times differ according to matching with the resonator. Secure an oscillation stabilization time determined through evaluation of matching. X1 clock Input high level pulse width tEXH EXCLK mode f EX = 16 MHz 26 ns fEX = 20 MHz 20 ns fEX = 24 MHz 16 ns fEX = 40 MHz 10 ns X1 clock rise time tEXR EXCLK mode f EX = 16 MHz 4 ns fEX = 20 MHz 4 ns fEX = 24 MHz 3 ns fEX = 40 MHz 2.5 ns X1 clock fall time tEXF EXCLK mode f EX = 16 MHz 4 ns fEX = 20 MHz 4 ns fEX = 24 MHz 3 ns fEX = 40 MHz 2.5 ns X1 clock Input total jitter (Dj + 14 * rms Random jitter) tCITJ The clock source of SGMII used @ 20MHz 73* 6 ps peak to peak X1 Input capacitance C X1 Main OSC. EXCLK mode, MOSC_CAP_SEL = 0010 10 pF Table 3.3 Main Oscillator Characteristics (3/3) Item Symbol Condition MIN. TYP . MAX. Unit Figure 3.1 Oscillator Circuit Diagram (Crystal with External Components) X1 X2

Page 70 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Figure 3.2 Main OSC Stabilization X1/X2 Power On Reset System Reset 1 System Reset 2 STOP State of MainOSC Disable Unstable Stable MOSC_ADET Hi-Z MOSCS.MOSCSTAB tMSTB VMOSCOP VMOSCAMP Disable Hi-Z tMOSCAMP

Page 71 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.2.1.3 Internal Oscillator Characteristics

Conditions:

See Section 3.2.1.1, Supply Voltage Characteristics.

3.2.1.4 PLL Characteristics

Conditions:

See Section 3.2.1.1, Supply Voltage Characteristics. Note 1. This characteristic is not tested in production. Note 2. Lock time is time until being set “1” in PLLS.PLLCLKSTAB bit after PLLE.PLLENTRG bit is written “1”. Table 3.4 Internal Oscillator Characteristics Item Symbol Condition MIN. TYP. MAX. Unit LS IntOSC frequency fRL 216 240 264 kHz HS IntOSC frequency fRH 190 200 210 MHz HV IntOSC frequency fRHV 81 6 2 4 M Hz Table 3.5 PLL Characteristics Item Symbol Condition MIN. TYP. MAX. Unit PLL output long term jitter*1 tPLLLTJ Term = 1 μs –500 500 ps Term = 10 μs– 1 1 n s Term = 20 μs– 2 2 n s PLL lock time*2 tPLLLCT 112 μs Table 3.6 RHSIF PLL Characteristics Item Symbol Condition MIN. TYP. MAX. Unit PLL lock time tRHPLLLCT 50 μs

Page 72 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.2.1.5 Regulator Characteristics

Conditions:

See Section 3.2.1.1, Supply Voltage Characteristics. Note 1. The capacitors has to be mounted with one of the following connections: - Distribute evenly the total capacitance for the device to all AWOVCL pins. - Concentrate the total capacitance for the device to one AWOVCL pin. In this case, the capacitor has to be connected to F23(BGA516), A22(BGA373), A18(BGA292), 126(QFP176), A13(BGA156) and 103(QFP144). And other AWOVCL pins which capacitor not connected has to be left open. Note 2. This is reference value. Note 3. When returning from DeepSTOP. Note 4. The time of current flow is less than 2.5 μs. Table 3.7 Regulator Characteristics Item Symbol Condition MIN. TYP. MAX. Unit Output voltage VAWOVCL AWOVCL pin 1.025 1.09 1.155 V VGETH0VCL GETH0VCL pin 1.025 1.09 1.155 V Capacitance CAWOVCL AWOVCL pin*1 0.140 0.2 0.286 μF CGETH0VCL GETH0VCL pin 0.154 0.22 0.286 μF Equivalent series resistance for load capacitance RVRAWO for CAWOVCL 40*2 mΩ RVRGETH0 for CGETH0VCL 40*2 mΩ Inrush current during power-on IRUSYSVCC SYSVCC*3 350*2*4 mA IRUGETH0PVCC GETH0PVCC 100*2 mA

Page 73 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Note 1. This is reference value. Note 2. Contact our sale office for the method of setting parameters. Note 3. The total capacitance for the device has to be distributed around thermal ball. Note 4. Operating current variation filtered by simple moving average of 20 μs window can be ignored. Note 5. Operating current variation with smaller than 1 mA/ μs slope is not necessary to be counted as “∆I”. Table 3.8 Switching Voltage Regulator Characteristics Item Symbol Condition MIN. TYP. MAX. Unit Output voltage VDD 1.025 1.09 1.155 V Switching frequency fSVRSW FSWMODE[1:0] = 00B 368 434 500 kHz FSWMODE[1:0] = 01B 736 868 1000 kHz SVR load transient response Less than ∆I (max) –33.5* 1 33.5*1 mV SVR efficiency FSWMODE[1:0] = 00B 80*1 % FSWMODE[1:0] = 01B 70*1 % Capacitance CSVRDRVCC SVRDRVCC pin 9 14 μF CSVRAVCC SVRAVCC pin 0.7 1 1.3 μF CVDD0 VDD pin. Close to LX *2 μF Equivalent series resistance for load capacitance RVRSVRDRVCC for CSVRDRVCC (@0.1MHz to 5MHz) 10 m Ω RVRSVRAVCC for CSVRAVCC (@0.1MHz to 5MHz) 10 m Ω RVRVDD for CVDD0 (@0.1MHz to 5MHz) 10 m Ω Inductance LX Close to external MOSFETs *2 μH DC resistance for inductance RLX for LX *2 mΩ Inrush current during power-on SVRDRVCC include external circuit 4000*1 mA Operating current variation*2*4*5 ∆II ISOVDD_R, U2A16 440 mA/ 100 μs I ISOVDD_R, U2A8 220 IISOVDD_R, U2A6 220 Ramp-up time with soft start tRUT 3.6 ms

Page 74 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Figure 3.3 External Components of Switching Voltage Regulator CSVRAVCC CSVRDRVCC SVRAVSS SVRDRVSS SVRAVCC SVRNGATE SVRDRVSS SVRPGATE VDD SVRDRVCC SVRDRVSS CVDD0 LX VSS VSS RH850/U2A ...

Page 75 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.2.2 Input Voltage Characteristics

Conditions:

See Section 3.2.1.1, Supply Voltage Characteristics. Note 1. "IOVCC" means power supply voltage for I/O ports. See the appendix “E02_01_List_of_Pin_Assignment.xlsx” for the power supply of each pin. Note 3. The configured drive strength of the output terminals in a power group might affect the hysteresis characteristics of the input terminals in the same power group. See Appendix file “E02_01_List_of_Pin_Assignment.xlsx” for the assignment of the power group. Table 3.9 Input Voltage Characteristics Item Symbol Condition*1 MIN. TYP . MAX. Unit High level input voltage V IH1 SHMT1, IOVCC = 3.0 to 5.5 V 0.65 × IOVCC IOVCC + 0.3 V VIH2 SHMT2, IOVCC = 3.0 to 5.5 V 0.75 × IOVCC IOVCC + 0.3 V VIH3 SHMT4, IOVCC = 3.0 to 5.5 V 0.80 × IOVCC IOVCC + 0.3 V VIH4 TTL, IOVCC = 3.0 to 5.5 V 2.2 IOVCC + 0.3 V Low level input voltage V IL1 SHMT1, IOVCC = 3.0 to 5.5 V –0.3 0.35 × IOVCC V VIL2 SHMT2, IOVCC = 3.0 to 5.5 V –0.3 0.25 × IOVCC V VIL3 SHMT4, IOVCC = 3.0 to 5.5 V –0.3 0.50 × IOVCC V VIL4 TTL, IOVCC = 3.0 to 5.5 V –0.3 0.8 V Input hysteresis for Schmitt*3 VHS1 SHMT1, IOVCC = 4.5 to 5.5 V 0.4 V SHMT1, IOVCC = 3.0 to 4.5 V 0.3 V VHS2 SHMT2, IOVCC = 3.0 to 5.5 V 0.2 × IOVCC V VHS3 SHMT4, IOVCC = 3.0 to 5.5 V 0.1 V

Page 76 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.2.3 Input Leakage Current

Conditions:

See Section 3.2.1.1, Supply Voltage Characteristics. Table 3.10 Input Leakage Current Item Symbol Condition MIN. TYP. MAX. Unit Input leakage current ILIH1 Vin = 0 to EnVCC  Pn_m (Except P2_0, P2_5, P2_10 to P2_15, P4_5 to P4_10, P22_0 and P22_4) Tj ≤ 105°C 0.5 μA 105°C < Tj ≤ 150°C 1.0 μA 150°C < Tj 2.0 μA ILIH2 Vin = 0 to EnVCC P4_5 to P4_10, P22_0 and P22_4 Tj ≤ 105°C 0.5 μA 105°C < Tj 2.0 μA I LIH3 Vin = 0 to AnVCC  APn_m Tj ≤ 150°C 0.5 μA 150°C < Tj 1.0 μA ILIL1 Vin = 0 to EnVCC  Pn_m (Except P2_0, P2_5, P2_10 to P2_15, P4_5 to P4_10, P22_0 and P22_4) Tj ≤ 105°C –0.5 μA 105°C < Tj ≤ 150°C –1.0 μA 150°C < Tj –2.0 μA I LIL2 Vin = 0 to EnVCC P4_5 to P4_10, P22_0 and P22_4 Tj ≤ 105°C –0.5 μA 105°C < Tj –2.0 μA I LIL3 Vin = 0 to AnVCC  APn_m Tj ≤ 150°C –0.5 μA 150°C < Tj –1.0 μA

Page 77 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.2.4 Pull-up/Pull-down Characteristics

Conditions:

See Section 3.2.1.1, Supply Voltage Characteristics. Note 1. "IOVCC" means power supply voltage for I/O ports. See the appendix “E02_01_List_of_Pin_Assignment.xlsx” for the power supply of each pin. Table 3.11 Pull-up/Pull-down Characteristics Item Symbol Condition MIN. TYP. MAX. Unit Input pull-up current source IPU1 IOVCC*1 = 3.0 to 5.5V, Vin = 0V 30 350 μA Input pull-down current source IPD1 Other than the below IOVCC* 1 = 3.0 to 5.5V, Vin = IOVCC*1 30 350 μA IPD2 RESET, AURORES1, AURORES2, AURORESPD, ERAMRES2, ERAMRESPD IOVCC*1 = 3.0 to 5.5V, Vin = IOVCC*1 110 μA

Page 78 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.2.5 Output Voltage Characteristics

Conditions:

See Section 3.2.1.1, Supply Voltage Characteristics. Note 1. "IOVCC" means power supply voltage for I/O ports. See the appendix “E02_01_List_of_Pin_Assignment.xlsx” for the power supply of each pin. Note 2. The number of pin indicates simultaneous ON in one power. The influence of the noise emission should be considered when switching the output level. Table 3.12 Output Voltage Characteristics*1 Item Symbol Condition MIN. TYP . MAX. Unit Output resistance RO11 Drive strength = 1 IOVCC – V OH = 0.4 V, VOL = 0.4 V 6 40 Ω RO12 Drive strength = 2 IOVCC – V OH = 0.4 V, VOL = 0.4 V 11 72 Ω RO13 Drive strength = 3 IOVCC – V OH = 0.4 V, VOL = 0.4 V 18 100 Ω RO14 Drive strength = 4 IOVCC – V OH = 0.4 V, VOL = 0.4 V 32 200 Ω RO15 Drive strength = 5 IOVCC – V OH = 0.4 V, VOL = 0.4 V 61 400 Ω High level output voltage V OH1 Drive strength = 1 IOVCC = 3.0 to 5.5 V I OH = –4 mA / pin (4 output pins)*2 IOVCC–0.8 V IOH= –2 mA / pin (4 output pins)*2 IOVCC–0.5 V VOH2 Drive strength = 2 IOVCC = 3.0 to 3.6 V I OH = –4 mA / pin (8 output pins)*2 IOVCC–0.8 V IOH= –2 mA / pin (8 output pins)*2 IOVCC–0.5 V Drive strength = 2 IOVCC = 3.6 to 5.5 V I OH = –4 mA / pin (2 output pins)*2 IOVCC–0.8 V IOH= –2 mA / pin (2 output pins)*2 IOVCC–0.5 V VOH3 Drive strength = 3 IOVCC = 3.0 to 5.5 V I OH = –4 mA / pin (8 output pins)*2 IOVCC–0.8 V IOH = –2 mA / pin (8 output pins)*2 IOVCC–0.5 V VOH4 Drive strength = 4 IOVCC = 3.0 to 5.5 V I OH = –2 mA / pin (16 output pins)*2 IOVCC–0.7 V IOH = –1 mA / pin (16 output pins)*2 IOVCC–0.5 V VOH5 Drive strength = 5 IOVCC = 3.0 to 5.5 V IOH = –1 mA / pin (16 output pins)*2 IOVCC–0.7 V IOH = –500 μA / pin (16 output pins)*2 IOVCC–0.5 V Low level output voltage V OL1 Drive strength = 1 IOVCC = 3.0 to 5.5 V I OL = 4 mA / pin (4 output pins)*2 0.8 V IOL = 2 mA / pin (4 output pins)*2 0.5 V VOL2 Drive strength = 2 IOVCC = 3.0 to 3.6 V I OL = 4 mA / pin (8 output pins)*2 0.8 V IOL = 2 mA / pin (8 output pins)*2 0.5 V Drive strength = 2 IOVCC = 3.0 to 5.5 V I OL = 4 mA / pin (2 output pins)*2 0.8 V IOL = 2 mA / pin (2 output pins)*2 0.5 V VOL3 Drive strength = 3 IOVCC = 3.0 to 5.5 V I OL = 4 mA / pin (8 output pins)*2 0.7 V IOL = 2 mA / pin (8 output pins)*2 0.5 V VOL4 Drive strength = 4 IOVCC = 3.0 to 5.5 V I OL = 2 mA / pin (16 output pins)*2 0.7 V IOL = 1 mA / pin (16 output pins)*2 0.5 V VOL5 Drive strength = 5 IOVCC = 3.0 to 5.5 V I OL = 1 mA / pin (16 output pins)*2 0.7 V IOL = 500 μA / pin (16 output pins)*2 0.5 V

Page 79 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.2.6 Output Current

Conditions:

See Section 3.2.1.1, Supply Voltage Characteristics. Table 3.13 Output Current Characteristics Item Symbol Condition MIN. TYP. MAX. Unit High level output current |IOH| per pin 8 mA Σ|IOH| EnVCC Each EnVCC 60 mA Σ|IOH| AnVCC Each AnVCC 16 mA Low level output current IOL per pin 8 mA Σ IOL EnVCC Each EnVCC 60 mA Σ IOL AnVCC Each AnVCC 16 mA

Page 80 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.2.7 Injection Current Characteristics

Conditions:

See Section 3.2.1.1, Supply Voltage Characteristics. Note 1. Injection current to the logic pin multiplied with LVDS function is prohibited when LVDS function is used. When LVDS function is not used, Injection current to the logic pin multiplied with LVDS function causes at maximum additional 1 μA leakage current at the P/N combinational pin. For example, injection current to HSIF0_TXDP causes at maximum additional 1 μA leakage current at HSIF0_TXDN. NOTE  Injection current to P3_8 pin is prohibited when SGMII function is used.  Input voltage must be kept within –0.8V ≤ Vin ≤ 6.0V, if injection current is kept within rated value.  Power supply voltage must be kept within operating conditions.  Injection current effects power dissipation in the package for thermal characteristics. Table 3.14 Injection Current Operating Conditions Item Symbol Condition MIN. TYP . MAX. Unit DC injection current (per pin) I INJ_DIN Digital pin *1 –2 3 mA IINJ_AIN Analogue pin –3 3 mA DC injection current (each power supply) IINJ_E0VCC E0VCC 50 mA IINJ_E1VCC E1VCC 50 mA IINJ_E2VCC E2VCC 30 mA IINJ_A0VCC A0VCC 20 mA IINJ_A1VCC A1VCC 20 mA IINJ_A2VCC A2VCC 20 mA DC injection current (total) I INJ_TOTAL 80 mA

Page 81 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.2.8 LVDS Characteristics

3.2.8.1 LVDS Driver Characteristics

Conditions:

See Section 3.2.1.1, Supply Voltage Characteristics. Table 3.15 LVDS Driver Characteristics (based on IEEE 1596.3-1996) Item Symbol Condition MIN. TYP . MAX. Unit Output low-level voltage VLVDSOL 1000 mV Output high-level voltage VLVDSOH 1400 mV Output differential voltage VLVDSOD 150 250 mV Offset voltage VLVDSOS 1.125 1.2 1.275 V Output impedance RLVDSOI 40 300 Ω Figure 3.4 LVDS Driver Measurement Conditions Transmission signal Terminating register 100 Ω ± 1 % Inside the microcomputer (schematic) Outside the microcomputer Figure 3.5 Meaning of LVDS Driver Symbols VLVDSOD VLVDSOH VLVDSOVLVDSOS VSS

Page 82 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.2.8.2 LVDS Receiver Characteristics

Conditions:

See Section 3.2.1.1, Supply Voltage Characteristics. Table 3.16 LVDS Receiver Characteristics (based on IEEE 1596.3-1996) Item Symbol Condition MIN. TYP . MAX. Unit Differential Input threshold voltage VLVDSIDTH –100 100 mV Input voltage range VLVDI 0.825 1.575 V Figure 3.6 LVDS Receiver Measurement Conditions Received signalTerminating register 100 Ω ± 1 % Inside the microcomputer (schematic) Outside the microcomputer Figure 3.7 Meaning of LVDS Receiver Symbols VLVDIVLVDI VLVDSIDTH VSS

Page 83 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.2.9 SGMII Characteristics

Conditions:

See Section 3.2.1.1, Supply Voltage Characteristics. Note 1. For details of the symbols, refer to the IEEE1596.3-1996 standard. Note 2. All parameters measured at Rload = 100 Ω ±1 % load Note 1. For details of the symbols, refer to the IEEE1596.3-1996 standard. Table 3.17 SGMII REFCK Characteristics Item Symbol Condition MIN. TYP. MAX. Unit High level input voltage VIH 2.0 GETH0RVCC + 0.3 V Low level input voltage VIL –0.3 0.8 V Table 3.18 SGMII Tx Buffer Characteristics Item Symbol Condition MIN. TYP. MAX. Unit Output voltage high VOH 1525 mV Output voltage low VOL 875 mV Output Differential Voltage |V OD| 150 400 mV Output Offset Voltage VOS 1075 1325 mV Change in VOD between “0” and “1” Δ|VOD|2 5 mV Change in VOS between “0” and “1” ΔVOS 25 mV Output current on Short to GND I sa, Isb 40 mA Output current when a, b are shorted Isab 12 mA Table 3.19 SGMII Rx Buffer Characteristics Item Symbol Condition MIN. TYP. MAX. Unit Input Voltage range a or b V I 675 1725 mV Input differential threshold V idth –50 50 mV Receiver differential input impedance R in 80 120 Ω

Page 84 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.2.10 Aurora Interface Clock Characteristics

Conditions:

See Section 3.2.1.1, Supply Voltage Characteristics. Note 1. Peak to peak differential input voltage. Note 1. Peak to peak differential input voltage. Table 3.20 Aurora Interface Clock Characteristics (CICREFP, CICREFN) Item Symbol Condition MIN. TYP . MAX. Unit Differential input voltage VDIFFCIC *1 200 1600 mV External AC coupling capacitor C ACC 75 100 200 nF Differential input resistance ZDIFFCIC 70 100 130 Ω Table 3.21 Aurora Interface Characteristics (TODP0-3/TODN0-3) Item Symbol Condition MIN. TYP . MAX. Unit Differential output voltage VDIFFTOD *1 800 1600 mV Differential output resistance ZDIFFTOD 70 130 Ω

Page 85 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.2.11 IO Capacitances

Conditions:

See Section 3.2.1.1, Supply Voltage Characteristics. Note 1. This capacity is the capacity va lue per BGA_Ball (QFP_Pin) 1 terminal. Note 2. For analog input pins (ADCJnIm and ADCJnImS), refer to Section 3.4, A/D Converter Characteristics. Table 3.22 IO Capacitances *1, *2 Item Symbol Condition MIN. TYP. MAX. Unit Input capacitance CI f = 1 MHz

0 V for non measurement pins

Input/output capacitance C IO 10 pF Output capacitance C O 10 pF

Page 86 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.2.12 Supply Current Characteristics

3.2.12.1 General Definition

Power consumption except for the current of I/O buffer (IEnVCC) is specified below. The parameter IEnVCC depends on customer’s application and thus need to be defined by customer in order to determine the total power dissipation of a device.

Page 87 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.2.12.2 Power Supply Currents

Conditions:

See Section 3.2.1.1, Supply Voltage Characteristics. Note 1. The condition of “TYP .” shows the specification with the following conditions. Also, the value is just for reference only. - Tj = 25°C - SYSVCC = VCC = EnVCC = LVDVCC = AnVCC = AnVREFH = SVRDRVCC = SVRAVCC = 5.0 V - GETH0PVCC = GETH0BVCC = GETH0RVCC = 3.3 V - ISOVDD = 1.09 V Note 2. The above value does not include the current of SVR converter. Note 3. The above value does not include the current of I/O buffer. Note 4. Indicated leak current will be applied if the power continues supplying to ISOVDD during DeepSTOP mode. Note 5. Additional current (max.60 mA for Code Flash per unit, max.35 mA for Data Flash per unit) will be applied when data writing/erasing to Code or Data Flash is processing. Note 6. MainOSC and all peripherals are stopped. Table 3.23 Current consumption for RH850/U2A-EVA*2, *3 Item Symbol Power supply CPU frequency MIN. TYP.*1 MAX. Unit RUN mode current ISYSVCC_R SYSVCC 400 MHz 6 34 mA

320 MHz 6 34 mA

240 MHz 6 34 mA

IVCC_R VCC*5 400 MHz 22 45 mA

320 MHz 22 45 mA

240 MHz 22 45 mA

IISOVDD_R ISOVDD 400 MHz 480 1870 mA

320 MHz 405 1694 mA

240 MHz 330 1518 mA

STOP mode current*6 ISYSVCC_S SYSVCC 3 20 mA IVCC_S VCC 0.005 1 mA IISOVDD_S ISOVDD 385 1300 mA DeepSTOP mode current*6 ISYSVCC_DS SYSVCC 0.52 12 mA IVCC_DS VCC 2 400 μA IISOVDD_DS ISOVDD 14*4 900*4 mA Cyclic RUN mode current*6 ISYSVCC_CR SYSVCC 100 MHz 4 32 mA IVCC_CR VCC 100 MHz 0.008 1.2 mA IISOVDD_CR ISOVDD 100 MHz 405 1350 mA Cyclic STOP mode current*6 ISYSVCC_CS SYSVCC 3 20 mA IVCC_CS VCC 0.005 1 mA IISOVDD_CS ISOVDD 385 1300 mA

Page 88 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Note 1. The condition of “TYP .” shows the specification with the following conditions. Also, the value is just for reference only. - Tj = 25°C - SYSVCC = VCC = EnVCC = LVDVCC = AnVCC = AnVREFH = SVRDRVCC = SVRAVCC = 5.0 V - GETH0PVCC = GETH0BVCC = GETH0RVCC = 3.3 V - ISOVDD = 1.09 V Note 2. The above value does not include the current of SVR converter. Note 3. The above value does not include the current of I/O buffer. Note 4. Indicated leak current will be applied if the power continues supplying to ISOVDD during DeepSTOP mode. Note 5. Additional current (max.60 mA for Code Flash per unit, max.35 mA for Data Flash per unit) will be applied when data writing/erasing to Code or Data Flash is processing. Note 6. MainOSC is stopped. Table 3.24 Current consumption for RH850/U2A-EVA (specific power supply) Item Symbol Condition MIN. TYP. MAX. Unit EMUVCC IEMUVCC 20 mA DVCC IDVCC 20 mA ERAMVCC IERAMVCC 5 mA EMUVDD IEMUVDD 20 mA DVDD IDVDD 350 mA ERAMVDD IERAMVDD 250 mA Table 3.25 Current consumption for RH850/U2A16*2, *3 Item Symbol Power supply CPU frequency MIN. TYP.*1 MAX. Unit RUN mode current ISYSVCC_R SYSVCC 400 MHz 6 34 mA IVCC_R VCC*5 400 MHz 11 35 mA

320 MHz 11 35 mA

240 MHz 11 35 mA

IISOVDD_R ISOVDD 400 MHz 420 1650 mA

320 MHz 355 1483 mA

240 MHz 290 1316 mA

STOP mode current*6 ISYSVCC_S SYSVCC 3 20 mA IVCC_S VCC 0.005 1 mA IISOVDD_S ISOVDD 335 1130 mA DeepSTOP mode current*6 ISYSVCC_DS SYSVCC 0.52 12 mA IVCC_DS VCC 2 400 μA IISOVDD_DS ISOVDD 12*4 730*4 mA Cyclic RUN mode current*6 ISYSVCC_CR SYSVCC 100 MHz 4 32 mA IVCC_CR VCC 100 MHz 0.008 1.2 mA IISOVDD_CR ISOVDD 100 MHz 350 1180 mA Cyclic STOP mode current*6 ISYSVCC_CS SYSVCC 3 20 mA IVCC_CS VCC 0.005 1 mA IISOVDD_CS ISOVDD 335 1130 mA

Page 89 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Note 1. The condition of “TYP .” shows the specification with the following conditions. Also, the value is just for reference only. - Tj = 25°C - SYSVCC = VCC = EnVCC = LVDVCC = AnVCC = AnVREFH = SVRDRVCC = SVRAVCC = 5.0 V - GETH0PVCC = GETH0BVCC = GETH0RVCC = 3.3 V - ISOVDD = 1.09 V Note 2. The above value does not include the current of SVR converter. Note 3. The above value does not include the current of I/O buffer. Note 4. Indicated leak current will be applied if the power continues supplying to ISOVDD during DeepSTOP mode. Note 5. Additional current (max.60 mA for Code Flash per unit, max.35 mA for Data Flash per unit) will be applied when data writing/erasing to Code or Data Flash is processing. Note 6. MainOSC is stopped. Table 3.26 Current consumption for RH850/U2A8*2, *3 Item Symbol Power supply CPU frequency MIN. TYP.*1 MAX. Unit RUN mode current ISYSVCC_R SYSVCC 400 MHz 6 30 mA

320 MHz 6 30 mA

240 MHz 6 30 mA

IVCC_R VCC*5 400 MHz 9 28 mA

320 MHz 9 28 mA

240 MHz 9 28 mA

IISOVDD_R ISOVDD 400 MHz 245 870 mA

320 MHz 210 780 mA

240 MHz 175 690 mA

STOP mode current*6 ISYSVCC_S SYSVCC 3 16 mA IVCC_S VCC 0.005 0.6 mA IISOVDD_S ISOVDD 170 580 mA DeepSTOP mode current*6 ISYSVCC_DS SYSVCC 0.46 8 mA IVCC_DS VCC 2 320 μA IISOVDD_DS ISOVDD 5*4 385*4 mA Cyclic RUN mode current*6 ISYSVCC_CR SYSVCC 100 MHz 4 28 mA IVCC_CR VCC 100 MHz 0.008 0.8 mA IISOVDD_CR ISOVDD 100 MHz 180 620 mA Cyclic STOP mode current*6 ISYSVCC_CS SYSVCC 3 16 mA IVCC_CS VCC 0.005 0.6 mA IISOVDD_CS ISOVDD 170 580 mA

Page 90 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Note 1. The condition of “TYP .” shows the specification with the following conditions. Also, the value is just for reference only. - Tj = 25°C - SYSVCC = VCC = EnVCC = AnVCC = AnVREFH = SVRDRVCC = SVRAVCC = 5.0 V - ISOVDD = 1.09 V Note 2. The above value does not include the current of SVR converter. Note 3. The above value does not include the current of I/O buffer. Note 4. Indicated leak current will be applied if the power continues supplying to ISOVDD during DeepSTOP mode. Note 5. Additional current (max.60 mA for Code Flash per unit, max.35 mA for Data Flash per unit) will be applied when data writing/erasing to Code or Data Flash is processing. Note 6. MainOSC is stopped. Table 3.27 Current consumption for RH850/U2A6*2, *3 Item Symbol Power supply CPU frequency MIN. TYP.*1 MAX. Unit RUN mode current ISYSVCC_R SYSVCC 400 MHz 6 30 mA IVCC_R VCC*5 400 MHz 9 28 mA IISOVDD_R ISOVDD 400 MHz 240 840 mA

320 MHz 207 755 mA

240 MHz 173 670 mA

STOP mode current*6 ISYSVCC_S SYSVCC 3 16 mA IVCC_S VCC 0.005 0.6 mA IISOVDD_S ISOVDD 168 570 mA DeepSTOP mode current*6 ISYSVCC_DS SYSVCC 0.46 8 mA IVCC_DS VCC 2 320 μA IISOVDD_DS ISOVDD 4*4 375*4 mA Cyclic RUN mode current*6 ISYSVCC_CR SYSVCC 100 MHz 4 28 mA IVCC_CR VCC 100 MHz 0.008 0.8 mA IISOVDD_CR ISOVDD 100 MHz 178 610 mA Cyclic STOP mode current*6 ISYSVCC_CS SYSVCC 3 16 mA IVCC_CS VCC 0.005 0.6 mA IISOVDD_CS ISOVDD 168 570 mA

Page 91 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.2.12.3 Power Supply Currents for specific features

Conditions:

See Section 3.2.1.1, Supply Voltage Characteristics. Note 1. This table shows additional current w hen the specific function indicated above is used. Note 2. For QFP package and BGA156 package, the current of AnVREFH (IADCnREF) is total of AnVREFH current (IADCnREF) and AnVCC current (IADCn). Table 3.28 Current consumption for specific features*1 Item Symbol Condition MIN. TYP. MAX. Unit SVR converter ISVR Current of SYSVCC 4 mA ISVRA Current of SVRAVCC 12 mA LVDS for RHSIF/MSPI I LVDS Current of LVDVCC 16 mA Gigabit Ethernet IGBETH Current of GETH0BVCC, GETH0RVCC and GETH0PVCC 90 mA ADCJ0 I ADC0*2 Current of A0VCC 4ch T&H function is used 5.7 mA I ADC0REF*2 Current of A0VREFH 0.2 mA ADCJ1 IADC1*2 Current of A1VCC 4ch T&H function is used 5.7 mA IADC1REF*2 Current of A1VREFH 0.2 mA ADCJ2 IADC2*2 Current of A2VCC 2.9 mA IADC2REF*2 Current of A2VREFH 0.2 mA

Page 92 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.2.13 Voltage Detector (POC, VLVI) Characteristics

Conditions:

See Section 3.2.1.1, Supply Voltage Characteristics. Note 1. POC monitors SYSVCC supply voltage. Table 3.29 Voltage Detector (POC, VLVI) Characteristics*1 Item Symbol Condition MIN. TYP. MAX. Unit Detection voltage (SYSVCC) VPOC 2.5 2.63 2.75 V VVLVI 1.9 2.0 2.1 V Response time tDPOC1 Rise 1.2 ms tDPOC2 Fall 10 μs SYSVCC minimum pulse width tWPOC 0.2 ms SYSVCC voltage ramp tSYSVS 0.002 550 ms/V Figure 3.8 POC Characteristics tWPOC SYSVCC VPOC (MAX.) VPOC (TYP.) VPOC (MIN.) tDPOC1 tDPOC2 tSYSVS tSYSVS tDPOC1 POCRES

Page 93 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.2.14 VMON Characteristics

Conditions:

See Section 3.2.1.1, Supply Voltage Characteristics. Note 1. See RH850/U2A-EVA Group User's Manual: Hardware Section 11.3.6, Registers for details specification of filter time. Table 3.30 VMON Characteristics*1 Item Symbol Condition MIN. TYP . MAX. Unit VDD primary high detection level V VDDMAH AWOVDD 1.155 1.17 1.205 V VVDDMIH ISOVDD 1.155 1.17 1.205 V VDD primary low detection level V VDDMAL AWOVDD 0.975 1.01 1.025 V VVDDMIL ISOVDD Enable assist by Delay Monitor (DMON) 0.985 1.01 1.025 V VCC primary high detection level V VCCMH 5.5 5.64 5.8 V VCC primary low detection level V VCCML 2.8 2.9 3 V E0VCC primary high detection level V EVCCMH 5.5 5.64 5.8 V E0VCC primary low detection level V EVCCML 2.8 2.9 3 V VMONOUT delay time tDVMON 10+Filter time*1 μs VMON minimum pulse width tWVMON 0.2 ms Voltage ramp tVS 0.002 550 ms/V Figure 3.9 VMON Characteristics tVS tWVMON tDVMON tWVMON tVS tDVMON tDVMON tDVMON High detection level (max) Low detection level (min) VMONOUT

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3.3 AC Characteristics

3.3.1 AC Characteristic Measurement Condition

3.3.1.1 General Conditions

Below conditions are valid for all subsequent timing specifications if not noted otherwise:

See Section 3.2.1.1, Supply Voltage Characteristics.
Drive strength = 3
CL = 30 pF
All bits of PINVn/JPINV0 are set as 0.
All bits of PODCn/JPODC0 are set as 0 except for specificati on on RIIC timing. NOTE Even though AC characteristics correspond to the nominal frequency, a main oscillator tolerance of up to 1000 ppm is considered with regard to timing characteristics for communication modules.

3.3.1.2 Input Measurement Points

If not stated otherwise, the below given AC timing specification is based on the measurements points as follows: Figure 3.10 AC Input Measurement Points EnVCC VSS 0.8 × EnVCC 0.2 × EnVCC Test points 0.8 × EnVCC 0.2 × EnVCC

Page 95 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.3.1.3 Output Measurement Points

If not stated otherwise, the below given AC timing specification is based on the measurements points as follows: Figure 3.11 AC Output Measurement Points

3.3.1.4 Load conditions

0.8 ×EnVCC Test points 0.2 ×EnVCC 0.8 ×EnVCC 0.2 ×EnVCC Figure 3.12 AC Load Conditions DUT (device under test) CL = 30 pF

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3.3.2 Power On/Off Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. Note 1. t RESH1 is the reset time required for the supply of internal clock signals to become stable after power supplies are turned on. There are no restrictions on the rising order of each power supply. Note 2. t PWH is the time from assertion of the reset signal until any of the power voltages have dropped below the lower-limit voltages. There are no restrictions on the falling order of each power supply. Note 3. t PLLL is the time required for PLL to lock in after MOSC oscillation has become stable. Note 4. Access by the Nexus, LPD and BSCAN during t TRMDH duration is prohibited (both of High and low condition of TRST). Note 5. The device can withstand up to 1000 uncontro lled power down cycles without impact on lifetime. Uncontrolled means not according to power down timing requirements. Note 6. Objection of power supplies for t RESH1, tTRSTH1 and tMDL1 is changed by power configuration. When SVR is used:All power supplies except for ISOVDD When SVR is not used: All power supplies Table 3.31 Power On/Off Timing Item Symbol Condition MIN. TYP. MAX. Unit Reset hold time at power-on tRESH1*6 Power-up*1 SVR is used 1.3 + tRUT ms Power-up*1 SVR is not used 1.3 ms Power hold time at reset assertion*5 tPWH Power-down*2 (ETNB1 (SGMII) used) 64 μs Power-down*2 (ETNB1 (SGMII) not used) 10.5 μs Operation mode low level hold time at power-on t MDL1*6 SVR is used 0.1 + t RUT ms SVR is not used 0.1 ms Operating mode setup time at power-on t MDS1 1m s Operating mode setup time at reset assert t MDS2 1m s Operating mode hold time at reset negate t MDH1 1m s Operating mode hold time at power-off tMDH2 0 μs TRST setup time at reset tTRMDS 2 μs TRST hold time at reset negate*4 tTRMDH 30 ms TRST hold time at power-on tTRSTH1*6 SVR is used 1.29 + t RUT ms SVR is not used 1.29 ms TRST hold time at power-off tTRSTH3 Time since SYSVCC and VDD were power-off. 10 μs Oscillator stabilization time t OSC 5.5 ms PLL lock in time tPLLL *3 1m s EMUVDD hold time at power-on tEMUVDDH1 0m s EMUVDD setup time at power-off tEMUVDDS1 0m s

Page 97 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics CAUTION The states of I/O pins are not reset during the noise cancellation interval of the reset signal following its assertion while power is being turned off. During that time, do not allow any input of mid-range potential to the pin or contention of output data. NOTE DVCC, DVDD, ERAMVCC, ERAMVDD and EMUVDD are not included in the other power voltages. For power on/off timing about those power sources, see Figure 3.18, EMUVCC, EMUVDD Power On / Off Timings and Section 3.3.30, Debug Resource (Aurora, ERAM) Specific Reset Timing. Figure 3.13 Power On/Off Timings (Normal operating mode and User boot mode 0) tPWH tPWH tPWH tPWH tPWH tPLLLtOSC tTRMDH tTRMDStTRMDStTRSTH1 tRESH1 tMDH1 tMDS2 SYSVCC, VCC, AD_VCC min DRV_VCC min EnVCC min VDD min Min operating voltage for each power supply SYSVCC, VCC, SVRAVCC SVRDRVCC EnVCC ISOVDD MOSC PLL Other power voltages SYSVCC, VCC, AD_VCC min DRV_VCC min EnVCC min VDD min Min operating voltage for each power supply RESET FLMD0 TRST

Page 98 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics NOTE DVCC, DVDD, ERAMVCC, ERAMVDD and EMUVDD are not included in the other power voltages. For power on/off timing about those power sources, see Figure 3.18, EMUVCC, EMUVDD Power On / Off Timings and Section 3.3.30, Debug Resource (Aurora, ERAM) Specific Reset Timing. Figure 3.14 Power On/Off Timings (Serial programming mode 0) tPWH tPWH tPWH tPWH tPWH tPLLLtOSC tRESH1 tMDH1 tMDS2 SYSVCC, VCC, AD_VCC min DRV_VCC min EnVCC min VDD min Min operating voltage for each power supply SYSVCC, VCC, SVRAVCC SVRDRVCC EnVCC ISOVDD MOSC PLL Other power voltages SYSVCC, VCC, AD_VCC min DRV_VCC min EnVCC min VDD min Min operating voltage for each power supply RESET FLMD0

Page 99 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics NOTE DVCC, DVDD, ERAMVCC, ERAMVDD and EMUVDD are not included in the other power voltages. For power on/off timing about those power sources, see Figure 3.18, EMUVCC, EMUVDD Power On / Off Timings and Section 3.3.30, Debug Resource (Aurora, ERAM) Specific Reset Timing. Figure 3.15 Power On/Off Timings (Serial programming mode 1) tPWH tPWH tPWH tPWH tPWH tPLLLtOSC tRESH1 tMDH1 tMDH2 SYSVCC, VCC, AD_VCC min DRV_VCC min EnVCC min VDD min Min operating voltage for each power supply SYSVCC, VCC, SVRAVCC SVRDRVCC EnVCC VDD MOSC PLL Other power voltages SYSVCC, VCC, AD_VCC min DRV_VCC min EnVCC min VDD min Min operating voltage for each power supply RESET FLMD0 FLMD1 “L” tMDS1tMDL1

Page 100 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics NOTE DVCC, DVDD, ERAMVCC, ERAMVDD and EMUVDD are not included in the other power voltages. For power on/off timing about those power sources, see Figure 3.18, EMUVCC, EMUVDD Power On / Off Timings and Section 3.3.30, Debug Resource (Aurora, ERAM) Specific Reset Timing. Figure 3.16 Power On/Off Timings (User boot mode 1) tRESH1 tMDH2 RESET FLMD0, FLMD1 FLMD2 “L” tMDS1tMDL1 tPWH tPWH tPWH tPWH tPWH tPLLLtOSC tTRMDH tTRMDStTRMDStTRSTH1 SYSVCC, VCC, AD_VCC min DRV_VCC min EnVCC min VDD min Min operating voltage for each power supply SYSVCC, VCC, SVRAVCC SVRDRVCC EnVCC VDD MOSC PLL Other power voltages SYSVCC, VCC, AD_VCC min DRV_VCC min EnVCC min VDD min Min operating voltage for each power supply TRST

Page 102 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.3.2.1 Power Up Sequencing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition Note 1. tBIST means BIST run time. Refer to Table 44.490, BIST scenario selection at the next System Reset 2 on RH850/U2A-EVA Group User's Manual: Hardware Section 44.6.2.41, BSEQ0SEL — BIST Scenario Select Register for details. Note that the given BIST run time is the typical value and the tolerance of the corresponding clock needs to be taken into account for the maximum value.

3.3.3 Standby Transition/Return Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition Table 3.32 Power Up Sequencing Item Symbol Condition MIN. TYP. MAX. Unit Runtime from release of RESET to start of instruction fetch 1.5 + tBIST*1 ms Table 3.33 DeepSTOP Transition/Return Timing In case of VDD External Supply Item Symbol Condition MIN. TYP . MAX. Unit Wake-up trigger to PWRCTL delay time t DPWRCTL 100 μs VDD hold time tHDD 0 μs VDD power-on start time tPDD 0 μs

Page 103 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.3.4 Clock Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. Note 1. There is a function to output the internal clock via EXTCLKnO pin. NOTE For base clock, refer to related RH850/U2A-EVA Group User's Manual: Hardware Section 13, Clock Controller. Table 3.34 Clock Output Timing*1 Item Symbol Condition MIN. TYP. MAX. Unit Clock output period time t CLKOUT 41.6 ns Clock output high level width t WCOH tCLKOUT / 2 – 10 ns Clock output low level width t WCOL tCLKOUT / 2 – 10 ns Figure 3.19 Clock Output Timing EXTCLKnO tCLKOUT tWCOH tWCOL

Page 104 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.3.5 Output Slew Rate

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. Table 3.35 Output Slew Rate Item Symbol Condition MIN. TYP . MAX. Unit Output rise and fall time t KRP11/tKFP11 Drive strength = 1 20% to 80% CL = 100 pF 6.7 ns tKRP12/tKFP12 Drive strength = 2 20% to 80% CL = 30 pF 4.0 ns CL = 50 pF 6.7 ns CL = 100 pF 13.4 ns tKRP13/tKFP13 Drive strength = 3 20% to 80% CL = 30p F 6.7 ns CL = 50 pF 11.1 ns CL = 100 pF 21.0 ns tKRP14/tKFP14 Drive strength = 4 20% to 80% CL = 30 pF 13.5 ns CL = 50 pF 22.5 ns CL = 100 pF 45.0 ns t KRP15/tKFP15 Drive strength = 5 20% to 80% CL = 30 pF 27.0 ns CL = 50 pF 45.0 ns CL = 100 pF 90.0 ns

Page 105 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.3.6 Control Signal Timing

3.3.6.1 RESET Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. Note 1. t WRSL is the minimum required time to complete the reset state generated by an external reset signal. When an external reset signal is input that is shorter than this time, the reset state will continue even after the external reset release. This microcontroller is completely reset after completion of the reset state. An external reset request is accepted with a reset input width of more than the maximum time of tWRRJ. When the reset pulse width is less than the minimum value of the reset noise rejection width, the reset request is not accepted. When the reset signal is input during DeepSTOP mode, the reset state will continue during the wait time set by PWRGD_CNT even when the external reset signal is released. filtered out or not). This characteristic is not tested in production. Table 3.36 RESET Timing Item Symbol Condition MIN. TYP . MAX. Unit RESET input low level width tWRSL*1 800 μs RESET pulse rejection width*2 tWRRJ 400 2400 ns Figure 3.20 RESET Timing Reset signal after passing through noise filter tWRSL tWRRJ tWRRJ RESET

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3.3.6.2 Interrupt, Wake-up and Error Input Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. Note 1. S: Number of sampling times fs: The value given by following formula fDNFCK: frequency of CLK_LSB filtered out or not). This characteristic is not tested in production. Note 3. Edge Detection or Level Detecti on (CLKA_LPS is operated by CLK_HSIOSC/20) Note 4. Level Detection (CLKA _LPS is operated by CLK_LSIOSC) Table 3.37 Interrupt Timing Item Symbol Condition MIN. TYP . MAX. Unit NMI input high level width tWNIH *3 600 ns *4 20 μs NMI input low level width tWNIL *3 600 ns *4 20 μs NMI pulse rejection width*2 tWNIRJ 100 600 ns INTPn input high level width tWITH *3 600 ns *4 20 μs INTPn input low level width tWITL *3 600 ns *4 20 μs INTPn pulse rejection width*2 tWIRJ 100 600 ns RLIN3nRX wake-up input high level width t WRLINH (S + 1) x 1/fs*1 ns RLIN3nRX wake-up input low level width t WRLINL (S + 1) x 1/fs*1 ns RLIN3nRX wake-up pulse rejection width*2 tWRLINRJ (S – 1) x 1/fs*1 (S + 1) x 1/fs*1 ns CANnRX wake-up input high level width t WCANH (S + 1) x 1/fs*1 ns CANnRX wake-up input low level width t WCANL (S + 1) x 1/fs*1 ns CANnRX wake-up pulse rejection width*2 tWCANRJ (S – 1) x 1/fs*1 (S + 1) x 1/fs*1 ns FLXnRXDA wake-up input high level width t WFLXH (S + 1) x 1/fs*1 ns FLXnRXDA wake-up input low level width t WFLXL (S + 1) x 1/fs*1 ns FLXnRXDA wake-up pulse rejection width*2 tWFLXRJ (S – 1) x 1/fs*1 (S + 1) x 1/fs*1 ns ERRORINn wake-up input high level width t WERRH (S + 1) x 1/fs*1 ns ERRORINn wake-up input low level width t WERRL (S + 1) x 1/fs*1 ns ERRORINn wake-up pulse rejection width*2 tWERRRJ (S – 1) x 1/fs*1 (S + 1) x 1/fs*1 ns fs fDNFCK

Page 107 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Figure 3.21 Interrupt, wake-up and error input timing tWNIRJ NMI tWNIRJ tWNIH tWNIL tWIRJ INTPn tWIRJ tWITH tWITL

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3.3.6.3 Mode Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. filtered out or not). This characteristic is not tested in production. NOTE Switching of FLMD0 after rising edge of RESET is prohibited except for serial programming mode. Table 3.38 Mode Timing Item Symbol Condition MIN. TYP. MAX. Unit FLMD0, FLMD1, FLMD2, MODE0 input high level width tWMDH 600 ns FLMD0, FLMD1, FLMD2, MODE0 input low level width tWMDL 600 ns FLMD0, FLMD1, FLMD2, MODE0 pulse rejection width* tWMDRJ 100 600 ns Figure 3.22 Mode Timing FLMD0 FLMD1 FLMD2 MODE0 tWMDH tWMDL tWMDRJ tWMDRJ

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3.3.6.4 ADTRG Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. Note 1. S: Number of sampling times fs: The value given by the following formula fDNFCK: frequency of CLK_ADC, CLKA_ADC filtered out or not). This characteristic is not tested in production. Table 3.39 ADCJnTRGm Timing Item Symbol Condition MIN. TYP . MAX. Unit ADCJnTRGm input high level width t WADH (S + 1) x 1/fs*1 ns ADCJnTRGm input low level width t WADL (S + 1) x 1/fs*1 ns ADCJnTRGm pulse rejection width*2 tWADRJ (S – 1) x 1/fs*1 (S + 1) x 1/fs*1 ns fs fDNFCK Figure 3.23 ADCJnTRGm Timing ADCJnTRGm tWADH tWADL

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3.3.6.5 Communication Signal Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. Note 1. S: Number of sampling times fs: The value given by the following formula fDNFCK: frequency of CLK_HSB filtered out or not). This characteristic is not tested in production.

3.3.7 Low Power Sampler (DPIN input) Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition.
Drive strength = 4 (SELDP2-0) Table 3.40 Control Signal Item Symbol Condition MIN. TYP . MAX. Unit SENTnRX input high level width t WSENTIH Analog filter 600 ns Digital filter (S + 1) x 1/fs* 1 ns SENTnRX input low level width t WSENTIL Analog filter 600 ns Digital filter (S + 1) x 1/fs* 1 ns SENTnRX pulse rejection width t WSENTIRJ Analog filter 100 600 ns Digital filter (S – 1) x 1/fs* 1 (S + 1) x 1/fs*1 ns PSI5nRX input high level width*2 tWPSI5IH Analog filter 600 ns Digital filter (S + 1) x 1/fs* 1 ns PSI5nRX input low level width tWPSI5IL Analog filter 600 ns Digital filter (S + 1) x 1/fs* 1 ns PSI5nRX pulse rejection width*2 tWPSI5IRJ Analog filter 100 600 ns Digital filter (S – 1) x 1/fs* 1 (S + 1) x 1/fs*1 ns fs fDNFCK Table 3.41 Low Power Sampler Timing Item Symbol Condition MIN. TYP . MAX. Unit DPINn input delay time tDSDDI 150 ns

Page 111 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Figure 3.24 Low Power Sampler Timing tDSDDI SELDP2-0 DPINn

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3.3.8 SFMA Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition.
Drive strength = 2
Buffer type = Sch1 Table 3.42 SFMA Timing Item Symbol Condition MIN. TYP. MAX. Unit SFMA0CLK clock cycle t SFMAcyc 25 ns SFMA0CLK high pulse width t SFMAWH 0.4 × tSFMA0cyc 0.6 × tSFMA0cyc ns SFMA0CLK low pulse width t SFMAWL 0.4 × tSFMA0cyc 0.6 × tSFMA0cyc ns Data input setup time tSFMADIS 9.0 ns Data input hold time tSFMDIH 0.0 ns SFMA0SSL setup time t SFMASS 1 × tSFMA0cyc – 12.5 8 × tSFMA0cyc ns SFMA0SSL hold time tSFMASH 1.5 × tSFMA0cyc 8.5 × tSFMA0cyc + 12.5 ns Continuous transfer delay time t SFMACTD 1 × tSFMA0cyc 8 × tSFMA0cyc ns Data output delay time tSFMADOD 6.6 ns Data output hold time tSFMADOH –4.6 ns Data output buffer on time t SFMADBON 6.6 ns Data output buffer off time t SFMADBOFF –7.0 3.0 ns Figure 3.25 SFMA Clock Output Timing SFMA0CLK Output tSFMAWL tSFMAcyc tSFMAWH

Page 114 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Figure 3.29 SFMA Timing for Switching the Buffers on and off (CPHAT = 1, CPHAR = 1) SFMA0CLK CPOL = 0 Output SFMA0CLK CPOL = 1 Output SFMA0O[3:0] Output tSFMADBOFF (min) tSFMADBON tSFMADBOFF (max)

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3.3.9 MMCA Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition.
Drive strength = 2
Buffer type = Sch1 Table 3.43 MMCA Timing Item Symbol Condition MIN. TYP. MAX. Unit MMCA0CLK clock cycle tMMCA0CYC 25 ns MMCA0CLK high time tMMCA0WH 6.5 ns MMCA0CLK low time tMMCA0WL 6.5 ns MMCA0CMD output data delay time t MMCA0CMDD – 6.5 6.5 ns Data output delay time tMMCA0DADD – 6.5 6.5 ns MMCA0CMD input data setup time t MMCA0CMS 7.5 ns MMCA0CMD input data hold time t MMCA0CMH 2.5 ns Data input setup time tMMCA0DAS 7.5 ns Data input hold time tMMCA0DAH 2.5 ns Figure 3.30 MMCA Timing MMCA0CLK (out) MMCA0CMD (out) MMCA0DAT[7:0] (out) MMCA0CMD (in) MMCA0DAT[7:0] (in) tMMCA0CYC tMMCA0CMDD (min)tMMCA0CMDD (max) MMCA0DADD (max) MMCA0DADD (min)t t MMCA0CMHtMMCA0CMSt MMCA0DAHtMMCA0DASt tMMCA0MLtMMCA0MH

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3.3.10 MSPI Timing

3.3.10.1 MSPI Communication Speed Overview

Table 3.44 MSPI Communication Speed Overview (1/3) MSPIn pin name Port Max. Frequency MSPI0 SC P4_6 10 MHz SO P4_5 10 MHz SI P4_7 10 MHz SC P6_8 10 MHz SO P6_9 10 MHz SI P6_7 10 MHz SC P2_12 20 MHz SO P2_13 20 MHz SI P2_11 20 MHz SCKN / SCKP P2_14, P2_15 40 MHz SON / SOP P2_12, P2_13 40 MHz SIN / SIP P2_10, P2_11 40 MHz MSPI1 SC P2_2 10 MHz SO P5_2 10 MHz SI P2_1 10 MHz SC P6_8 10 MHz SO P6_7 10 MHz SI P6_9 10 MHz SC P10_3 20 MHz SO P10_2 20 MHz SI P10_4 20 MHz SCKN / SCKP P4_10, P4_9 40 MHz SON / SOP P4_8, P4_7 40 MHz SIN / SIP P4_6, P4_5 40 MHz MSPI2 SC P4_7 10 MHz SO P4_6 10 MHz SI P4_10 10 MHz SC P10_11 10 MHz SO P10_10 10 MHz SI P10_12 10 MHz SC P2_0 20 MHz (The selection of "Drive strength = 1" is available at equal or less than 10 MHz.) SO P2_5 20 MHz (The selection of "Drive strength = 1" is available at equal or less than 10 MHz.) SI P2_3 20 MHz

Page 117 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics MSPI3 SC P22_4 10 MHz (The selection of "Drive strength = 1" is available) SO P22_0 10 MHz (The selection of "Drive strength = 1" is available) SI P22_1 10 MHz SC P24_10 10 MHz SO P24_13 10 MHz SI P24_12 10 MHz SC P5_2 20 MHz SO P5_4 20 MHz SI P5_3 20 MHz MSPI4 SC P23_0 10 MHz SO P23_2 10 MHz SI P23_1 10 MHz SC P21_0 20 MHz SO P21_2 20 MHz SI P21_1 20 MHz MSPI5 SC P12_0 10 MHz SO P12_2 10 MHz SI P12_1 10 MHz SC P24_4 20 MHz SO P24_6 20 MHz SI P24_5 20 MHz MSPI6 SC P9_0 10 MHz SO P9_2 10 MHz SI P9_1 10 MHz SC P11_0 10 MHz SO P11_2 10 MHz SI P11_1 10 MHz MSPI7 SC P11_8 10 MHz SO P11_10 10 MHz SI P11_9 10 MHz SC P19_0 10 MHz SO P19_2 10 MHz SI P19_1 10 MHz MSPI8 SC P0_0 10 MHz SO P0_2 10 MHz SI P0_1 10 MHz SC P18_1 10 MHz SO P18_3 10 MHz SI P18_2 10 MHz Table 3.44 MSPI Communication Speed Overview (2/3) MSPIn pin name Port Max. Frequency

Page 118 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics MSPI9 SC P1_0 10 MHz SO P1_2 10 MHz SI P1_1 10 MHz SC P18_8 10 MHz SO P18_10 10 MHz SI P18_9 10 MHz Table 3.44 MSPI Communication Speed Overview (3/3) MSPIn pin name Port Max. Frequency

Page 119 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.3.10.2 MSPI Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition.
Buffer type = Sch1 Note 1. This item is programmable, the value can be set by MSPInPRCSm[1:0] and MSPInCDIVm[4:0]. Note 2. This item is programmable, the value can be set by MSPInSEUPm[11:0] and it must be set to 002 H or above. Note 3. This item is programmable, the value can be set by MSPInHOLDm. Note 4. The selection of "Drive strengt h = 1" is available on P2_0 and P22_4 only. Note 5. Use by “PCLK/2 ≥ MSPInSCK”. Note 6. When using the MSPI at master mode with the setting MSPInCFGm1.MSPInCPHAm = 0, set the period from CS active to the first edge of SCK to 1/2 or more of the communication rate by MSPInSEUPm. Table 3.45 MSPI Timing (Master mode : Communication Speed 10MHz) Item Symbol Condition MIN. TYP. MAX. Unit MSPI operation clock cycle TMSPInCLK 12.5 ns MSPInSCK cycle*1*5 TSCKCYC 100 ns MSPInSCK Low/High width*1 TSCKWID CL = 30 pF Drive strength = 3 0.5 × TSCKCYC – 9 ns CL = 50 pF Drive strength = 3 0.5 × T SCKCYC – 12 ns CL = 100 pF Drive strength = 3 0.5 × TSCKCYC – 23 ns CL = 30 pF Drive strength = 4 0.5 × T SCKCYC – 15.5 ns CL = 50 pF Drive strength = 2 0.5 × TSCKCYC – 10 ns CL = 100 pF Drive strength = 1 0.5 × TSCKCYC – 10 ns Chip select signal setup time*2*6 TMCSSU TMSPInCLK = 12.5 ns MSPInSEUPm [11:0] x T MSPInCLK - 15 ns Chip select signal hold time*3 TMCSHO TMSPInCLK = 12.5 ns MSPInHOLDm [11:0] x T MSPInCLK - 5 ns Receive data setup time (MSPInSAMP =0) TMSISU1 20 ns Receive data setup time (MSPInSAMP =1) TMSISU2 20 ns Receive data hold time (MSPInSAMP =0) T MSIHO 0n s Receive data hold time (MSPInSAMP =1) TMSIHO 0n s Transmit data delay time TMSODL 7n s Transmit data hold time TMSOHL (TSCKCYC / 2) – 5 ns

Page 120 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Note 1. This item is programmable, the value can be set by MSPInPRCSm[1:0] and MSPInCDIVm[4:0]. Note 2. This item is programmable, the value can be set by MSPInSEUPm[11:0] and it must be set to 002 H or above. Note 3. This item is programmable, the value can be set by MSPInHOLDm. Note 4. Use by “PCLK/2 ≥ MSPInSCK”. Note 5. When using the MSPI at master mode with the setting MSPInCFGm1.MSPInCPHAm = 0, set the period from CS active to the first edge of SCK to 1/2 or more of the communication rate by MSPInSEUPm. Note 1. This item is programmable, the value can be set by MSPInPRCSm[1:0] and MSPInCDIVm[4:0]. Note 2. This item is programmable, the value can be set by MSPInSEUPm[11:0] and it must be set to 002 H or above. Note 3. This item is programmable, the value can be set by MSPInHOLDm. Note 4. Use by “PCLK/2 ≥ MSPInSCK”. Note 5. When using the MSPI at master mode with the setting MSPInCFGm1.MSPInCPHAm = 0, set the period from CS active to the first edge of SCK to 1/2 or more of the communication rate by MSPInSEUPm. Table 3.46 MSPI Timing (Master mode : Communication Speed 20MHz) Item Symbol Condition MIN. TYP. MAX. Unit MSPI operation clock cycle TMSPInCLK 12.5 ns MSPInSCK cycle*1*4 TSCKCYC 50 ns MSPInSCK Low/High width*1 TSCKWID CL = 15pF@50Ω Drive strength = 3 0.5 × TSCKCYC – 6 ns Chip select signal setup time*2*5 TMCSSU TMSPInCLK = 12.5 ns MSPInSEUPm [11:0] x T MSPInCLK – ns Chip select signal hold time*3 TMCSHO TMSPInCLK = 12.5 ns MSPInHOLDm [11:0] x T MSPInCLK – 5 ns Receive data setup time (MSPInSAMP = 1) TMSISU2 20 ns Receive data hold time (MSPInSAMP = 1) T MSIHO 0n s Transmit data delay time TMSODL 7n s Transmit data hold time TMSOHL (TSCKCYC/2) – 5 ns Table 3.47 MSPI Timing (Master mode : Communication Speed 40MHz) Item Symbol Condition MIN. TYP. MAX. Unit MSPI operation clock cycle TMSPInCLK 12.5 ns MSPInSCK cycle*1*4 TSCKCYC 25 ns MSPInSCK Low/High width*1 TSCKWID CL = 15pF@LVDS 0.5 × T SCKCYC – 2.5 ns Chip select signal setup time*2*5 TMCSSU TMSPInCLK = 12.5 ns MSPInSEUPm [11:0] x T MSPInCLK – ns Chip select signal hold time*3 TMCSHO TMSPInCLK = 12.5 ns MSPInHOLDm [11:0] x T MSPInCLK – 5 ns Receive data setup time (MSPInSAMP = 1) T MSISU2 7n s Receive data hold time (MSPInSAMP = 1) T MSIHO 0n s Transmit data delay time TMSODL 5 ns Transmit data hold time TMSOHL (TSCKCYC/2) – 5 ns

Page 121 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Table 3.48 MSPI Timing (Slave mode : Communication Speed 10MHz) Item Symbol Condition MIN. TYP. MAX. Unit MSPI operation clock cycle TMSPInCLK 12.5 ns MSPInSCK cycle TSCKCYC 100 ns MSPInSCK Low/High width TSCKWID 0.5 × TSCKCYC – 23 ns Chip select signal setup time (MSPInCSIE = 1) TSCSSU 15 ns Chip select signal hold time (MSPInCSIE = 1) TSCSHO 10 ns Receive data setup time TSSISU 6n s Receive data hold time TSSIHO 5n s Transmit data delay time 1 TSSODL1 54 ns Transmit data delay time 2 (MSPInCSIE = 1) T SSODL2 40 ns Transmit data hold time TSSOHL (TSCKCYC/2) – 5 ns Transmit data release time (MSPInCSIE = 1) T SSOREL 40 ns Table 3.49 MSPI Timing (Slave mode : Communication Speed 20MHz) Item Symbol Condition MIN. TYP. MAX. Unit MSPI operation clock cycle TMSPInCLK 12.5 ns MSPInSCK cycle TSCKCYC 50 ns MSPInSCK Low/High width TSCKWID 0.5 × TSCKCYC – 6 ns Chip select signal setup time (MSPInCSIE = 1) T SCSSU 15 ns Chip select signal hold time (MSPInCSIE = 1) T SCSHO 10 ns Receive data setup time TSSISU 6n s Receive data hold time TSSIHO 5n s Transmit data delay time 1 TSSODL1 24 ns Transmit data delay time 2 (MSPInCSIE = 1) T SSODL2 40 ns Transmit data hold time TSSOHL (TSCKCYC/2) – 5 ns Transmit data release time (MSPInCSIE = 1) T SSOREL 40 ns

Page 124 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.3.11 SCI3 Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition.
Buffer type = Sch1 Note: tPCLK is the period of PCLK (CLK_HSB). Table 3.51 SCI3 Timing (Master Mode, Asynchronous) Item Symbol Condition MIN. TYP. MAX. Unit Transfer rate rSCI3AS 10 Mbps Table 3.52 SCI3 Timing (Master Mode, Synchronous) Item Symbol Condition MIN. TYP. MAX. Unit Output cycle time tSCI3Scyc 200 ns Output clock pulse width t SCI3SW 0.4 × tSCI3Scyc 0.6 × tSCI3Scyc ns Transmit data delay time t SCI3TXD –40 40 ns Receive data setup time t SCI3RXS 4 × tPCLK ns Receive data hold time tSCI3RXH 4 × tPCLK ns Figure 3.35 SCI Clock Input/Output Timing tSCI3SW SCI3nSCK tSCI3Scyc tSCI3SW tSCI3SR tSCI3SF Figure 3.36 SCI3 Input/Output Timing, Clock Synchronous Mode (in Master Mode) tSCI3TXD tSCI3RXS tSCI3RXH SCI3nSCK (output) SCI3nTXD SCI3nRXD

Page 125 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Note 1. This does not apply to transmission of Data 0 (the fi rst bit) which is transferred not in continuous transfer mode. Transmission of Data 0 (the first bit) which is transferred not in continuous transfer mode starts when TDRE becomes 0. Note: tPCLK is the period of PCLK (CLK_HSB).

3.3.12 RLIN3 Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition.
Drive strength = 4
Buffer type = Sch1 Note 1. The LIN extended baud rate is not part of the LIN standard specification. Table 3.53 SCI3 Timing (Slave Mode) Item Symbol Condition MIN. TYP . MAX. Unit Input cycle time tSCI3Scyc 200 ns Input clock pulse width t SCI3SW 0.4 × tSCI3Scyc 0.6 × tSCI3Scyc ns Transmit data delay time*1 tSCI3TXD 2 × tPCLK 50 + 4 × tPCLK ns Input clock rising time t SCI3SR 20 ns Input clock falling time t SCI3SF 20 ns Receive data setup time t SCI3RXS 4 × tPCLK ns Receive data hold time t SCI3RXH 4 × tPCLK ns Figure 3.37 SCI3 Input/Output Timing, Clock Synchronous Mode (in Slave Mode) tSCI3TXD (min) tSCI3TXD (max) tSCI3RXS tSCI3RXH SCI3nSCK (intput) SCI3nTXD SCI3nRXD Table 3.54 RLIN3 Timing Item Symbol Condition MIN. TYP. MAX. Unit RLIN3 transfer rate r RLlin LIN mode 20 kbps rRLline LIN extended baud rate*1 115.2 kbps rRLurt UART mode 8 Mbps

Page 126 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.3.13 RIIC Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition.
Buffer type = Sch1 Note 1. At the start condition, the first cl ock pulse is generated after the hold time. Note 2. The system requires a minimum of 300 ns hold time internally for the RIICnSDA signal (at VIH min. of RIICnSCL signal). In order to occupy the undefined area at the falling edge of RIICnSCL. Note 3. If the system does not extend the RIICnSCL signal low hold time (t Low), only the maximum data hold time (tHD: DAT) needs to be satisfied. Note 1. At the start condition, the first cl ock pulse is generated after the hold time. Note 2. The system requires a minimum of 300 ns hold time internally for the RIICnSDA signal (at VIH min. of RIICnSCL signal). In order to occupy the undefined area at the falling edge of RIICnSCL. Note 3. The fast mode I 2C bus can be used in normal mode I2C bus system. In this case, set the fast mode I2C bus so that it meets the following conditions. - If the system does not extend the RIICnSCL signal’s low state hold time: tSU: DAT ≥ 250 ns - If the system extends the RIICnSCL signal’s low state hold time: Transmit the following data bit to the RIICnSDA line prior to releasing the RIICnSCL line (1250 ns: Normal mode I2C bus specification). Note 4. The filtered width is specified by the frequency of IIC Φ and the value of RIICnMR3.NF[1:0]. Note 5. If the system does not extend the RIICnSCL signal low hold time (t Low), only the maximum data hold time (tHD: DAT) needs to be satisfied. Table 3.55 RIIC Timing (Normal Mode) Item Symbol Condition MIN. TYP . MAX. Unit RIICnSCL clock period fCLK 100 kHz Bus free time (between stop/start condition) tBUF 4.7 μs Hold time*1 tHD: STA 4.0 μs RIICnSCL clock low level width tLOW 4.7 μs RIICnSCL clock high level time tHIGH 4.0 μs Setup time for start/restart condition tSU: STA 4.7 μs Data hold time tHD: DAT CBUS compatible master 5.0 μs I2C mode 0*2 *3 μs Data setup time tSU: DAT 250 ns Stop condition setup time tSU: STO 4.0 μs Table 3.56 RIIC Timing (Fast Mode) Item Symbol Condition MIN. TYP . MAX. Unit RIICnSCL clock period fCLK 400 kHz Bus free time (between stop/start condition) tBUF 1.3 μs Hold time*1 tHD: STA 0.6 μs RIICnSCL clock low level width tLOW 1.3 μs RIICnSCL clock high level time tHIGH 0.6 μs Setup time for start/restart condition tSU: STA 0.6 μs Data hold time tHD: DAT I 2C mode 0*2 *5 μs Data setup time tSU: DAT 100*3 ns Stop condition setup time tSU: STO 0.6 μs Pulse width with spike suppressed by input filter t SP 0* 4 ns

Page 127 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Figure 3.38 RIIC Timing RIICnSCL P tSU: STA tHD: STA tLOW tHIGH tBUF RIICnSDA tSP tHD: DAT tSU: DAT S tSU: STOtHD: STA Sr P Note P: Stop condition S: Start condition Sr: Restart condition

Page 128 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.3.14 RS-CANFD Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition.
Buffer type = Sch1 Note 1. For the configuration of the transfer speed, see RH850/U2A-EVA Group User's Manual: Hardware Table 3.57 RS-CANFD Timing Item Symbol Condition MIN. TYP . MAX. Unit Transfer rate rCN1 Classical CAN mode 1 Mbps rCN2 CAN FD mode (nominal bit rate) 1 Mbps rCN3 CAN FD mode (data bit rate) 8 Mbps Internal delay time t DCIN tINPUT + tOUTPUT 50 ns Figure 3.39 RS-CANFD Timing Internal output delay time (tOUTPUT) Internal input delay time (tINPUT) CANnTX CANnRX CAN controller Section 23.5.1.3, Baud Rate.

Page 129 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.3.15 FlexRay Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition.
CL =25 pF
Buffer type = Sch1 Note 1. Base of this specification is “FlexRay El ectrical Physical Layer Specification V3.0.1, Oct-2010”

3.3.16 RSENT Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition.
Drive strength = 4
Buffer type = Sch1 Table 3.58 FlexRay Timing*1 Item Symbol Condition MIN. TYP . MAX. Unit Transfer rate rFLXA 10 Mbps Table 3.59 RSENT Timing Item Symbol Condition MIN. TYP. MAX. Unit Tick Time 1 90 µs

Page 130 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.3.17 Renesas High-speed Serial I/F Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition.
HSIF0_REFCLK: CL = 15 pF
Buffer type = Sch1
E0VCC = 5.0 ± 0.5 V or 3.3V ± 0.3 V Conditions:
See Section 3.3.1, AC Characteristic Measurement Condition.
HSIF0_REFCLK: CL = 15 pF
E0VCC = 5.0 ± 0.5 V or 3.3V ± 0.3 V
HSIF0_TXDP, HSIF0_TXDN: CL = 5.0 pF Note 1. Asynchronous Table 3.60 External Reference Clock Input/Output Characteristics Item Symbol Condition MIN. TYP . MAX. Unit External Reference Clock Input frequency f REFCKI 10 20 MHz External Reference Clock Input duty cycle DCREFCKI 35 65 % External Reference Clock output frequency f REFCKO 10 20 MHz External Reference Clock output duty cycle DCREFCKO 35 65 % Table 3.61 RHSIF Transmit Data Timing Item Symbol Condition MIN. TYP. MAX. Unit Transmit data cycle f TX Slow mode 5 M Baud Fast mode 320 M Baud Transmit data delay time (HSIF0_REFCLK input) tREFITXDD Slow mode 0 60 ns Fast mode*1 ns Transmit data delay time (HSIF0_REFCLK output) t REFOTXDD Slow mode RHSIFnREFCLK 20MHz –20 20 ns Slow mode RHSIFnREFCLK 10MHz 15 85 ns Fast mode* 1 ns

Page 132 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.3.18 CXPI Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition.
Drive strength = 4
Buffer type = Sch1 Note 1. tPCLK is period of CLK_HSB Note 2. “511 × tPCLK” means maximum surge noise filter time. For details, see RH850/U2A-EVA Group User's Manual: Hardware Section 30.4.1.6, CXP1nFIL — CXPI Input Filter Setting Register Table 3.63 CXPI Timing (CXPI-PWM Mode, Master node) Item Symbol Condition MIN. TYP. MAX. Unit CXPI transfer rate rCXPI 20 kbps CXPI cycle time Tbit 50 μs Required loop back delay time (from CXP1nTX to CXP1nRX) tpwm_loop 0.05 × Tbit μs Table 3.64 CXPI Timing (CXPI-PWM Mode, Slave node) Item Symbol Condition MIN. TYP. MAX. Unit CXPI transfer rate rCXPI 20 kbps CXPI cycle time Tbit 50 μs CXP1nTX output delay time (from CXP1nRX) ttx_0_pd 4 × tPCLK *1 511 × tPCLK + 4 × tPCLK + 0.1*1,*2 μs Required loop back delay time (from CXP1nTX to CXP1nRX) t pwm_loop 0.05 × Tbit μs Table 3.65 CXPI Timing (CXPI-NRZ Mode, Master or Slave node) Item Symbol Condition MIN. TYP . MAX. Unit CXPI transfer rate rCXPI 20 kbps CXPI cycle time Tbit 50 μs Required loop back delay time (from CXP1nTX to CXP1nRX) tnrz_loop 1 × Tbit 4 × Tbit μs

Page 134 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Figure 3.45 tnrz_loop Waveform in CXPI NRZ Mode CXP1nRX CXP1nTX Communication bus tnrz_loop Logic0 Logic1 Logic0 Logic1 Logic0 Logic1

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3.3.19 Ethernet Timing

3.3.19.1 MII Characteristics

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition.
CL = 15 pF
Buffer type = TTL Note 1. The duty cycle of ETNBnTXCLK and ET NBnRXCLK shall be between 35 to 65% (IEEE802.3). Table 3.66 Ethernet Timing – 10 Mbit/s MII Characteristics Item Symbol Condition MIN. TYP. MAX. Unit ETNBnTXCLK width tMTC 400 – 100 ppm 400 400 + 100 ppm ns ETNBnTXCLK high width tMTCH *1 140 200 260 ns ETNBnTXCLK low width tMTCL *1 140 200 260 ns ETNBnTXD [3:0] delay time tMTXD 02 5 n s ETNBnTXEN delay time tMTXE 02 5 n s ETNBnRXCLK width tMRC 400 – 100 ppm 400 400 + 100 ppm ns ETNBnRXCLK high width tMRCH *1 140 200 260 ns ETNBnRXCLK low width tMRCL *1 140 200 260 ns ETNBnRXD [3:0] setup time tMRXDS 10 ns ETNBnRXD [3:0] hold time tMRXDH 10 ns ETNBnRXDV, ETNBnRXER setup time t MRDES 10 ns ETNBnRXDV, ETNBnRXER hold time t MRDEH 10 ns ETNBnWOL delay time tMWOL 13 0 n s

Page 136 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition.
Cload = 15 pF
Drive strength = 2
Buff er type = TTL Note 1. The duty cycle of ETNBnTXCLK and ET NBnRXCLK shall be between 35 to 65% (IEEE802.3). Table 3.67 Ethernet Timing – 100 Mbit/s MII Characteristics Item Symbol Condition MIN. TYP. MAX. Unit ETNBnTXCLK width tMTC 40 – 100 ppm 40 40 + 100 ppm ns ETNBnTXCLK high width tMTCH *1 14 20 26 ns ETNBnTXCLK low width tMTCL *1 14 20 26 ns ETNBnTXD [3:0] delay time tMTXD 02 5 n s ETNBnTXEN delay time tMTXE 02 5 n s ETNBnRXCLK width tMRC 40 – 100 ppm 40 40 + 100 ppm ns ETNBnRXCLK high width tMRCH *1 14 20 26 ns ETNBnRXCLK low width tMRCL *1 14 20 26 ns ETNBnRXD [3:0] setup time tMRXDS 10 ns ETNBnRXD [3:0] hold time tMRXDH 10 ns ETNBnRXDV, ETNBnRXER setup time t MRDES 10 ns ETNBnRXDV, ETNBnRXER hold time t MRDEH 10 ns ETNBnWOL delay time tMWOL 13 0 n s Figure 3.46 Ethernet Timing – MII Transmitter tMTXE (min)tMTXE (max) tMTXD (max) ETNBnTXCLK ETNBnTXD[3:0] ETNBnTXEN tMTC tMTCH tMTCL tMTXD (min)

Page 138 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.3.19.2 RMII Characteristics

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition.
CL = 15 pF
Drive strength = 2
Buffer type = TTL Note 1. The duty cycle of ETNB0REF 50CK shall be between 35 to 65% (RMIITM specification). Table 3.68 Ethernet Timing – RMII Characteristics Item Symbol Condition MIN. TYP. MAX. Unit ETNB0REF50CK width tRMC 20 – 50 ppm 20 20 + 50 ppm ns ETNB0REF50CK high width t RMCH *1 71 3 n s ETNB0REF50CK low width t RMCL *1 71 3 n s ETNB0RXD [1:0], ETNB0CRS _DV and ETNB0RXER setup time tRMS 4n s ETNB0RXD [1:0], ETNB0CRS_DV and ETNB0RXER hold time t RMH 2n s ETNB0TXD [1:0], ETNB0TXEN output delay time tRMD 21 6 n s ETNB0WOL delay time tRMWOL 13 0 n s Figure 3.49 Ethernet Timing – RMII Transmitter tRMD (max) ETNB0REF50CK ETNB0TXD[1:0] ETNB0TXEN tRMC tRMCH tRMCL tRMD (min) Figure 3.50 Ethernet Timing – RMII Receiver tRMS tRMH tRMS tRMH ETNB0REF50CK ETNB0RXD[1:0] ETNB0CRS_DV ETNB0RXER tRMC tRMCH tRMCL

Page 139 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Figure 3.51 Ethernet Timing – RMII WOL tRMWOL (max) ETNB0REFCLK ETNB0WOL tRMWOL (min)

Page 140 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.3.19.3 SGMII Characteristics

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. Note 1. See the Figure 3.52, Differential output return loss for details of differential output return loss. Table 3.69 Ethernet Timing – SGMII REFCK Characteristics Item Symbol Condition MIN. TYP. MAX. Unit Clock input frequency tCIF 40 – 100ppm 40 + 100 ppm ns Clock input duty cycle t CIDC 45 55 % Clock input rising/falling time (20%-80%) t CIRFT 3n s Clock Input Total jitter (Dj+ 14* rms Random jitter) tCITJ 73*1 ps peak to peak Note 1. 12 kHz to 20 MHz rms jittrer = 3 ps. Table 3.70 Ethernet Timing – SGMII Tx buffer Characteristics Item Symbol Condition MIN. TYP. MAX. Unit Signaling speed tSS 1.25 – 100 ppm 1.25 + 100 ppm GBd Total output jitter (Dj+14*rms random jitter) t TOJ 300 ps peak to peak VOD rise/fall time (20% - 80%) t VRFT 60 250 ps Differential output return loss (min) DORL *1 dB Figure 3.52 Differential output return loss Loss dB Frequency f0 f1 Slope Parameter value Unit A0 -8 dB f0 50 MHz f1 0.625 GHz f2 1.25 GHz Slope 10 dB/dec

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3.3.19.4 Management Interface

Timing of management interface (ETNBnMDC and ETNBnMDIO) depends on software. It is necessary to adjust wait time according to AC specification of PHY . Table 3.71 Ethernet Timing – SGMII Rx buffer Characteristics Item Symbol Condition MIN. TYP. MAX. Unit Signaling speed tSS 1.25 – 100 ppm 1.25 + 100 ppm GBd Total input jitter tolerance* (Dj+14*rms random jitter) tTIJT 400 ps peak to peak setup/hold time*1, *3 tSHT 120 ps Note 1. Measured at 50% of the transition Note 2. Only supported by RH850/U2A Note 3. Only supported by RH850/U2A-EVA Table 3.72 Ethernet Timing – Characteristics Item Symbol Condition MIN. TYP. MAX. Unit SGMII power stabilization time t SPST 1.2 ms

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3.3.20 PSI5 Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition.
Drive strength = 4

3.3.21 PSI5-S Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. Table 3.73 PSI5 Timing Item Symbol Condition MIN. TYP. MAX. Unit Bit time 125 kbps (Low speed) 7.6 8.0 8.4 µs 189 kbps (High speed) 5.0 5.3 5.6 µs 250 kbps (PAS compatibility) 3.8 4.0 4.2 µs Gap time 125 kbps (Low speed) 8.4 µs 189 kbps (High speed) 5.6 µs 250 kbps (PAS compatibility) 2.0 µs Table 3.74 PSI5-S Timing Item Symbol Condition MIN. TYP . MAX. Unit PSI5-S transfer rate r PSI5S1 PSI5-S mode 5.33 Mbps rPSI5S2 UART mode 5.33 Mbps Output clock cycle t PSIScyc PSI5-S mode 37.5 ns Output clock pulse width t PSISCKW PSI5-S mode 0.3 x t PSIScyc 0.5 x tPSIScyc ns

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3.3.22 Timer Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. Note 1. S: Number of sampling times fs: The value given by the following formula fDNFCK: frequency of CLKA_TAUJ (for TAUJ2 and TAUJ3), CLK_HSB (others) result in an undefined signal condition (i.e. pulses might be filtered or not. This characteristic is not tested in production. Note 3. When CLK_LSIOSC is selected by CLKA_TAUJ regist er, at least one clock period of CLK_LSIOSC (4.6 µs) is required for activation of input signal for that domain. Any input pulses with less than 4.6 µs width may be rejected. Note 4. By-pass of filter is possible. For details, see RH850/U2A-EVA Group User's Manual: Hardware Table 3.75 Timer Input Timing Item Symbol Condition MIN. TYP. MAX. Unit TAUDnIm input high level width t WTDIH (S + 1) x 1/fs*1 ns TAUDnIm input low level width tWTDIL (S + 1) x 1/fs*1 ns TAUDnIm pulse rejection width*2 tWTDRJ (S – 1) x 1/fs*1 (S + 1) x 1/fs*1 ns TAUJnIm input high level width t WTJIH Analog noise filter 600 *3 ns Digital noise filter (S + 1) x 1/fs *1 ns TAUJnIm input low level width tWTJIL Analog noise filter 600 *3 ns Digital noise filter (S + 1) x 1/fs *1 ns TAUJnIm pulse rejection width*2 tWTJRJ Analog noise filter 100 600*3 ns Digital noise filter (S – 1) x 1/fs *1 (S + 1) x 1/fs*1 ns TAPAnESO input high level width*4 tWTPIH Analog noise filter 600 ns Digital noise filter (S + 1) x 1/fs *1 ns TAPAnESO input low level width*4 tWTPIL Analog noise filter 600 ns Digital noise filter (S + 1) x 1/fs *1 ns TAPAnESO pulse rejection width*2, *4 tWTPRJ Analog noise filter 100 600 ns Digital noise filter (S – 1) x 1/fs *1 (S + 1) x 1/fs*1 ns ENCAnTINm input high level width tWENIH (S + 1) x 1/fs*1 ns ENCAnTINm input low level width tWENIL (S + 1) x 1/fs*1 ns ENCAnTINm pulse rejection width*2 tWENRJ (S – 1) x 1/fs*1 (S + 1) x 1/fs*1 ns TSG3nPTSIm/ENCAnEx, TSG3nCLKI high level width tWTGIH (S + 1) x 1/fs*1 ns TSG3nPTSIm/ENCAnEx, TSG3nCLKI low level width tWTGIL (S + 1) x 1/fs*1 ns TSG3nPTSIm/ENCAnEx, TSG3nCLKI pulse rejection width*2 tWTGRJ (S – 1) x 1/fs*1 (S + 1) x 1/fs*1 ns fs fDNFCK Section 2.7.2.10, ANF/DNF Type F1.

Page 144 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Figure 3.53 Timer Input Timing tWTDRJ tWTDIH TAUDnIm TAUJnIm TAPAnESO ENCAnTINm TSG3nPTSIm/ENCAnEx, TSG3nCLKI tWTJRJ tWTPRJ tWENRJ tWTGRJ tWTJIH tWTPIH tWENIH tWTGIH tWTDIL tWTJIL tWTPIL tWENIL tWTGIL tWTDRJ tWTJRJ tWTPRJ tWENRJ tWTGRJ

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3.3.23 GTM Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. Note 1. Tsamp = 1/f CLK_UHSB Table 3.76 GTM Timing Item Symbol Condition MIN. TYP. MAX. Unit GTM input high level width tWGTIH 4 × Tsamp*1 ns GTM input low level width tWGTIL 4 × Tsamp*1 ns GTM output cycle time tCYGTO 4 × Tsamp*1 ns GTMECLKn output cycle tCYGTECLK 8 × Tsamp*1 ns GTMECLKn output high level width t WGTOH 4 × Tsamp*1 – 10 ns GTMECLKn output low level width t WGTOL 4 × Tsamp*1 – 10 ns Figure 3.54 GTM Timing GTMATnOm GTMnIm GTMECLKn tWGTIH tWGTIL tCYGTO tCYGTECLK tWGTOH tWGTOL

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3.3.24 Emergency shut-Off (ESO) Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. Table 3.77 ESO Timing Item Symbol Condition MIN. TYP. MAX. Unit GTMATnOx Hi-z delay time tDESO 50 ns Figure 3.55 ESO Timing ESOn (Input) GTMATnOx (Output) tDESO Hi-Z

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3.3.25 Debug Reset Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. Note 1. Input pulses shorter than the giv en min. value will be filtered out (resulting in no interrupt detected). Input pulses between min. and max. value result in an undefined interrupt signal condition (i.e. pulses might be filtered out or not). Table 3.78 Debug Reset Timing Item Symbol Condition MIN. TYP. MAX. Unit TRST input low level width tWTRL 600 ns TRST pulse rejection*1 tWTRRJ 100 600 ns AURORES1, AURORES2, AURORESPD input low level width tWARSL 600 ns AURORES1, AURORES2, AURORESPD pulse rejection width*1 tWARRJ 100 600 ns ERAMRESPD, ERAMRES2 input low level width tWERSL 600 ns ERAMRESPD, ERAMRES2 pulse rejection width*1 tWERRJ 100 600 ns Figure 3.56 Debug Reset Timing TRST tWTRL tWTRRJ tWARSL tWARRJ tWERSL tWERRJ AURORES1 AURORES2 AURORESPD ERAMRES2 ERAMRESPD

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3.3.26 Nexus Interface Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition.
Buffer type = TTL Table 3.79 Nexus Interface Timing Item Symbol Condition MIN. TYP. MAX. Unit TCK Cycle width tTCKW 50 ns TCK high level width tTCKWH 21 ns TCK low level width tTCKWL 21 ns TMS/TDI setup time tTISU 6n s TMS/TDI hold time tTIH 6n s TDO output delay time tTDOD 17 ns RDY delay time tRDYD 17 ns TCK/TRST/TMS/TDI input rising time t TIR 4n s TCK/TRST/TMS/TDI input falling time t TIF 4n s Figure 3.57 Nexus Interface Timing TCK tTCKW tTCKWH tTCKWL TDO RDY tTDOD TDI, TMS tTISU tTIH tRDYD tTIR tTIF

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3.3.27 LPD (4pin) Interface Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. Table 3.80 LPD (4pin) Interface Timing Item Symbol Condition MIN. TYP. MAX. Unit LPDCLK cycle time tLPDCKCYC 25 ns LPDCLK high/low level width tLPDCKW 4.5 ns LPDCLK input rising/falling time t LPDCKRF 8n s LPDI setup time tLPDSU 3n s LPDI hold time tLPDH 3n s LPDCLKO cycle time tLPDCKOCYC 25 ns LPDCLKO high/low level width t LPDCKOW tLPDCKW - 2 ns LPDCLK to LPDCLKO delay time t LPDCKOD 44 ns LPDO output delay tLPDOD 01 8 ns Figure 3.58 LPD (4pin) Interface Timing tLPDSU tLPDH LPDCLK LPDI tLPDCKCYC tLPDCKW tLPDCKW tLPDOD LPDCLKO LPDO tLPDCKOCYC tLPDCKOW tLPDCKOW tLPDCKRFtLPDCKRF tLPDCKOD

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3.3.28 AUDR Interface Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition.
CL = 10 pF
Drive strength = 2
Buffer type = SHMT1 (AUDRST), TTL ( Others) Table 3.81 AUDR Interface Timing Item Symbol Condition MIN. TYP. MAX. Unit AUDCK cycle time t AUCKcyc 20 ns AUDCK high level width t AUCKH 0.4 x tAUCKcyc ns AUDCK low level width t AUCKL 0.4 x tAUCKcyc ns AUDRST setup time t AURSTS 12 ns AUDRST pulse width t AURSTW 5 x tAUCKcyc ns AUDSYNC setup time t AUSYS 10 ns AUDSYNC hold time t AUSYH 5n s AUDATA input setup time t AUDTS 8n s AUDATA input hold time t AUDTH 5n s AUDATA output delay t AUDTD tAUCKcyc – 3.4 ns Figure 3.59 AUDR Interface Timing tAUCKH tAUCKcyc tAUCKL tAUDTHtAUDTS tAUSYHtAUDSYS tAURSTS tAURSTW tAURSTS tAUDTD AUDCK (Input) AUDATA3 to AUDATA0 (Input) AUDATA3 to AUDATA0 (Output) AUDSYNC (Input) AUDRST

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3.3.29 Aurora Interface Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. 3.3.29.1 Aurora Interface — 1.25 Gbps baud rate Note 1. At driver output. Note 2. Skew at transmitter output between the differential pair. Note 3. Skew at transmitter output bet ween lanes of a multi-lane channel. 3.3.29.2 Aurora Interface — 2.5 Gbps baud rate Note 1. At driver output. Note 2. Skew at transmitter output between the differential pair. Note 3. Skew at transmitter output bet ween lanes of a multi-lane channel. Table 3.82 Aurora Interface Operating Condition – 1.25Gbps baud rate Item Symbol Condition MIN. TYP. MAX. Unit Rise/Fall Time t AITRF *1 60 ps Deterministic jitter t AIDJ 0.17 UI Total jitter tAITJ 0.35 UI Output skew t AIOS *2 25 ps Multiple output skew t AIMOS *3 1000 ps Unit interval t AIUI 800 - 100 ppm 800 +100 ppm ps Table 3.83 Aurora Interface Operating Condition – 2.5Gbps baud rate Item Symbol Condition MIN. TYP. MAX. Unit Rise/Fall Time tAITRF *1 40 ps Deterministic jitter tAIDJ 0.17 UI Total jitter tAITJ 0.35 UI Output skew tAIOS *2 20 ps Multiple output skew tAIMOS *3 1000 ps Unit interval tAIUI 400 - 100 ppm 400 + 100 ppm ps

Page 152 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics 3.3.29.3 Aurora Interface — 3.125 Gbps baud rate Note 1. At driver output. Note 2. Skew at transmitter output between the differential pair. Note 3. Skew at transmitter output bet ween lanes of a multi-lane channel.

3.3.29.4 Aurora Interface — 5 Gbps baud rate

Note 1. At driver output. Note 2. Skew at transmitter output between the differential pair. Note 3. Skew at transmitter output bet ween lanes of a multi-lane channel. 3.3.29.5 Aurora Interface — 6.25 Gbps baud rate Note 1. At driver output. Note 2. Skew at transmitter output between the differential pair. Note 3. Skew at transmitter output bet ween lanes of a multi-lane channel. Table 3.84 Aurora Interface Operating Condition – 3.125Gbps baud rate Item Symbol Condition MIN. TYP. MAX. Unit Rise / Fall Time tAITRF *1 30 ps Deterministic jitter t AIDJ 0.17 UI Total jitter tAITJ 0.35 UI Output skew tAIOS *2 15 ps Multiple output skew t AIMOS *3 1000 ps Unit interval tAIUI 320 -100 ppm 320 + 100 ppm ps Table 3.85 Aurora Interface Operating Condition – 5Gbps baud rate Item Symbol Condition MIN. TYP. MAX. Unit Rise/Fall Time tAITRF *1 30 ps Deterministic jitter t AIDJ 0.25 UI Total jitter tAITJ 0.35 UI Output skew tAIOS *2 15 ps Multiple output skew t AIMOS *3 1000 ps Unit interval tAIUI 200 - 100 ppm 200 + 100 ppm ps Table 3.86 Aurora Interface Operating Condition – 6.25Gbps baud rate Item Symbol Condition MIN. TYP. MAX. Unit Rise / Fall Time tAITRF *1 30 ps Deterministic jitter t AIDJ 0.25 UI Total jitter tAITJ 0.35 UI Output skew tAIOS *2 15 ps Multiple output skew t AIMOS *3 1000 ps Unit interval tAIUI 160 - 100 ppm 160 +100 ppm ps

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3.3.29.6 Aurora Interface — Transmitter clock Timing

Note 1. Peak to peak. Note 2. Phase noise of CICREF[P/N] should be below the line of Figure 3.60. Table 3.87 Aurora Interface Transmitter clock timing Item Symbol Condition MIN. TYP. MAX. Unit Reference clock frequency fAICLK 1.25 Gbps baud rate 62.5 MHz

2.5 Gbps baud rate 125 MHz

3.125 Gbps baud rate 156.25 MHz

5 Gbps baud rate 125 MHz

6.25 Gbps baud rate 156.25 MHz Reference clock rise time t AICTR 200 400 ps Reference clock fall time t AICTF 200 400 ps Reference clock duty cycle 45 55 % Reference clock total jitter t AICTJ *1 40*2 ps Stability tAICSTAB 50 ppm Figure 3.60 Phase noise of CICREF[P/N] −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 1.E+03 1.E+04 Offset Frequency [Hz] Phase noise [dBc/Hz]

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3.3.30 Debug Resource (Aurora, ERAM) Specific Reset Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. Table 3.88 Debug Resource (Aurora, ERAM) Specific Reset Timing Item Symbol Condition MIN. TYP. MAX. Unit AURORES2 release timing delay t DART2R 0 400 ns AURORES2 inactive hold time tHART2R 2.4 μs AURORES2 setup time tSART2P 2.4 μs ERAMRES2 release timing delay t DERT2R 0 400 ns ERAMRES2 inactive hold time tHERT2R 2.4 μs ERAMRES2 assert setup time tSERT2P 2.4 μs AURORES1, AURORESPD release timing delay tDART2AVD 2.4 μs AURORES1, AURORESPD inactive hold time tSART2AVD 2.4 μs ERAMRESPD release timing delay t DERT2EVD 2.4 μs ERAMRESPD inactive hold time t SERT2EVD 2.4 μs Note: About the parameter tWRSL, refer to “RESET input level width” in Section 3.3.6.1, RESET Timing Figure 3.61 AURORES2 AC Timing tWRSL tDART2R tSART2P tHART2R RESET AURORES2 ISOVDD Note: About the parameter tWRSL, refer to “RESET input low level width” in Section 3.3.6.1, RESET Timing Figure 3.62 ERAMRES2 AC Timing tWRSL tDERT2R tSERT2P tHERT2R RESET ERAMRES2 ISOVDD

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3.3.31 Debug Event Interface Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. Note 1. When used as event trigger. Note 2. When used as break input. Note 3. t MCKW is the cycle of the clock (MCKO) obtained by dividing the CPU clock (CLK_CPU) and the value must be divided by 16 (default). For details, refer to the RH850/U2A-EVA Group User’s Manual: Emulation. Table 3.89 Debug Event Interface Timing Item Symbol Condition MIN. TYP . MAX. Unit EVTI input high level width t WEVIH *1 2 ×tMCKW *3 ns *2 2 ×tTCKW ns EVTI input low level width t WEVIL *1 2 ×tMCKW *3 ns *2 2 ×tTCKW ns EVTO output high level width t WEVOH tMCKW *3 ns EVTO output low level width t WEVOL tMCKW *3 ns MSYN input high level width t WMSNH 2 ×tMCKW *3 ns MSYN input low level width t WMSNL 2 ×tMCKW *3 ns Figure 3.65 EVTI Timing EVTI tWEVIL tWEVIH Figure 3.66 EVTO Timing EVTO tWEVOL tWEVOH Figure 3.67 MSYN Timing MSYN tWMSNL tWMSNH

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3.3.32 Debug Interface Mode Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. Table 3.90 Debug Interface Mode Timing Item Symbol Condition Min. Typ. Max. Unit TCK (JP0_2) input timing before TRST tDBGIFSWCK 10×tLPDCKW 10×tTCKW ns TDI (JP0_0) setup time tDBGIFSWS 10×tLPDCKW 10×tTCKW ns TDI (JP0_0) hold time tDBGIFSWH 2 μs Figure 3.68 Debug Interface Mode Timing TRST TCK (JP0_2) TDI (JP0_0) tDBGIFSWCK tDBGIFSWS tDBGIFSWH

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3.3.33 Debug Wake-up Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. Table 3.91 Debug wake-up timing Item Symbol Condition Min. Typ. Max. Unit INTDCUTDI setup time tIDCUS 1m s INTDCUTDI hold time tIDCUH 3m s Figure 3.69 Debug wake-up timing tIDCUS tIDCUH TRST TDI

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3.3.34 Flash Programming

3.3.34.1 Flash Programming Characteristics

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. Note 1. Input the external clock data is mo re than or equal to 8 clocks of CLK_HSB. Note 2. t FPcyc is a period of CLK_HSB. Table 3.92 Flash Programming transfer rate Item Symbol Condition MIN. TYP. MAX. Unit Flash Programming transfer rate r FP 2-wired UART mode 2.5 Mbps FPCK cycle time tKCYSF 3-wired Clock Sync mode 100 *1 ns FPCK high level width tKWHSF 3-wired Clock Sync mode t KCYSF/2 – 10 ns FPCK low level width tKWLSF 3-wired Clock Sync mode t KCYSF/2 – 10 ns FPDR setup time tSSISF 3-wired Clock Sync mode 2 × t FPcyc *2 ns FPDR hold time tHSISF 3-wired Clock Sync mode 2 × t FPcyc *2 ns FPDT output delay tDSOSF 3-wired Clock Sync mode 2 × t FPcyc *2 3 × tFPcyc *2 + 32 ns FPDT hold time tHSOSF 3-wired clock sync mode 2 × t FPcyc *2 ns Figure 3.70 Flash Programming transfer rate FPCK FPDT FPDR tKWLSF tKWHSF tKCYSF tHSOSF tDSOSF tHSISFtSSISF

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3.3.34.2 Serial Programming Setup Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. For FLMD0 pulses, see RH850/U2A-EVA Group User's Manual: Hardware Section 51.7.3, Selection of Flash Programming Interface. Table 3.93 Serial Programming Setup Timing Item Symbol Condition MIN. TYP . MAX. Unit FLMD0 pulse input start time t MD0IS 2m s FLMD0 pulse input end time t MD0IE 100 ms FLMD0 low/high level width t MD0PWL/ tMD0PWH 4 μs FLMD0 rise time tMD0R 20 ns FLMD0 fall time tMD0F 20 ns Figure 3.71 Flash Programming transfer rate NOTE tMD0IE tMD0IS tMD0PWL tMD0PWH tMD0F tMD0R (low level) FLMD1 RESET FLMD0

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3.4 A/D Converter Characteristics

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. Table 3.94 ADC Characteristics (1/2) Item Symbol Condition MIN. TYP. MAX. Unit Resolution RESn 12 12 bit Analog supply voltages AnVCC 3.0 5.5 V Reference voltages AnVREFH AnVCC–1.0 (Do not set to below 3.0 V) [For U2A- EVA, U2A16 and U2A8 Only] AnVCC V AnVCC [For U2A6 Only] Analog input voltage V IAN ADCJnIm (T&H not used) AnVSS AnVREFH V ADCJnIm (T&H used) 0.2 AnVREFH -0.2 V ADCJ0ImS (A0VREFH ≥ E2VCC) A0VSS E2VCC V ADCJ1ImS (A1VREFH ≥ E1VCC) A1VSS E1VCC V ADCJ2ImS (A2VREFH ≥ E0VCC) A2VSS E0VCC V Operation frequency f ADCLK CLKA_ADC 10*3 40 MHz CLK_ADC 20 40 MHz Conversion time tCONV tSPL + tSAR*4 1.0 μs Sampling time tSPL*4 0.45 μs T&H sampling time t THSMP In self-diagnosis 0.45 μs First conversion (including after self-diagnosis) 10 μs Other than above 0.45 μs T&H hold time tTHHOLD 10 μs Slope of analog input voltage tVSIAN T&H used –5 5 kV/s Total error TOE ADCJnIm (T&H not used) –4.0 4.0 LSB ADCJnIm (T&H used), 3.0 V ≤ AnVREFH < 4.5 V –8.0 8.0 LSB ADCJnIm (T&H used), 4.5 V ≤ AnVREFH < 5.5 V –6.0 6.0 LSB ADCJnImS –8.0 8.0 LSB Integral non-linearity error*1 INL ADCJnIm (T&H not used) –2.0 2.0 LSB ADCJnIm (T&H used) –3.0 3.0 LSB ADCJnImS –6.0 6.0 LSB Differential non-linearity error*1 DNL ADCJnIm (T&H not used) –1.0 2.0 LSB ADCJnIm (T&H used) –1.0 2.0 LSB ADCJnImS –1.0 4.0 LSB Offset error*1 (Zero scale error) OSE ADCJnIm (T&H not used) –3.5 3.5 LSB ADCJnIm (T&H used), 3.0 V ≤ AnVREFH < 4.5 V –7.5 7.5 LSB ADCJnIm (T&H used), 4.5 V ≤ AnVREFH < 5.5 V –5.5 5.5 LSB ADCJnImS –7.5 7.5 LSB

Page 162 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Note 1. Quantization error is not included. Note 2. Error of only voltage monitor. Note 3. Include oscillation accuracy of HS IntOSC. Note 4. For details of tSPL and tSAR, see RH850/U2A-EVA Group User's Manual: Hardware Section 43.4.24, Analog Input Sampling and Scan Group Processing Time. CAUTION An analog input pin can also be used as a digital general-purpose input or output pin. Changes in a digital input or output at the analog input pin during an AD conversion may reduce the precision of conversion. The coupling noise from the changes in digital inputs or outputs of pins near the analog input pin during an AD conversion may also reduce the precision of conversion. The power supply noise from the changes in digital outputs of pins of the same power supply as the analog input or the ADC that are performing AD conversion may also reduce the precision of conversion. Full-scale error*1 FSE ADCJnIm (T&H not used) –3.5 3.5 LSB ADCJnIm (T&H used), 3.0 V ≤ AnVREFH < 4.5 V –7.5 7.5 LSB ADCJnIm (T&H used), 4.5 V ≤ AnVREFH < 5.5 V –5.5 5.5 LSB ADCJnImS –7.5 7.5 LSB Pin self diagnosis for AnVCC/2 –60.0 60.0 LSB Other than above –40.0 40.0 LSB AD core self-diagnosis Function –8.0 8.0 LSB Secondary power supply voltage monitor absolute error for E0VCC, VCC –16 16 LSB for AWOVDD, ISOVDD –10 10 LSB Pull-up resistor for wiring break detection RPU ADCJnIm pins VIAN = AnVSS 10 34 k Ω VIAN = AnVCC/2 5 22 k Ω VIAN = AnVCC 3 16 k Ω ADCJnImS pins VIAN = AnVSS 10 34 k Ω VIAN = EnVCC/2 5 22 k Ω VIAN = EnVCC 3 16 k Ω Pull-down resistor for wiring break detection R PD ADCJnIm pins VIAN = AnVSS 1.5 10 k Ω VIAN = AnVCC/2 5 19 k Ω VIAN = AnVCC 10 34 k Ω ADCJnImS pins VIAN = AnVSS 1.5 10 k Ω VIAN = EnVCC/2 5 19 k Ω VIAN = EnVCC 10 34 k Ω Table 3.94 ADC Characteristics (2/2) Item Symbol Condition MIN. TYP. MAX. Unit

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3.4.1 Sampling Errors in the External Circuit of the A/D Converter

Sampling error is error to which “Errors (Sampling error 1) which depend on input leakage current of analog pin” and “Errors (Sampling error 2) which depend on conversion cycles with charge sharing” were added. The external circuits of the A/D pins which become the factor of sampling error (sampling error 1 and sampling error 2) are shown below. (a) Errors (Sampling error 1) which depend on input leakage current of analog pin The error depends on the input leakage current (ILeak) of analog pin and external resistance (Re), and occurs. The error which depends on the input leakage current is given by the formula of the following. (b) Errors (Sampling error 2) which depend on conversion cycles with charge sharing A formula for errors in sampled values due to the external circuit of the A/D converter is given below. These errors will depend on the input circuit and conversion cycle. The formula given below for the errors is simplified for the calculation of sampling error based on internal stray capacitance, amplifier offset, resistance of the signal source, and conversion cycle. This formula can also be used to calculate the effects of the signal source resistance and conversion cycle on these errors. The formula gives the error of analog input 2 as shown in the figure below when A/D conversion is performed in the order of analog input 1 then 2. Sampling error Sampling error 1 Sampling error 2+= Sampling error 1 (LSB) Re ILeak 4096 Vavrefh Figure 3.72 Errors (Sampling error 1) which Depend on Input Leakage Current of Analog Pin Sensor Re Input leakage current (ILeak) C AnVCC EnVCC MCU |Vvfaerr| × CIN2 Ce + CIN2Sampling error 2 (LSB) = [( + )× + ( × C1 × V3 × Re )] ×|V2 - V1| × CIN1 Ce + CIN1 4096 Vavrefh 1 - e (-T1)/(Re×Ce)

Page 164 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Table 3.95 Definition of the symbols for the Sampling Error Formula Item Symbol Condition Reference Unit Common capacitance of the final stage of channel multiplexer CIN1 ADCJ0Im 1.5 pF ADCJ0ImS 5.2 pF ADCJ1Im 1.5 pF ADCJ1ImS 6.6 pF ADCJ2Im 1.5 pF ADCJ2ImS 5.2 pF Common capacitance of the final stage of the amplifier and T&H control circuit CIN2 ADCJ0Im, ADCJ0ImS 9.1 pF ADCJ1Im, ADCJ1ImS 9.1 pF ADCJ2Im, ADCJ2ImS 8.0 pF External capacitor on analog input pin Ce Depends on customer's environment µF Signal source impedance Re kΩ Conversions cycle of analog Input pins T1 ms AnVREFH voltage Vavrefh V Potential difference between V1 and V2 V2-V1 V Offset voltage of the amplifier and T&H control circuit Vvfaerr 50 mV Parasitic capacitance in the channel multiplexer C1 ADCJnIm 2 pF ADCJnImS 4 |AnVCC voltage / 2.5 - measured pin voltage (V2)| V3 Depends on customer's environment V Figure 3.73 Schematic for Sampling Error 2 Formula Values for conversion error calculated by using this formula do not include error (absolute error, etc.) specified in the A/D converter characteristics. This formula is a desktop formula and is theoretical. When the signal source has an extremely high resistance or when the conversion cycle is too short, calculated and measured values may differ. Actual error depends on the external capacitor, external resistor, capacitance and resistance of board wiring, so evaluate and verify the error on the user board is no greater than the value produced by this formula (Condit ion of this formula is “Re < 1.5 MΩ and T1 ≥ 10 μs”, or “1.5 MΩ ≤ Re ≤ 2 MΩ and T1 ≥ 512 μs”). Analog input 1 Re V1 PKG Pin PKG Pin Analog input 2 Ce Channel multiplexer CIN2ADCCIN1 Amplifier and T&H control circuit

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3.5 Code Flash Characteristics

Note 1. f CLKFC is the frequency of CLK_LSB. Note 2. The number of rewrites is the number of erasures for each block. When the number of rewrites is “n”, the device can be erased “n” times for each block. For example, when a block of 64 KB is erased after 512 bytes of writing have been performed for different addresses 128 times, the number of rewrites is counted as 1. However, multiple writing to the same address is not possible with 1 erasure (overwriting prohibited). Note 3. Retention period under average Ta = 85°C. This is the period starting on completion of a successful erasure of the code flash memory. Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition.
Only the processing time of the hardware. The overhead required by the software is not includ ed. Note 1. When erase counter function is used, add the erase counter update time. For details, see Table 3.101 and Table 3.102. The code flash memory is shipped in the erased state. If the code flash memory is read where it has not been written after erasure (no write condition), an ECC error is generated, resul ting in the occurrence of an exception. Table 3.96 Code Flash Basic Characteristics Item Symbol Condition MIN. TYP. MAX. Unit Operation frequency f CLKFC *1 84 0 MHz Number of rewrites*2 CWRT Data retention of 20 years *3 1000 times Table 3.97 Code Flash Programming Characteristics Item Symbol Block size Condition 8MHz ≤ fCLKFC <

20 MHz

20MHz ≤ fCLKFC <

40 MHz fCLKFC = 40 MHz

8 KB CWRT < 100 times 5.0 17 4.0 15 3.8 14 ms CWRT ≥ 100 times 6.0 20 4.8 18 4.6 17 ms Erasure time*1 16 KB CWRT < 100 times 26 108 24 98 24 96 ms CWRT ≥ 100 times 32 130 29 118 29 116 ms

64 KB CWRT < 100 times 88 374 81 340 78 330 ms

CWRT ≥ 100 times 106 449 98 408 94 396 ms

Page 166 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Table 3.98 Code Flash Programming/Erasure suspend latency Characteristics Item Symbol Block size Condition 8MHz ≤ fCLKFC < 20MHz ≤ fCLKFC < Programming Suspend Latency tSPD 160 120 120 μs Erasure Suspend Latency tSESD1 Priority on suspension The 1st suspend for the same erasing pulse 150 120 120 μs tSESD2 Priority on suspension The 2nd suspend for the same erasing pulse 1.7 1.7 1.7 ms tSEED Priority on erasure 1.7 1.7 1.7 ms Table 3.99 Code Flash Programming/Erasure resume latency Characteristics Item Symbol Block size Condition 8MHz ≤ fCLKFC < 20MHz ≤ fCLKFC < Programming Resume Latency tRPT 80 50 50 μs Erasure Resume Latency tREST1 Priority on suspension Resume after the 1st suspend for the same erasing pulse 1.7 1.7 1.7 ms tREST2 Priority on suspension Resume after the 2nd suspend for the same erasing pulse 110 80 80 μs tREET Priority on erasure 110 80 80 μs Table 3.100 Code Flash Forced Stop command latency Item Symbol Block size Condition 8MHz ≤ fCLKFC < 20MHz ≤ fCLKFC < Forced Stop command Latency tFD 28 20 20 μs Table 3.101 Erase Counter update time Characteristics [For U2A-EVA] Item Symbol Block size Condition 8MHz ≤ fCLKFC < 20MHz ≤ fCLKFC < Table 3.102 Erase Counter update time Characteristics [For U2A16/U2A8/U2A6] Item Symbol Block size Condition 8MHz ≤ fCLKFC < 20MHz ≤ fCLKFC <

Page 167 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.6 Data Flash Characteristics

Note 1. f CLKFD is the frequency of CLK_LSB. Note 2. The number of rewrites is the number of erasures for each block. When the number of rewrites is “n”, the device can be erased “n” times for each block. For example, when a block of 4096 bytes is erased after 4 bytes of writing have been performed for different addresses 1024 times, the number of rewrites is counted as 1. However, multiple writing to the same address is not possible with 1 erasure (overwriting prohibited). Note 3. Retention period under average Ta = 85°C. This is the period starting on completion of a successful erasure of the data flash memory. Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition.
Only the processing time of the hardware. The overhead required by the software is not included. Note 1. Extended Data Area Only The data flash memory is shipped in the erased state. If the data flash memory is read where it has not been written after erasure (no write condition), an ECC error is generated , resulting in the occurrence of an exception. Table 3.103 Data Flash Basic Characteristics Item Symbol Condition MIN. TYP. MAX. Unit Operation frequency f CLKFD *1 84 0 MHz Number of rewrites*2 DWRT Data retention 20 years *3 125k Times Data retention 3 years*3 250k Times Table 3.104 Data Flash Programming Characteristics Item Symbol Block size Condition 8MHz ≤ fCLKFD <

20MHz ≤ fCLKFD <

40 MHz fCLKFD = 40 MHz

Erasure time 2 KB *1 11.1 105 9.9 95 9.6 92 ms 4 KB 19.2 179 17 160 16.4 155 ms Blank check command time 4 B 5.5 2.3 1.3 μs 4 KB 1.8 0.8 0.5 ms Property Erasure time 2 KB 11.1 105 9.9 95 9.6 92 ms

Page 168 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics Table 3.105 Data Flash Programming/Erasure suspend latency Characteristics Item Symbol Block size Condition 8MHz ≤ fCLKFD < 20MHz ≤ fCLKFD < Programming Suspend Latency*1 tSPD 160 120 120 μs Erasure Suspend Latency*1 tSESD1 Priority on suspension The 1st suspend for the same erasing pulse 150 120 120 μs tSESD2 Priority on suspension The 2nd suspend for the same erasing pulse 300 300 300 μs tSEED Priority on erasure 300 300 300 μs Note 1. Data Area and Extended Data Area Only Table 3.106 Data Flash Programming/Erasure resume latency Characteristics Item Symbol Block size Condition 8MHz ≤ fCLKFD < 20MHz ≤ fCLKFD < Programming Resume Latency*1 tRPT 80 50 50 μs Erasure Resume Latency*1 tREST1 Priority on suspension Resume after the 1st suspend for the same erasing pulse 300 300 300 μs tREST2 Priority on suspension Resume after the 2nd suspend for the same erasing pulse 100 70 70 μs tREET Priority on erasure 100 70 70 μs Note 1. Data Area and Extended Data Area Only Table 3.107 Forced Stop command latency Item Symbol Block size Condition 8MHz ≤ fCLKFD < 20MHz ≤ fCLKFD < Forced Stop command Latency tFD 28 20 20 μs

Page 169 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.7 Temperature Sensor Characteristics

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition. Note 1. The temperature borders need to be set keeping t he temperature range (Tj(min) to Tj(max)) including the temperature sensor accuracy. Note 2. It does not include accuracy of measuring equipment. Note 3. Temperature sensor cannot detect local heat generation inside the chip. Table 3.108 Temperature Sensor Characteristics*1*2*3 Item Symbol Condition MIN. TYP . MAX. Unit Temperature accuracy A CCTS1 – 40 °C ≤ Tj ≤ + 140 °C –4 4 °C ACCTS2 Tj > 140 °C –2 2 °C Temperature update period t TSUP 10 ms Operation stabilization waiting time tTSSB 200 μs

Page 170 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.8 Thermal Characteristics

3.8.1 Thermal Characteristics Parameter

Note 1. The thermal characterization parameters depends on the usage environment. Note 2. Ψjmb shows thermal characterization parameter from junction to board surface (center of the PKG on layer-1; Tmb). Ψjmb = (Tj-Tmb)/Pd (Pd: power consumption of the chip) Table 3.109 Thermal Characteristics*1 Parameter Estimated value Unit Remark U2A-EVAU2A16 U2A8 U2A6 BGA516 BGA516 BGA373 BGA292 BGA373 BGA292 BGA292 QFP176 BGA156 QFP144 compliant (4 layers) compliant (4 layers) compliant (4 layers) compliant (4 layers) compliant (4 layers) Ψjmb* compliant (4 layers) compliant (4 layers) (4 layers) (4 layers) (4 layers) 4LΨjmb* (4 layers) (4 layers) (4 layers)

Page 171 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.8.2 Assumed Board

Table 3.110 JESD51-9 Compliant Board (4 layers) Board Size (mm) Area (mm2)X Y Board Size 101.5 114.5 11621.75 Remaining copper rate Conductor thickness 50 – 95 – 95 – 50% 70 – 35 – 35 – 70 μm Table 3.111 L board (4 layers) Board Size (mm) Area (mm2)X Y Board Size 90 160 14400 Remaining copper rate Conductor thickness 30 – 80 – 80 – 30% 35 – 35 – 35 – 35 μm

Page 172 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 3 Electrical Characteristics

3.9 BSCAN Timing

Conditions:

See Section 3.3.1, AC Characteristic Measurement Condition.
Buffer type = TTL Table 3.112 BSCAN Timing Item Symbol Condition MIN. TYP . MAX. Unit TCK cycle width tDCKW 100 ns TDI setup time tSDI 12 ns TDI hold time tHDI 3n s TMS setup time tSMS 12 ns TMS hold time tHMS 3n s TDO delay time tDDO 03 0 ns Figure 3.74 BSCAN Timing TCK (in) TDI (in) TMS (in) TDO (out) tDCKW tSDI tSMS tDDO tHMS tHDI

Page 173 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 4 Package Section 4 Package

4.1 Package Outline

4.1.1 FPBGA (292pin) Package Drawing

Note: INDEX AREA is on the corner near a ball A1 (Top View side). Figure 4.1 FPBGA (292pin) outline MASS (Typ) [g] 0.9 Unit: mm Previous CodeRENESAS Code PRBG0292GC-A T292F1-80-GNP P-FBGA292-17x17-0.80 D E A e b x y y ZD ZE v w SD SE 0.30 0.50 Min Nom Dimension in MillimetersReference Symbol Max 17.00 17.00 0.35 0.80 0.55 0.90 0.90 0.40 0.40 1.90 0.40 0.60 0.12 0.10 0.20 0.15 0.20 S INDEX AREA y S Sy Sφ b φ xA BM SwA SwB Z A B E D ZD E e A A 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 B D F H K M P T V Y L N R U W A C E G J SE SD v4x

Page 174 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 4 Package

4.1.2 FPBGA (516pin (RENESAS Code = PRBG0516GC-A)) Package Drawing

Note: INDEX AREA is on the corner near a ball A1 (Top View side). Figure 4.2 FPBGA (516pin (RENESAS Code = PRBG0516GC-A)) outline Reference Symbol Dimension in Millimeters Min. Nom. Max. D 24.90 25.00 25.10 E 24.90 25.00 25.10 A 2.00 A1 0.29 0.34 0.39 e 0.80 b 0.50 0.55 0.60 x1 0.20 x2 0.08 y 0.15 y1 0.20 n 516 ZD 0.90 ZE 0.90 P-FBGA516-25x25-0.80 PRBG0516GC-A 2.00

Page 175 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 4 Package

4.1.3 FPBGA (516pin (RENESAS Code = PRBG0516GD-A)) Package Drawing

Note: INDEX AREA is on the corner near a ball A1 (Top View side). Figure 4.3 FPBGA (516pin (RENESAS Code = PRBG0516GD-A)) outline Reference Symbol Dimension in Millimeters Min. Nom. Max. D 24.90 25.00 25.10 E 24.90 25.00 25.10 A 2.00 A1 0.29 0.34 0.39 e 0.80 b 0.50 0.55 0.60 x1 0.20 x2 0.08 y 0.15 y1 0.20 n 516 ZD 0.90 ZE 0.90 P-FBGA516-25x25-0.80 PRBG0516GD-A 2.20

Page 176 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 4 Package

4.1.4 FPBGA (373pin) Package Drawing

Note: INDEX AREA is on the corner near a ball A1 (Top View side). Figure 4.4 FPBGA (373pin) outline E D INDEX AREA A B φx1 S A B φx2 S n × φb A y1 S S y CZ e (ZE) (ZD) Reference Symbol Dimension in Millimeters Min. Nom. Max. D 20.90 21.00 21.10 E 20.90 21.00 21.10 A ʵʵ 2.00 A1 0.30 0.35 0.40 e ʵ 0.80 ʵ b0 . 4 9 0 . 5 4 0 . 5 9 x1 ʵʵ 0.20 x2 ʵʵ 0.08 y ʵʵ 0.10 y1 ʵʵ 0.20 ZD ʵ 0.90 ʵ ZE ʵ 0.90 ʵ n ʵ 373 ʵ P-FBGA373-21x21-0.80 PRBG0373GB-A 1.4 AE AC AA W U R N L J G E C A AD AB Y V T P M K H F D B

Page 177 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 4 Package

4.1.5 LFPBGA (156pin) Package Drawing

Note: INDEX AREA is on the corner near a ball A1 (Top View side). Figure 4.5 LFPBGA (156pin) outline A A1y CZ S e (ZD) n × φb (ZE) φx1 S A B φx2 S E D AINDEX AREA B y1 S Reference Symbol Dimension in Millimeters Min. Nom. Max. D 9.92 10.00 10.08 E 9.92 10.00 10.08 A ʵʵ 1.70 A1 0.21 0.26 0.31 e ʵ 0.65 ʵ b 0.40 0.45 0.50 x1 ʵʵ 0.15 x2 ʵʵ 0.08 y ʵʵ 0.10 y1 ʵʵ 0.20 n ʵ 156 ʵ ZD ʵ 0.775 ʵ ZE ʵ 0.775 ʵ P-LFBGA156-10x10-0.65 PLBG0156JC-A 0.30

Page 178 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 4 Package

4.1.6 HLQFP (144pin) Package Drawing

Figure 4.6 HLQFP (144pin) outline ʵʵ ʵ ʵ ʵ ʵ ʵ ʵ ʵ ʵ ʵ ʵ ʵʵ ʵʵ

Page 179 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Section 4 Package

4.1.7 HLQFP (176pin) Package Drawing

Figure 4.7 HLQFP (176pin) outline 4 41 89132 133 176 89132 133 176 4 41 0.25 b c B P-HLFQFP176-24x24-0.50 PLQP0176KH-B 1.97 ʵʵ ʵ ʵ ʵ ʵ ʵ ʵ ʵ ʵ ʵ ʵ ʵʵ ʵʵ

Page 180 of 182R01DS0494ED0100 Rev.1.00 June 16, 2025 RH850/U2A Datasheet

Revision History

Rev. Date

Description

1.00 2025.06.16 - First Edition

General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products The following usage notes are applicable to all Microprocessing un it and Microcontroller unit products from Renesas. For detail ed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-off state as described in your product documentation. 4. Handling of unused pins Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to power supply or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 5. Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.). 6. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 7. Power ON/OFF sequence In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device.

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Renesas microcontroller Rev.1.00 June 16, 2025

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Renesas microcontroller Rev.1.00 June 16, 2025

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