TS321

TS321 Low-Power Single Operational Amplifier datasheet (Rev. D)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SLOS489,D]
• PDF pages: 25

Technical content

3 4IN+ IN– VCC– 3 6 4 5 OUT VCC+IN– IN+ VCC– NC NCNC Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TS321 SLOS489D –DECEMBER 2005–REVISED MAY 2018 TS321Low-PowerSingleOperationalAmplifier

1 Features

1• Wide Power-Supply Range – Single Supply from 3 V to 30 V – Dual Supply from ±1.5 V to ±15 V

• Large Output Voltage Swing from 0 V to 3.5 V (Minimum) (VCC = 5 V)
• Low Supply Current at 500 μA (Typical)
• Low Input Bias Current at 20 nA (Typical)
• Stable With High Capacitive Loads

2 Applications

• Desktop PCs
• HVAC: Heating, Ventilating, and Air Conditioning
• Portable Media Players
• Refrigerators
• Washing Machines: High-End and Low-End

3 Description

The TS321 is a bipolar operational amplifier for cost- sensitive applications in which space savings are important. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TS321 SOIC (8) 4.90 mm × 3.90 mm SOT-23 (5) 2.90 mm × 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet.

SLOS489D –DECEMBER 2005–REVISED MAY 2018 www.ti.com Product Folder Links: TS321 Submit Documentation Feedback Copyright © 2005–2018, Texas Instruments Incorporated Table of Contents

4 Revision History

Changes from Revision C (April 2015) to Revision D Page Changes from Revision B (December 2013) to Revision C Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device

3 4IN+ IN– VCC– 3 6 4 5 OUT VCC+IN– IN+ VCC– NC NCNC TS321 www.ti.com SLOS489D –DECEMBER 2005–REVISED MAY 2018 Product Folder Links: TS321 Submit Documentation FeedbackCopyright © 2005–2018, Texas Instruments Incorporated

5 Pin Configuration and Functions

(Top View) NC - no internal connection 5-Pin SOT-23 (Top View) Pin Functions PIN I/O DESCRIPTION NAME SOIC SOT-23 IN– 2 4 I Negative input IN+ 3 3 I Positive input NC — — Do not connect5 OUT 6 1 O Output VCC– 4 2 — Negative supply VCC+ 7 5 — Positive supply

SLOS489D –DECEMBER 2005–REVISED MAY 2018 www.ti.com Product Folder Links: TS321 Submit Documentation Feedback Copyright © 2005–2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Differential voltages are at IN+ with respect to IN–. (3) Input voltages are at IN with respect to VCC–.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage, VCC Single supply 32 V Dual supplies ±16 Differential input voltage(2),VID ±32 V Input voltage range (3), VI –0.3 32 V Input current, IIK 50 mA Duration of output short circuit to ground, tshort Unlimited Operating virtual junction temperature, TJ 150 °C Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) ±1500

6.3 Recommended Operating Conditions

V Dual supply ±1.5 ±15 TA Operating free-air temperature –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) Maximum power dissipation is a function of TJ(max), qJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = [TJ(max) – TA] / qJA. Selecting the maximum of 150°C can effect reliability. (3) The package thermal impedance is calculated in accordance with JESD 51-7.

6.4 Thermal Information: TS321

THERMAL METRIC(1) (2)(3) TS321 UNITD (SOIC) DBV (SOT-23)

5 PINS 5 PINS

RθJA Junction-to-ambient thermal resistance 97 206 °C/W

www.ti.com SLOS489D –DECEMBER 2005–REVISED MAY 2018 Product Folder Links: TS321 Submit Documentation FeedbackCopyright © 2005–2018, Texas Instruments Incorporated (1) The direction of the input current is out of the device. This current essentially is constant, independent of the state of the output, so no loading change exists on the input lines. (2) The input common-mode voltage of either input signal should not be allowed to go negative by more than 0.3 V. The upper end of the common-mode voltage range is VCC+ – 1.5 V, but either or both inputs can go to 32 V without damage.

6.5 Electrical Characteristics

VCC+ = 5 V, VCC– = GND, VO = 1.4 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIO Input offset voltage RS = 0, 5 V < VCC+ < 30 V 0 < VIC < (VCC+ – 1.5 V) TA = 25°C 0.5 4 mV TA = Full range 5 IIO Input offset current TA = 25°C 2 30 nA TA = Full range 50 IIB Input bias current(1) TA = 25°C 20 150 nA TA = Full range 200 AVD Large-signal differential voltage amplification VCC = 15 V, RL = 2 kΩ VO = 1.4 V to 11.4 V TA = 25°C 50 100 V/mV TA = Full range 25 VICR Common-mode input voltage(2) VCC = 30 V TA = 25°C 0 VCC+ – 1.5 V TA = Full range 0 VCC+ – 2 VOH High-level output voltage VCC = 30 V RL = 2 kΩ TA = 25°C 26 27 V TA = Full range 25.5 VCC = 30 V RL = 10 kΩ TA = 25°C 27 28 TA = Full range 26.5 VCC = 5 V RL = 2 kΩ TA = 25°C 3.5 TA = Full range 3 VOL Low-level output voltage RL = 10 kΩ TA = 25°C 5 15 mV TA = Full range 20 GBP Gain bandwidth product VCC = 30 V, VI = 10 mV, RL = 2 kΩ f = 100 kHz, CL = 100 pF TA = 25°C

0.8 MHz

VCC = 15 V, VI = 0.5 V to 3 V, RL = 2 kΩ, CL = 100 pF, unity gain, TA = 25°C

0.4 V/µs

φm Phase margin TA = 25°C 60 ° CMRR Common-mode rejection ratio RS ≤ 10 kΩ TA = 25°C 65 85 dB ISOURCE Output source current VCC = 15 V, VO = 2 V, VID = 1 V TA = 25°C 20 40 mA ISINK Output sink current VCC = 15 V, VID = 1 V VO = 2 V TA = 25°C 10 20 mA VCC = 15 V, VID = 1 V VO = 0.2 V TA = 25°C 12 50 µA IO Short-circuit to GND VCC = 15 V, TA = 25°C 40 60 mA SVR Supply-voltage rejection ratio VCC = 5 V to 30 V, TA = 25°C 65 110 dB ICC Total supply current VCC = 5 V TA = 25°C, no load 500 800 µA VCC = 30 V TA = 25°C, no load 600 900 VCC = 5 V TA = full range, no load 600 900 VCC = 30 V TA = full range, no load 1000 THD Total harmonic distortion VCC = 30 V, VO = 2 Vpp, AV = 20 dB RL = 2 k, f = 1 kHz, CL = 100 pF, TA = 25°C 0.015%

SLOS489D –DECEMBER 2005–REVISED MAY 2018 www.ti.com Product Folder Links: TS321 Submit Documentation Feedback Copyright © 2005–2018, Texas Instruments Incorporated Electrical Characteristics (continued) VCC+ = 5 V, VCC– = GND, VO = 1.4 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT eN Equivalent input noise voltage VCC = 30 V, f = 1 kHz, RS = 100 Ω TA = 25°C 50

(1) Short circuits from outputs to VCC can cause excessive heating and eventual destruction.

6.6 Typical Characteristics

Figure 1. Input Current vs Temperature Figure 2. Supply Current vs Temperature Figure 3. Output Sinking Characteristics Figure 4. Output Sourcing Characteristics Figure 5. Short-Circuit Current to Supply (1) Figure 6. Short-Circuit Current to Ground

IN– IN+ OUT TS321 SLOS489D –DECEMBER 2005–REVISED MAY 2018 www.ti.com Product Folder Links: TS321 Submit Documentation Feedback Copyright © 2005–2018, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The TS321 is a single-channel operational amplifier. The device can handle a single supply between 3 V and 30 V or a dual-supply between ±1.5 V and ±15 V. Available in the small SOT-23 package, the TS321 is great for saving space in any application.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Operating Voltage

The TS321 can be powered from a single supply between 3 V and 30 V or a dual-supply between ±1.5 V and ±15 V.

7.3.2 Gain Bandwidth Product

Gain bandwidth product is found by multiplying a measured bandwidth of the amplifier by the gain at which that bandwidth was measured. The TS321 has a gain bandwidth of 0.8 MHz.

7.3.3 Slew Rate

The slew rate is the rate at which an operational amplifier can change the output when there is a change on the input. The TS321 has a 0.4-V/μs slew rate.

7.3.4 Input Common-Mode Range

The valid common-mode range is from device ground pin to VCC – 1.5 V (VCC – 2 V across temperature).

7.3.5 Stability With High Capacitive Loads

Figure 7. Small-Signal Response

7.4 Device Functional Modes

amplifier or dual-supply amplifier depending on the application.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

powered before VCC for flexibility in multiple supply circuits.

8.2 Typical Application

amplifier makes negative voltages positive. Figure 8. Typical Application Schematic

8.2.1 Design Requirements

sufficient to accommodate this application.

8.2.2 Detailed Design Procedure

8.2.3 Application Curve

Figure 9. Input and Output Voltages of the Inverting Amplifier

9 Power Supply Recommendations

The TS321 is specified to operate between 3 V and 30 V or a dual supply between ±1.5 V and ±15 V.

10 Layout

10.1 Layout Guidelines

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, see SLOA089.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting input minimizes parasitic capacitance, as shown in Layout Example.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.

10.2 Layout Example

Figure 10. Operational Amplifier Schematic for Noninverting Configuration

Figure 11. Operational Amplifier Board Layout for Noninverting Configuration

SLOS489D –DECEMBER 2005–REVISED MAY 2018 www.ti.com Product Folder Links: TS321 Submit Documentation Feedback Copyright © 2005–2018, Texas Instruments Incorporated

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For more information, see the following:

• Simplifying Stability Checks
• Circuit Board Layout Techniques

11.2 Trademarks

All trademarks are the property of their respective owners.

11.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.4 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

www.ti.com 30-Jan-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TS321ID Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 125 SR321I TS321IDBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (9C1G, 9C1M, 9C1S) TS321IDBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (9C1G, 9C1M, 9C1S) TS321IDBVRG4 Obsolete Production SOT-23 (DBV) | 5 - - Call TI Call TI -40 to 125 9C1G TS321IDBVT Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (9C1G, 9C1S) TS321IDBVT.A Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (9C1G, 9C1S) TS321IDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 SR321I TS321IDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 SR321I (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative Addendum-Page 1

www.ti.com 30-Jan-2026 and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TS321 :

• Automotive : TS321-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 4-Apr-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 4-Apr-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TS321IDBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 TS321IDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TS321IDBVT SOT-23 DBV 5 250 202.0 201.0 28.0 TS321IDBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TS321IDR SOIC D 8 2500 353.0 353.0 32.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.25 3.0 2.6 2X 0.95 1.9 1.45 0.90 0.15

0.00 TYP

5X 0.5 0.3 0.6

0.3 TYP

0 TYP

1.9 (0.1) (0.15) 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25 mm per side. 5. Support pin may differ or may not be present.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/K 08/2024 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

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