Dual Low-Dropout Linear Regulator datasheet
Document overview
- Manufacturer or author: Texas Instruments, Incorporated [SLVS365,*]
- PDF pages: 18
Technical content
/C0084/C0080/C0080/C0077/C0048/C0049/C0049/C0048 /C0068/C0085/C0065/C0076 /C0076/C0079/C0087/C0262/C0068/C0082/C0079/C0080/C0079/C0085/C0084 /C0076/C0073/C0078/C0069/C0065/C0082 /C0082/C0069/C0071/C0085/C0076/C0065/C0084/C0079/C0082 SLVS365 −MARCH 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Dual Voltage Output, 3.3 V ±3% and
1.8 V ±2%
/C00683.3-V Output Within 2 V of 1.8-V Output Under All Conditions /C00681.5-A Load Current Capability on 3.3-V Output /C0068300-mA Load Current Capability on 1.8-V Output /C0068Overcurrent Protection for Both Outputs /C0068Thermally-Enhanced Packaging Concept for Efficient Heat Management /C0068Thermal Shutdown to Protect Device During Excessive Power Dissipation
description
The TPPM0110 is a power source intended for use in systems that have a single 5-V input source and require dual, linearly-regulated, low-dropout voltage sources. The outputs must track within 2 V of each other during all conditions and modes of operation. Each output is protected against overcurrent conditions. In the event that one of the outputs is shorted to ground, the other output must maintain a voltage output differential of less than 2 V compared to the output with the abnormal condition. The 3.3-V ± 3% regulated output is capable of driving loads of 1.5 A, and the 1.8-V ± 2% regulated output is capable of driving loads of 300 mA under all normal operating conditions. The device is available in a PowerPAD thermally-enhanced package for efficient heat management, and requires a copper plane to dissipate the heat. PowerPAD is a trademark of Texas Instruments. Copyright 2001, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NC NC NC 3.3VOUT NC 5VCC NC 1.8VOUT NC NC GND NC NC NC NC NC NC NC NC NC DWP HSOP PACKAGE (TOP VIEW)
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Bandgap Reference 3.3VOUT Startup, Interlock, Overcurrent, and Thermal Shutdown Control Control GND Bandgap Reference 1.8VOUT Control Startup, Interlock, Overcurrent, and Thermal Shutdown Control
Table 1. Input Selection‡ implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND.
- Absolute negative voltage values on these terminals should not be below –0.5 V.
- Assumed correct thermal management technique implementation and ambient temperature of 25°C.
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electrical characteristics, TA = 0°C to 55°C, CL = 100 µF, V(5VCC) = 5 V (unless otherwise noted) The operating ratings specified below is interpreted as conditions that do not degrade the device’s parametric or functional specifications for the life of the product. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(5VCC) Input voltage 4.7 5 5.3 V I(Q) Quiescent supply current IO(3.3VOUT) = 1.2 A and IO(1.8VOUT) = 300 mA 1 mA I(Q) Quiescent supply current With no loads on outputs 600 µA IO Output load current 3.3VOUT = 3.3 V ±3% 1.5 A IO Output load current 1.8VOUT = 1.8 V ±2% 300 mA V(DO) Regulator drop-out3.3VOUT IO < 1.2 A 1 VV(DO) Regulator drop-out voltage 1.8VOUT IO < 250 mA 2.5 V I(3.3VOUT)OC Overcurrent protection 3.3VOUT, IL↑, See Note 4 2.25 3 5.4 A I(3.3VOUT)OC Overcurrent protection Hysteresis 500 mA I(1.8VOUT)OC Overcurrent protection 1.8VOUT, See Note 4 0.45 0.6 1.08 A I(1.8VOUT)OC Overcurrent protection Hysteresis 200 mA C L Load capacitance for both regulated outputs 100 µF ESR (CL) Equivalent series resistance 1 Ω Vth Threshold voltage 5 V ↓, IO(3.3VOUT)= 1.2 A, IO(1.8VOUT) = 250 mA 3.4 4.2 V Vth Threshold voltage Hysteresis 250 mV TTSD † Thermal shutdown hysteresis Temperature ↑ 150 180 °CTTSD † Thermal shutdown hysteresis Hysteresis 15 † Design targets only. Not tested in production. NOTE 4: In the event of an overcurrent condition, the output should be a constant current limit such that the current never exceeds 360% of IO(TYP). Once the overcurrent condition is removed, the device returns to within the specified regulation limits. electrical characteristics, TA = 0°C to 55°C, CL = 100 µF, V(5VCC) = 5 V (unless otherwise noted)† The following parametric requirements are applicable to both 3.3VOUT and 1.8VOUT when subjected to these transient tests. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(OTL) Output transient voltage limitVoltage that load step can affect nominal output voltage (see Note 5) −3% 3% IO(STEP) Output load step current See Note 5 0 IO(TYP) A IO(SLEW) Output load step current slew rateSee Note 5 and 6 8 A/µs t(STEP) Output transient time limit See Note 5 10 µs Power up overshoot Maximum voltage overshoot allowed on either output when component begins regulation. Voltage transient time limit is t(STEP) (see Note 5) 7 % † Design targets only. Not tested in production.. NOTES: 5. Both outputs must maintain voltage regulation within ±3% of nominal, for a load step from 0 to IO(TYP) and from IO(TYP) to 0 A with a current slew rate of 8A/ms. Load may be toggled at a rate of 20 kHz typical. The outputs must return to the specified regulation limits within the specified time of 10 µs (typical). 6. Both linear regulators must be capable of regulating small ESR ceramic capacitors or aluminum electrolytic capacitors (see ESR specification).
NOTE 7: See JEDEC PCB specifications for high-K and correct implementation for 150 LFM air flow. NOTE: The 100-µF capacitor has: ESL = 3 nH and ESR = 0.5 Ω to 1 Ω. equivalent series inductance ESL < 3 nH and equivalent series resistance ESR < 1 Ω. Figure 1. Test Circuit
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NOTE: The outputs track within 2 V in the power-up and power-down sequence. Figure 2. Power-Up and Power-Down Sequence NOTE: The outputs track within 2 V in the power-up sequence. Figure 3. Power-Up Sequence
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Figure 6. Load Regulation on 3.3VOUT Figure 7. Settling Time Due to Load Regulation on 3.3VOUT
/C0084/C0080/C0080/C0077/C0048/C0049/C0049/C0048 /C0068/C0085/C0065/C0076 /C0076/C0079/C0087/C0262/C0068/C0082/C0079/C0080/C0079/C0085/C0084 /C0076/C0073/C0078/C0069/C0065/C0082 /C0082/C0069/C0071/C0085/C0076/C0065/C0084/C0079/C0082 SLVS365 −MARCH 2001 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL THERMAL CHARACTERISTICS To ensure reliable operation of the device, the junction temperature of the output device must be within the safe operating area (SOA). This is achieved by providing a means to dissipate the heat generated from the junction of the output structure. There are two components that contribute to thermal resistance. They consist of two paths in series. The first is the junction-to-case thermal resistance, R θJC; the second is the case-to-ambient thermal resistance, RθCA . The overall junction-to-ambient thermal resistance, RθJA, is determined by: R θJA = RθJC + RθCA The ability to efficiently dissipate the heat from the junction is a function of the package style and board layout incorporated in the application. The operating junction temperature is determined by the operating ambient temperature, T A, and the junction power dissipation, PJ. The junction temperature, TJ, is determined by the following thermal equation: TJ = TA + PJ (RθJC) + PJ (RθCA ) TJ = TA + PJ (RθJA) This particular application uses the 20-pin DWP power pad package with a standard lead frame with a dedicated ground terminal. Using a multilayer printed-circuit board (PCB), the power pad is mounted as recommended in the TI packaging application. The power pad is electrically connected to the ground plane of the board through a dedicated ground pin and the die mount power pad. This provides a means for heat spreading through the copper plane associated within the PCB (ground layer). The thermal resistance from junction to ambient, R θJA, is dependent of several factors, the implemented method of package attachment to the heat spreading material and the air flow in the system application.
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APPLICATION INFORMATION
To maximize the efficiency of this package for application on a single layer or multilayer PCB, certain guidelines must be followed. The following information is to be used as a guideline only. For further information, refer to the PowerPAD concept implementation document. multilayer PCB The following are guidelines for mounting the PowerPAD IC on a multilayer PCB with a ground plane. Solid Pad (Land Pattern) Package Thermal Pad Thermal Vias Via = 0,33 mm Diameter Minimum Pitch Between Vias is 1,52 mm Package Outline Figure 8. Package and Land Configuration for a Multilayer PCB Figure 9. Multilayer Board (Side View)
www.ti.com 11-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPPM0110DWP Obsolete Production SO PowerPAD (DWP) | 20 - - Call TI Call TI 0 to 70 TPPM0110 TPPM0110DWPR Active Production SO PowerPAD (DWP) | 20 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR 0 to 70 TPPM0110 TPPM0110DWPR.A Active Production SO PowerPAD (DWP) | 20 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR 0 to 70 TPPM0110 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 20-Apr-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TPPM0110DWPR SO PowerPAD Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 20-Apr-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPPM0110DWPR SO PowerPAD DWP 20 2000 350.0 350.0 43.0 Pack Materials-Page 2
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