TPLD1201

TPLD1201 Programmable Logic Device with 8-GPIO datasheet (Rev. F)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SCPS287,F]
• PDF pages: 60

Technical content

TPLD1201 Programmable Logic Device with 8-GPIO

1 Features

• Operating characteristics – Extended temperature range: -40°C to 125°C – Wide supply voltage range: 1.71V to 5.5V
• Configurable macro-cells – 2-, 3-, and 4-bit lookup tables – D-type flip-flops and latches with and without reset/set option – 8-bit pipe delay – Counters and delay generator – Programmable deglitch filter or edge detector – Discrete analog comparators – Voltage reference – Oscillator
• Flexible digital I/O features – All digital signals can be routed to any GPIO – Digital input modes: digital in with and without Schmitt-trigger, low-voltage digital in – Digital output modes: push-pull, open-drain NMOS, tri-state
• Development tools – InterConnect Studio – Evaluation module – TPLD programming board

2 Applications

• Factory automation and control
• Communications equipment
• Retail automation and payment
• Test and measurement
• Pro audio, video and signage
• Personal electronics

3 Description

The TPLD1201 is part of the TI programmable logic device (TPLD) family of devices that feature versatile programmable logic ICs with combinational logic, sequential logic, and analog blocks. TPLD provides a fully integrated, low power solution to implement common system functions, such as timing delays, voltage monitors, system resets, power sequencers, I/O expanders, and more. This device features configurable I/O structures that extends compatibility within mixed-signal environments, reducing the number of discrete components required. System designers can create circuits and configure the macro-cells, I/O pins, and interconnections by temporarily emulating the non-volatile memory or by permanently programming the one-time programmable (OTP) through InterConnect Studio . The TPLD1201 is supported by a hardware and software ecosystem with application notes, reference designs, and design examples. Visit ti.com for more information and access to design tools.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) TPLD1201 RWB (X2QFN, 12) 1.6mm × 1.6mm DGS (VSSOP, 10) 4.9mm × 3.0mm RWS (X2QFN, 12) 1.6mm × 1.6mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. D CLK Q D CLK Q D CLK Q D CLK Q IN CLK OUT1 OUT0 NRST RST CLK OUT cnt dff dff dff dff pipedelay EN (IO) POW1 (IO) POW2 (IO) POW3 (IO) POW4 (IO) POW5 (IO)OUT por osc lut lut lut lut Simplified Application TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11 Mechanical, Packaging, and Orderable

SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 www.ti.com

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4 Pin Configuration and Functions

9 GND

Figure 4-1. RWB Package, 12-Pin X2QFN (Top View) GPI GPIO2 GPIO1 GPIO4 GND VCC GPIO9 GPIO6 GPIO7 GPIO5 Not to scale Figure 4-2. DGS Package, 10-Pin VSSOP (Top View) Not to scale

7 GND

Figure 4-3. RWS Package, 12-Pin X2QFN (Top View) Table 4-1. Pin Functions PIN DESCRIPTION NAME RWB DGS RWS TYPE(1) Primary function Secondary function (if any) GPI 4 1 2 I General-purpose input(3) GPIO1 5 2 3 I/O General-purpose I/O ACMP0 IN+ GPIO2 6 3 4 I/O General-purpose I/O External VREF IN/ACMP0 or ACMP1 IN- GPIO4 8 4 6 I/O General-purpose I/O with output enable (OE)(4) ACMP1 IN+ GND 9 5 7 P Ground GPIO5 10 6 8 I/O General-purpose I/O GPIO6 11 7 9 I/O General-purpose I/O GPIO7 12 8 10 I/O General-purpose I/O with output enable (OE)(4) Internal VREF OUT GPIO9 2 9 12 I/O General-purpose I/O External OSC IN VCC 3 10 1 P Supply voltage NC 1 — 5 — Not internally connected(2) NC 7 — 11 — Not internally connected(2) (1) P = power, I/O = input/output, I = Input (2) Pins not internally connected must be grounded or left floating (3) The general-purpose input (GPI) pin will sustain a high-voltage (VPP) during programming. Take special precaution with peripherals connected to this pin if performing in-system programming. (4) The output enable (OE) connection is available through the connection mux and can be configured in InterConnect Studio. www.ti.com TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPLD1201

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage on VCC relative to GND -0.5 7 V VI Input voltage -0.5 VCC + 0.5 V VO Output voltage -0.5 VCC + 0.5 V IIOK Input-output clamp current VIO < 0 or VIO > VCC -50 50 mA IO Continuous output current VO = 0 to VCC -50 50 mA IDC Maximum average or DC current (through each pin) Push-pull 1X 12 mA Push-pull 2X 17 Open-drain NMOS 1X 18 Open-drain NMOS 2X 28 TJ Junction temperature 150 °C Tstg Storage temperature -65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V Charged device model (CDM), per ANSI/ESDA/JEDEC specification JS-002, all pins(2) ±1500 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) VCC MIN MAX UNIT VCC Supply voltage 1.71 5.5 V VI Input voltage 0 VCC V VO Output voltage 0 VCC V VAI Analog input voltage Positive input (ACMP IN+) 0 VCC VNegative input (ACMP IN-, Ext. VREF) 0.15 1.2 VIH High-level input voltage Logic input 1.71V to 5.5V 0.7 × VCC V Low-voltage logic input 1.8V ± 0.09V 0.95 3.3V ± 0.3V 1.2 5V ± 0.5V 1.3 VIL Low-level input voltage Logic input 1.71V to 5.5V 0.3 × VCC V Low-voltage logic input 1.8V ± 0.09V 0.40 3.3V ± 0.3V 0.55 5V ± 0.5V 0.65 TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 www.ti.com

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5.3 Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted) VCC MIN MAX UNIT F(EXT) External Oscillator Frequency 1.8V ± 0.09V 8 MHz3.3V ± 0.3V 8 5V ± 0.5V 8 TA Ambient temperature –40 125 °C

5.4 Thermal Information

THERMAL METRIC(1) UNIT RθJA RθJC(top) RθJB ΨJT ΨJB RθJC(bot) (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Supply and Power-on Reset VPORR Power-on reset voltage, VCC rising VI = VCC or VPORF Power-on reset voltage, VCC falling VI = VCC or tSU Startup time from VCC rising past VPORR 1.71V to 5.5V 245 µs VPP Programming voltage 7.5 8 V Digital IO VT+ Positive-going input threshold voltage Logic Input with Schmitt Trigger 1.8V ± 0.09V 0.94 1.27 V3.3V ± 0.3V 1.55 2.30 5V ± 0.5V 2.21 3.19 VT- Negative-going input threshold voltage Logic Input with Schmitt Trigger 1.8V ± 0.09V 0.58 0.94 V3.3V ± 0.3V 1.1 1.79 5V ± 0.5V 1.63 2.7 VHYS Schmitt trigger hysteresis (VT+ − VT−) Logic Input with Schmitt Trigger 1.8V ± 0.09V 0.20 0.51 V3.3V ± 0.3V 0.33 0.61 5V ± 0.5V 0.42 0.75 VHYS GPI Hysteresis Voltage Hysteresis voltage applicable to the IN0 1.71V to 5.5V 0.2 V www.ti.com TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPLD1201

5.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VOH High-level output voltage Push-pull 1X or Open- drain PMOS 1X IOH = -100µA 1.8V ± 0.09V 1.68 V Push-pull 2X or Open- drain PMOS 2X 1.69 Push-pull 1X or Open- drain PMOS 1X IOH = -3mA 3.3V ± 0.3V 2.60 Push-pull 2X or Open- drain PMOS 2X 2.71 Push-pull 1X or Open- drain PMOS 1X IOH = -5mA 5V ± 0.5V 3.99 Push-pull 2X or Open- drain PMOS 2X 4.13 VOL Low-level output voltage Push-pull 1X IOL = 100µA 1.8V ± 0.09V 0.038 V Push-pull 2X 0.034 Open-drain NMOS 1X 0.045 Open-drain NMOS 2X 0.02 Push-pull 1X IOL = 3mA 3.3V ± 0.3V 0.1 Push-pull 2X 0.1 Open-drain NMOS 1X 0.1 Open-drain NMOS 2X 0.1 Push-pull 1X IOL = 5mA 5V ± 0.5V 0.12 Push-pull 2X 0.12 Open-drain NMOS 1X 0.12 Open-drain NMOS 2X 0.12 II Input leakage current All pins VI = VCC 1.71V to 5.5V ±1 µA VI = GND 1.71V to 5.5V ±1 IOZ Off-state (high-Z state) output current IO4, IO7 VO = 0 to 5.5V ±1 µA FOUT Max output frequency(1) Push-pull 1X or Push-pull 15pF Load capacitance 1.8V ± 0.09V 5 MHz3.3V ± 0.3V 12 5V ± 0.5V 12 Rpu(int) Internal pull-up resistance 1 MΩ 100 kΩ 10 kΩ Rpd(int) Internal pull-down resistance 1 MΩ 100 kΩ 10 kΩ CI Input pin capacitance each input pin VI = VCC or GND 1.71V to 5.5V 1.2 pF CIO Input-output pin capacitance each I/O pin VIO = VCC or GND 1.71V to 5.5V 2.0 pF Analog Comparator tstart Start time ACMP power on delay Bandgap always on 1.71V to 5.5V 130 µs VAI Input voltage Positive input 1.71V to 5.5V

0 VCC

V Negative input 0 1.2 TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 www.ti.com

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over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Voffset Input offset voltage TA = 25℃ VHYS = 0mV, Gain = 1, VREF= 50mV - 1200mV 1.71V to 5.5V -10 10 mV –40°C < TA ≤ 125°C -15 15 dVIO/d T Input offset voltage drift –40°C < TA ≤ 125°C VHYS = 0mV, Gain = 1, VREF= 50mV - 1200mV 1.71V to 5.5V ±8.5 µV/ºC IB Input bias current 1 µA CID Input capacitance, differential 3 pF CIM Input capacitance, common mode 3 pF PROP Propagation delay, response time Gain = 1, Vref = 50mV - 1200mV, Overdrive = 50mV Low to High, Low bandwidth enabled 1.71V to 5.5V 1.5 µs High to Low Low bandwidth enabled 2.5 Low to High, Low bandwidth disabled 0.25 High to Low Low bandwidth disabled 0.15 Analog Comparator - Hysteresis VHYS Built-in hysteresis VHYS = 25mV TA = 25℃ 1.71V to 5.5V 16 21.6 35 mV -40ºC to 125ºC 15 40 VHYS = 50mV TA = 25℃ 42 50.7 62 -40ºC to 125ºC 40 65 VHYS = 200mV TA = 25℃ 170 202 240 -40ºC to 125ºC 165 245 Analog Comparator - Input Gain Rsin Series input resistance Gain = 0.5 1.71V to 5.5V MΩGain = 0.33 0.75 Gain = 0.25 1 Gerr Gain error Gain = 0.5 1.71V to 5.5V -1 1 Gain = 0.25 -1.5 2.5 Voltage Reference VREF Internal VREF error TA = 25℃ VREF = 150mV - 300mV 1.71V to 5.5V -8.5 8.5 TA = 25℃ VREF = 350mV - 600mV -3 3 TA = 25℃ VREF = 650mV - 1000mV -2.5 2.5 TA = 25℃ VREF = 1050mV - 1200mV -3 3 www.ti.com TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPLD1201

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VREF VREF error TA = 25℃ VREF = 150mV - 300mV 1.71V to 5.5V -10.2 10.2 –40°C < TA ≤ 125°C -11 11 TA = 25℃ VREF = 350mV - 600mV -5 5 TA = 25℃ VREF = 650mV - 1000mV -3.3 3.3 TA = 25℃ VREF = 1050mV - 1200mV -4 4 ILOAD Output Current 1.71V to 5.5V 500 µA dVOUT/ dT Output voltage temperature drift 1.71V to 5.5V 550 ppm/ºC dVOUT/ dILOAD Load regulation 1.71V to 5.5V 0.1 1 mV/µA (1) Open drain switching performance will be limited by pull-up resistors used

5.6 Supply Current Characteristics

TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX Standby ICC Quiescent current Inputs = static, Outputs = open, IO = 0, OSC powered off 3.41 3.66 4.00 µA Oscillator ICC Quiescent current OSC0 enabled: 25kHz Predivide = 1 3.21 5.24 10.1 µA Predivide = 2 3.14 5.17 10.1 Predivide = 4 3.53 5.11 10.1 Predivide = 8 3.08 5.28 10.0 OSC0 enabled: 2MHz Predivide = 1 42.9 56.0 84.9 Predivide = 2 35.9 49.0 79.2 Predivide = 4 32.5 45.6 75.5 Predivide = 8 30.7 43.8 73.8 Analog Comparator ICC Quiescent current Discrete analog comparator (ACMP) External VREF, IN+ = 0V 24.8 26.2 26.8 µA Additional ACMP 3.2 4.7 4.7 Voltage Reference ICC Quiescent current Voltage reference (VREF) 16.8 18.3 19.9 µA TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 www.ti.com

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5.7 Switching Characteristics

TA = 25°C (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS VCC MIN TYP MAX UNIT Digital IO tpd Delay Digital input Push-pull output Rising 1.8V ± 0.09V 46.2 ns Falling 39.1 Rising 3.3V ± 0.3V 27.2 Falling 24.5 Rising 5V ± 0.5V 22.1 Falling 21.1 tpd Delay Digital input with Schmitt trigger Push-pull output Rising 1.8V ± 0.09V 49.5 ns Falling 41.5 Rising 3.3V ± 0.3V 29.3 Falling 25.3 Rising 5V ± 0.5V 23.9 Falling 21.5 tpd Delay Low-voltage digital input Push-pull output Rising 1.8V ± 0.09V 45.0 ns Falling 48.1 Rising 3.3V ± 0.3V 25.4 Falling 30.3 Rising 5V ± 0.5V 19.6 Falling 28.6 tpd Delay Digital input Open-drain NMOS output Rising 1.8V ± 0.09V ns Falling 38.8 Rising 3.3V ± 0.3V Falling 24.3 Rising 5V ± 0.5V Falling 20.9 tpd Delay Output enable from pin OE Push-pull output Hi-Z to 1 1.8V ± 0.09V 45.0 ns3.3V ± 0.3V 26.5 5V ± 0.5V 21.7 Hi-Z to 0 1.8V ± 0.09V 43.2 ns3.3V ± 0.3V 22.6 5V ± 0.5V 18.3 Configurable Use Logic tpd Delay 2-bit LUT IN OUT Rising 1.8V ± 0.09V 1.14 ns Falling 1.32 Rising 3.3V ± 0.3V 1.14 Falling 1.31 Rising 5V ± 0.5V 1.16 Falling 1.35 www.ti.com TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPLD1201

5.7 Switching Characteristics (continued)

TA = 25°C (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS VCC MIN TYP MAX UNIT tpd Delay 3-bit LUT IN OUT Rising 1.8V ± 0.09V 1.31 ns Falling 1.53 Rising 3.3V ± 0.3V 1.31 Falling 1.53 Rising 5V ± 0.5V 1.31 Falling 1.53 tpd Delay 4-bit LUT IN OUT Rising 1.8V ± 0.09V 1.53 ns Falling 1.86 Rising 3.3V ± 0.3V 1.53 Falling 1.86 Rising 5V ± 0.5V 1.53 Falling 1.86 tpd Delay DFF/Latch CLK Q Rising 1.8V ± 0.09V 1.42 ns Falling 1.44 Rising 3.3V ± 0.3V 1.42 Falling 1.44 Rising 5V ± 0.5V 1.42 Falling 1.44 tpd Delay DFF/Latch nRST/nSET Q Rising 1.8V ± 0.09V 1.58 ns Falling 1.58 Rising 3.3V ± 0.3V 1.58 Falling 1.58 Rising 5V ± 0.5V 1.58 Falling 1.58 Counter/Delay tpd Delay Counter - Delay mode Rising edge of IN Rising edge of OUT Falling edge triggered 1.8V ± 0.09V 2.21 ns Falling edge of IN Falling edge of OUT Rising edge triggered 2.01 Rising edge of IN Rising edge of OUT Falling edge triggered 3.3V ± 0.3V 2.21 Falling edge of IN Falling edge of OUT Rising edge triggered 2.01 Rising edge of IN Rising edge of OUT Falling edge triggered 5V ± 0.5V 2.21 Falling edge of IN Falling edge of OUT Rising edge triggered 2.01 TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 www.ti.com

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TA = 25°C (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS VCC MIN TYP MAX UNIT tpw Pulse width Counter - Edge detect mode Rising edge of OUT Falling edge of OUT Rising edge detect 1.8V ± 0.09V 57.6 ns 3.3V ± 0.3V 61.4 5V ± 0.5V 62.0 Falling edge detect 1.8V ± 0.09V 56.0 3.3V ± 0.3V 59.6 5V ± 0.5V 60.4 Both edge detect 1.8V ± 0.09V 55.9 3.3V ± 0.3V 59.7 5V ± 0.5V 60.5 Oscillator ferr Oscillator frequency error OSC025kHz 1.8V ± 0.09V -5 5 %3.3V ± 0.3V -5 5 5V ± 0.5V -5 5 OSC0 2MHz 1.8V ± 0.09V -5 5 %3.3V ± 0.3V -5 5 5V ± 0.5V -5 5 td_osc Oscillator startup delay OSC025kHz 1.8V ± 0.09V 11.5 µs3.3V ± 0.3V 10.5 5V ± 0.5V 9.9 OSC0 2MHz 1.8V ± 0.09V 3.3 µs3.3V ± 0.3V 2.7 5V ± 0.5V 2.5 tset_osc Oscillator startup settling time OSC025kHz 1.8V ± 0.09V 1 µs3.3V ± 0.3V 1 5V ± 0.5V 1 OSC0 2MHz 1.8V ± 0.09V 7 µs3.3V ± 0.3V 7 5V ± 0.5V 7 td_err Delay error OSC (Forced power on) 1.71V to 5.5V 0 1 CLK cycle Programmable Filter tpflt_pw Pulse width Programmable filter - Edge detect mode Rising edge of OUT Falling edge of OUT 1cell 1.8V ± 0.09V 154.0 ns3.3V ± 0.3V 157.3 5V ± 0.5V 158.7 2 cells 1.8V ± 0.09V 256.2 ns3.3V ± 0.3V 259.7 5V ± 0.5V 260.8 3 cells 1.8V ± 0.09V 356.2 ns3.3V ± 0.3V 360.3 5V ± 0.5V 361.5 4 cells 1.8V ± 0.09V 455.3 ns3.3V ± 0.3V 459.6 5V ± 0.5V 461.4 www.ti.com TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TPLD1201

TA = 25°C (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS VCC MIN TYP MAX UNIT tpflt_pd Delay Programmable filter - Edge detect mode Any cells 1.8V ± 0.09V 22.0 ns3.3V ± 0.3V 21.4 5V ± 0.5V 21.3 tpflt_d Delay Programmable filter - Both edge delay mode Rising/Falling edge of IN Rising/Falling edge of OUT 1cell 1.8V ± 0.09V 176.0 ns3.3V ± 0.3V 178.7 5V ± 0.5V 161.0 2 cells 1.8V ± 0.09V 278.2 ns3.3V ± 0.3V 281.1 5V ± 0.5V 282.1 3 cells 1.8V ± 0.09V 378.2 ns3.3V ± 0.3V 352.1 5V ± 0.5V 382.8 4 cells 1.8V ± 0.09V 477.3 ns3.3V ± 0.3V 481.0 5V ± 0.5V 482.7 TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 www.ti.com

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5.8 Typical Characteristics

TA = 25°C I O H O u t p u t H i g h C u r r e n t ( m A ) VOHOutput High Voltage (V) 1 . 5 1 . 8 2 . 1 2 . 4 2 . 7 3 . 3 3 . 6 3 . 9 4 . 2 4 . 5 4 . 8 5 . 1 1 . 8 V 2 . 5 V 3 . 3 V 5 V Figure 5-1. Typical 1X Push-Pull Output Voltage in the High State (VOH) I O L O u t p u t L o w C u r r e n t ( m A ) VOLOutput Low Voltage (V) 0 . 0 0 5 0 . 0 1 0 . 0 1 5 0 . 0 2 0 . 0 2 5 0 . 0 3 0 . 0 3 5 0 . 0 4 0 . 0 4 5 0 . 0 5 0 . 0 5 5 0 . 0 6 0 . 0 6 5 0 . 0 7 0 . 0 7 5 0 . 0 8 1 . 8 V 2 . 5 V 3 . 3 V 5 V Figure 5-2. Typical 1X Push-Pull Output Voltage in the Low State (VOL) I O H O u t p u t H i g h C u r r e n t ( m A ) VOHOutput High Voltage (V) 1 . 5 1 . 8 2 . 1 2 . 4 2 . 7 3 . 3 3 . 6 3 . 9 4 . 2 4 . 5 4 . 8 5 . 1 1 . 8 V 2 . 5 V 3 . 3 V 5 V Figure 5-3. Typical 2X Push-Pull Output Voltage in the High State (VOH) I O L O u t p u t L o w C u r r e n t ( m A ) VOLOutput Low Voltage (V) 0 . 0 0 5 0 . 0 1 0 . 0 1 5 0 . 0 2 0 . 0 2 5 0 . 0 3 0 . 0 3 5 0 . 0 4 0 . 0 4 5 0 . 0 5 1 . 8 V 2 . 5 V 3 . 3 V 5 V Figure 5-4. Typical 2X Push-Pull Output Voltage in the Low State (VOL) I O L O u t p u t L o w C u r r e n t ( m A ) VOLOutput Low Voltage (V) 0 . 0 0 5 0 . 0 1 0 . 0 1 5 0 . 0 2 0 . 0 2 5 0 . 0 3 0 . 0 3 5 0 . 0 4 0 . 0 4 5 0 . 0 5 0 . 0 5 5 0 . 0 6 0 . 0 6 5 0 . 0 7 0 . 0 7 5 0 . 0 8 1 . 8 V 2 . 5 V 3 . 3 V 5 V Figure 5-5. Typical 1X Open-Drain NMOS Output Voltage in the Low State (VOL) I O L O u t p u t L o w C u r r e n t ( m A ) VOLOutput Low Voltage (V) 0 . 0 0 5 0 . 0 1 0 . 0 1 5 0 . 0 2 0 . 0 2 5 0 . 0 3 0 . 0 3 5 0 . 0 4 0 . 0 4 5 0 . 0 5 1 . 8 V 2 . 5 V 3 . 3 V 5 V Figure 5-6. Typical 2X Open-Drain NMOS Output Voltage in the Low State (VOL) www.ti.com TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPLD1201

6 Parameter Measurement Information

Phase relationships between waveforms are selected arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, ZO = 50Ω, tt < 2.5ns. For clock inputs, fmax is measured when the input duty cycle is 50%. The outputs are measured one at a time with one input transition per measurement. CL (1) RL From Output Under Test VCCTest Point (1) CL includes probe and test-fixture capacitance. Figure 6-1. Load Circuit for 3-State Outputs CL (1) RLFrom Output Under Test VCCTest Point (1) CL includes probe and test-fixture capacitance. Figure 6-2. Load Circuit for Open-Drain Outputs CL (1) From Output Under Test Test Point (1) CL includes probe and test-fixture capacitance. Figure 6-3. Load Circuit for Push-Pull Outputs 50% tw Input 50% VCC 0 V Figure 6-4. Voltage Waveforms, Pulse Duration Clock Input 50% VCC 0 V 50% 50% VCC 0 V tsu Data Input th Figure 6-5. Voltage Waveforms, Setup and Hold Times 50%Input 50% VCC 0 V 50% 50% VOH VOL tPLH (1) tPHL (1) VOH VOL tPHL (1) tPLH (1) Output Output 50% 50% (1) The greater between tPLH and tPHL is the same as tpd. Figure 6-6. Voltage Waveforms Propagation Delays TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 www.ti.com

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7 Detailed Description

7.1 Overview

The TPLD1201 is part of the TI programmable logic device (TPLD) family of devices that feature versatile programmable logic ICs with combinational logic, sequential logic, and analog blocks to provide an integrated, compact, low power solution to implement common system functions. The TPLD1201 has one GPI and seven GPIOs that can be configured as a digital input, digital output, digital input or output, or analog input or output. The TPLD1201 has a system of interconnects, further referred to as the connection mux, to configure the routing of internal macro-cells and I/O pins. Each connection mux input is hardwired to a specific digital macro-cell output, such as digital I/O, lookup tables, and analog comparator outputs. The connection mux allows each of the digital inputs to only connect to one output so that bus contention does not occur. The TPLD1201 features the following macro-cells:

• Configurable use logic blocks: – Two 2-bit lookup tables (LUT) – Two 3-bit LUTs – Two 2-bit LUTs or D-type flip-flops (DFF) or latches – Two 3-bit LUTs or DFF or latches with reset/set option – One 3-bit LUT or Pipe delay – One 4-bit LUT or 8-bit counter (CNT) or delay generator (DLY)
• Three 8-bit CNT/DLYs
• One programmable deglitch filter (PFLT) or edge detector (EDET)
• One oscillator (OSC) to generate either a 25kHz or 2MHz clock
• Two analog comparators (ACMP)
• Voltage reference (VREF) with option to output to analog IO The InterConnect Studio software environment enables a simple drag-and-drop interface to build custom circuit designs and configure the macro-cells, I/O pins, and interconnections. In addition to circuit creation, InterConnect Studio has the ability to simulate digital and analog functionality to verify designs and provide a typical power consumption estimate. Once circuit designs are finalized, InterConnect Studio can temporarily emulate the design in the non-volatile memory or permanently program the one-time programmable (OTP). The OTP can be locked to prevent readback of its contents. TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 www.ti.com

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7.2 Functional Block Diagram

Connection Mux (CMX) Lookup Tables (LUTs) LUT2_2 LUT2_3 LUT3_2 LUT3_3 Configurable Use Logic Blocks LUT2_0 or DFF/L0 LUT2_1 or DFF/L1 LUT3_0 or DFF/L2 LUT3_1 or DFF/L3 LUT3_4 or Pipe Delay LUT4_0 or CNT/DLY2 Oscillator Analog Comparators Counter/Delay Generators Voltage Reference CNT/DLY0 CNT/DLY1 CNT/DLY3 ACMP0 ACMP1 VREF Bandgap BG Programmable Delay Generator Power-On reset PDLY/FILTER 25kHz or 2MHz POR GPIO NC VCC GPI GPIO GPIO NC GPIO GND GPIO GPIO GPIO7 Digital macrocell Analog macrocell Figure 7-1. TPLD1201 Functional Block Diagram www.ti.com TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPLD1201

7.3 Feature Description

7.3.1 I/O Pins

TPLD1201 has one input and seven multifunction I/O pins. GPIO pins can function as either a user defined input, output, or a special function.

7.3.1.1 Input Modes

The following options are available when configuring pins as an input:

• Digital input without Schmitt-trigger
• Digital input with Schmitt-trigger
• Low-voltage digital input The low-voltage digital input has lower V IH/VIL specifications than the digital input without Schmitt trigger. This allows for up-translation from any voltage domain lower than VCC that meets the low-voltage digital input VIH and VIL specifications. The following pins also have the option to operate as a special function:
• IO9: external clock input
• IO1: positive input of analog comparator 0
• IO2: negative input of analog comparators
• IO4: positive input of analog comparator 1
• IO7: internal voltage reference output

7.3.1.2 Output Modes

The following options are available with programmable drive strengths when configuring pins as an output:

• Push-pull output
• Open-drain NMOS output
• Open-drain PMOS output

7.3.1.3 Pull-Up or Pull-Down Resistors

All I/O pins have the option of user-selectable resistors that can be connected to the pin structure. The selectable values on these resistors are 10k Ω, 100k Ω and 1M Ω. The internal resistors can be configured as either pull-up or pull-down. When designing in InterConnect Studio , any pin left unused in a design are configured with a 1M Ω pull-down by default. Furthermore, following a power-on event, all ports are in a Hi-Z state until the power-on reset sequence has completed. Table 7-1. Pin Configuration Options GPIO IO Selection OE IO Options Resistor Resistor Value IN0 PIN not used — — Pull-Down 1MΩ Digital input 0 Digital in without Schmitt trigger Digital in with Schmitt trigger Low-voltage digital input Floating — Pull-Down 10kΩ 100kΩ 1MΩ TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 www.ti.com

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Table 7-1. Pin Configuration Options (continued) GPIO IO Selection OE IO Options Resistor Resistor Value IO1, IO2 Pin not used — — Pull Down 1MΩ Digital input 0 Digital in without Schmitt trigger Digital in with Schmitt trigger Low-voltage digital input Floating — Pull-Up 10kΩ 100kΩ 1MΩ Pull-Down 10kΩ 100kΩ 1MΩ Digital output 1 Push-pull (1X, 2X) Floating — Open-drain NMOS (1X, 2X) Open-drain PMOS (1X, 2X) Floating — Pull-Up 10kΩ 100kΩ 1MΩ Pull-Down 10kΩ 100kΩ 1MΩ Digital input/output

0 Analog input — —

Open-drain NMOS (1X, 2X) Floating — Pull-Up 10kΩ 100kΩ 1MΩ Pull-Down 10kΩ 100kΩ 1MΩ Analog input/output — Analog input/output Floating — Pull-Up 10kΩ 100kΩ 1MΩ Pull-Down 10kΩ 100kΩ 1MΩ www.ti.com TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPLD1201

Table 7-1. Pin Configuration Options (continued) GPIO IO Selection OE IO Options Resistor Resistor Value IO4, IO7 Pin not used — — Pull-Down 1MΩ Digital input 0 Digital in without Schmitt trigger Digital in with Schmitt trigger Low-voltage digital input Floating — Pull-Up 10kΩ 100kΩ 1MΩ Pull-Down 10kΩ 100kΩ 1MΩ Digital output 1/0 Push-pull (1X, 2X) Floating — Open-drain NMOS (1X, 2X) 3-state output (1X, 2X) Floating — Pull-Up 10kΩ 100kΩ 1MΩ Pull-Down 10kΩ 100kΩ 1MΩ Digital input/output Digital in without Schmitt trigger Digital in with Schmitt trigger Low-voltage digital input Analog input (IO4 only) Floating — Pull-Up 10kΩ 100kΩ 1MΩ Pull-Down 10kΩ 100kΩ 1MΩ

1 Push-pull (1X, 2X)

Open-drain NMOS (1X, 2X) Shared with above Analog input/output — Analog input/output Floating — Pull-Up 10kΩ 100kΩ 1MΩ Pull-Down 10kΩ 100kΩ 1MΩ TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 www.ti.com

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Table 7-1. Pin Configuration Options (continued) GPIO IO Selection OE IO Options Resistor Resistor Value IO5, IO6, IO9 Pin not used — — Pull Down 1MΩ Digital input 0 Digital in without Schmitt trigger Digital in with Schmitt trigger Low-voltage digital input Floating — Pull-Up 10kΩ 100kΩ 1MΩ Pull-Down 10kΩ 100kΩ 1MΩ Digital output 1 Push-pull (1X, 2X) Floating — Open-drain NMOS (1X, 2X) Open-drain PMOS (1X, 2X) Floating — Pull-Up 10kΩ 100kΩ 1MΩ Pull-Down 10kΩ 100kΩ 1MΩ Note GPI/IN0 also has the option to reset the device while powered on. Unlike POR, External Reset only resets the internal logic and routing, inputs, and outputs. The NVM retains its previous state. If GPI Reset is enabled, ensure that the input mode is set to Digital Input without Schmitt trigger. Users select whether the External Reset is Disabled, Level sensitive, or Edge triggered. When Level sensitive is selected, if the input is High, then the device is in reset mode where all internal devices are reset. When this pin goes Low, then the device begins the reset power on sequence. When Edge triggered is selected, the edge detector can be configured to Rising edge or Falling edge, and an edge on GPI/IN0 resets the device and begins the reset power on sequence.

7.3.2 Connection Mux

TPLD1201 has a system of interconnects, referred to as the connection mux, to configure the routing of internal macro-cells and I/O pins. The connection mux has 32 inputs and 44 outputs. Each of the 32 inputs of the connection mux is hardwired to particular macro-cells, including I/O pins, LUTs, analog comparators, other digital resources, VCC, and GND. The input to a digital macro-cell uses a 5-bit register to select one of these 32 input lines.

7.3.3 Configurable Use Logic Blocks

Combinational logic is supported through lookup tables (LUTs) within the TPLD1201 including two 2-bit LUTs and two 3-bit LUTs. Inputs and outputs for the combination function macro-cells are configured from the connection mux with specific logic functions being defined by the state of OTP bits. The TPLD1201 has seven combinational function blocks (macro-cells) that can serve more than one logic or timing function. In each case, they can serve as a lookup table (LUT), or as another logic or timing function. See the following list for the functions that can be implemented in these logic blocks:

• Two 2-bit LUTs
• Two 3-bit LUTs
• Two 2-bit LUTs or D-type flip-flops or latches
• Two 3-bit LUTs or D-type flip-flops or latches with reset/set option
• One 3-bit LUT or Pipe delay www.ti.com TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPLD1201

• One 4-bit LUT or 8-bit counter or delay generator 7.3.3.1 2-Bit LUT Macro-Cell When used to implement LUT functions, the 2-bit LUT takes in two input signals from the connection mux and produces a single output, which goes back into the connection mux. CMX_OUT CMX_OUT CMX_IN IN0 IN1 OUT 2-bit LUT CFG Figure 7-2. 2-Bit LUT Block Diagram These LUTs can be configured to any 2-input user defined function, including the following standard digital logic functions: AND, NAND, OR, NOR, XOR, XNOR, INV. Table 7-2 provides the truth table for a 2-bit LUT. Table 7-2. 2-Bit LUT Truth Table IN1 IN0 OUT 0 0 User defined 0 1 1 0 1 1 Each 2-bit LUT has 4 bits in the OTP to define their output function. TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 www.ti.com

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2-input user defined function, including the following standard digital logic functions: AND, NAND, OR, NOR, XOR, XNOR, INV. Table 7-4 provides the truth table for a 2-bit LUT. Table 7-4. 2-Bit LUT Truth Table IN1 IN0 OUT 0 0 User defined 0 1 1 0 1 1 Each 2-bit LUT has 4 bits in the OTP to define their output function. When used to implement a sequential logic element, the two input signals from the connection mux go to the data (D) and clock (CLK) inputs of the flip-flop/latch, with the output going back to the connection mux. This macro-cell has initial state parameters, as well as clock and output polarity parameters. The operation of the D flip-flop/latch follows the following functional descriptions:

• The clock polarity is configurable and can be set to non-inverted (CLKPOL = 0, CLK) or inverted (CLKPOL = 1, nCLK). – DFF with CLK: CLK is rising edge triggered, then Q = D; otherwise Q will not change. – DFF with nCLK: CLK is falling edge triggered, then Q = D; otherwise Q will not change. – Latch with CLK: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is High). – Latch with nCLK: when CLK is High, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is Low).
• The output polarity is configurable and can be set to non-inverted (Q) or inverted (nQ). Table 7-5 and Table 7-6 provides the truth tables for the D flip-flop and D latch, respectively. Table 7-5. D Flip-Flop Truth Table CLKPOL CLK D Q nQ ↓ 0 Q0 nQ0 ↑ 0 0 1 ↓ 1 Q0 nQ0 ↑ 1 1 0 ↓ 0 0 1 ↑ 0 Q0 nQ0 ↓ 1 1 0 ↑ 1 Q0 nQ0 Table 7-6. D Latch Truth Table CLKPOL CLK D Q nQ 0 0 0 1 1 0 Q0 nQ0 0 1 1 0 1 1 Q0 nQ0 TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 www.ti.com

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Table 7-6. D Latch Truth Table (continued) CLKPOL CLK D Q nQ 0 0 Q0 nQ0 1 0 0 1 0 1 Q0 nQ0 1 1 1 0 7.3.3.4 3-Bit LUT or D Flip-Flop or Latch with Set or Reset Macro-Cell This configurable use logic blocks can serve as either a 3-bit LUT, or as a D flip-flop/latch with a reset/set. CMX_OUT CMX_OUT CMX_IN FNC SEL IN0 IN1 OUT 3-bit LUT IN2 DFF/LCLK Q/nQD nRST/ nSET CMX_OUT CFG Figure 7-5. 3-Bit LUT or DFF or Latch with nRST or nSET Block Diagram When used to implement LUT functions, the 3-bit LUT takes in three input signals from the connection mux and produces a single output, which goes back into the connection mux. These LUTs can be configured to any 3-input user defined function, including the following standard digital logic functions: AND, NAND, OR, NOR, XOR, XNOR, INV. Table 7-7 provides the truth table for a 3-bit LUT. Table 7-7. 3-Bit LUT Truth Table IN2 IN1 IN0 OUT 0 0 0 User defined 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Each 3-bit LUT has 8 bits in the OTP to define their output function. www.ti.com TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TPLD1201

When used to implement a sequential logic element, the three input signals from the connection mux go to the data (D), clock (CLK), and reset/set (nRST/nSET) inputs for the flip-flop/latch, with the output going back to the connection mux. This macro-cell has initial state, clock polarity, reset/set polarity, and output polarity parameters. The operation of the D flip-flop/latch follows the following function descriptions:

• The clock polarity is configurable and can be set to non-inverted (CLKPOL = 0, CLK) or inverted (CLKPOL = 1, nCLK). – DFF with CLK: CLK is rising edge triggered, then Q = D; otherwise Q will not change. – DFF with nCLK: CLK is falling edge triggered, then Q = D; otherwise Q will not change. – Latch with CLK: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is High). – Latch with nCLK: when CLK is High, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is Low).
• These DFF/latches have an option for an active-low reset/set. – nRST: when the input is high, the DFF/latch is in normal operation; and when low, Q is reset to 0. – nSET: when the input is high, the DFF/latch is in normal operation; and when low, Q is set to 1.
• If reset/set is not desired, users can tie this input to VCC or another constant high source.
• The output polarity is configurable and can be set to non-inverted (Q) or inverted (nQ). Table 7-8 and Table 7-9 provides the truth tables for the D flip-flop and D latch with reset/set, respectively. Table 7-8. D Flip-Flop With nRST/nSET Truth Table nRST nSET CLKPOL CLK D Q nQ 0 — X X 0 1 — 0 X X 1 0 1 1 ↓ 0 Q0 nQ0 ↑ 0 0 1 ↓ 1 Q0 nQ0 ↑ 1 1 0 0 — X X 0 1 — 0 X X 1 0 1 1 ↓ 0 0 1 ↑ 0 Q0 nQ0 ↓ 1 1 0 ↑ 1 Q0 nQ0 Table 7-9. D Latch With nRST/nSET Truth Table nRST nSET CLKPOL CLK D Q nQ 0 — X X 0 1 — 0 X X 1 0 1 1 0 0 0 1 1 0 Q0 nQ0 0 1 1 0 1 1 Q0 nQ0 TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 www.ti.com

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Table 7-9. D Latch With nRST/nSET Truth Table (continued) nRST nSET CLKPOL CLK D Q nQ 0 — X X 0 1 — 0 X X 1 0 1 1 0 0 Q0 nQ0 1 0 0 1 0 1 Q0 nQ0 1 1 1 0 7.3.3.5 3-Bit LUT or Pipe Delay Macro-cell This macro-cell can serve as either a 3-bit LUT or as a pipe delay. CMX_OUT CMX_OUT CMX_IN FNC SEL IN0 IN1 OUT 3-bit LUT IN2 CMX_OUT IN nRST OUT0 OUT1 CMX_IN PIPE DELAY FF FF FF FF FF FF FF FF CFG Figure 7-6. 3-Bit LUT or Pipe Delay Block Diagram When used to implement LUT functions, the 3-bit LUT takes in three input signals from the connection mux and produces a single output, which goes back into the connection mux. These LUTs can be configured to any 3-input user defined function, including the following standard digital logic functions:

• AND
• NAND
• OR
• NOR
• XOR
• XNOR
• INV Table 7-10 provides the truth table for a 3-bit LUT. www.ti.com TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TPLD1201

Table 7-10. 3-Bit LUT Truth Table IN2 IN1 IN0 OUT 0 0 0 User defined 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Each 3-bit LUT has 8 bits in the OTP to define their output function. When used to implement a pipe delay, the three input signals from the connection mux go to the delay input (IN), clock (CLK), and reset (nRST) inputs for the flip-flop/latch, with two outputs going back to the connection mux. With this macro-cell, users can select the number of delay stages per output (from 1 to 8) and the output polarity for OUT1. The pipe delay is an 8-stage delay composed of 8 DFFs. The DFF cells are tied in series where the output of each delay cell goes to the next DFF cell. There are delay output points for each set of the OUT0 and OUT1 outputs to a mux that is used to control the selection of the amount of delay for each pipe delay output. For normal pipe delay functionality, the nRST input should be high. If nRST input is low, the pipe delay macro- cell is in a reset state and all outputs are low. Figure 7-7 shows an example of the pipe delay macro-cell with 2 stages of delay selected. nRST CLK IN OUT nOUT Figure 7-7. Pipe Delay Macro-Cell Timing Example (Delay = 2) 7.3.3.6 4-Bit LUT or 8-Bit Counter or Delay Macro-Cell This macro-cell can serve as either a 4-bit LUT or as a counter/delay generator (CNT/DLY). TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 www.ti.com

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CMX_OUT CMX_OUT FNC SEL CMX_OUT CMX_OUT CMX_IN CLK SEL CFG Figure 7-8. 4-Bit LUT or 8-Bit CNT/DLY Block Diagram When used to implement LUT functions, the 4-bit LUT takes in four input signals from the connection mux and produces a single output, which goes back into the connection mux. This LUT can be configured to any 4-input user defined function, including the following standard digital logic functions: AND, NAND, OR, NOR, XOR, XNOR, INV. Table 7-11 provides the truth table for a 4-bit LUT. www.ti.com TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TPLD1201

Table 7-11. 4-Bit LUT Truth Table IN3 IN2 IN1 IN0 OUT 0 0 0 0 User defined 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Each 4-bit LUT has 16 bits in the OTP to define their output function. When used to implement 8-bit counter/delay function, the two input signals from the connection mux go to the clock (CLK) and reset (RST/DLY IN) for the counter/delay macro-cell, with the output going back to the connection mux. As a counter, the macro-cell counts to the given data value and generates a pulse when it reaches the set value or is reset. As a delay, it postpones rising or falling edges for the duration that is a function of the register value. For more information on CNT/DLY macro-cell, see Section 7.3.4. 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY) The counters/delay generators are 8-bit, supporting counter data values from 1 to 255. For flexibility, the clock source for each of these macro-cells can be configured as the internal oscillator, a divided clock derived from an oscillator (OSC/4, /12, /24, /64, /4096), or an external clock source coming from the connection mux. There is also the option to chain from the output of the previous CNT/DLY macro-cell to implement longer counter/ delay circuits. Note that the counter/delay macro-cell is rising edge triggered, that is the counter will increment/ decrement on rising clock edges. DLY IN OUT 8-bit DLY0 RST OUT 8-bit CNT OSC Divided OSC Ext. CLK Prev. CNT CMX_OUT CMX_IN CLK SEL CMX_OUT CFG ... Figure 7-9. CNT/DLY Block Diagram TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 www.ti.com

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Ext. CLK Prev. CNT CMX_OUT CMX_IN CLK SEL EDGE DETECT CFG CMX_IN ... Figure 7-10. CNT/DLY3 Block Diagram As a counter/delay (CNT/DLY) macro-cell, users select from the following modes: delay, counter. CNT/DLY3, when in Delay mode, also has an optional edge detector that generates a short pulse on the specified edge in addition to the delayed output.

7.3.4.1 Delay Mode

When configured as a Delay generator (DLY), this macro-cell delays the input based on counter DATA and CLK input frequency and postpones rising and/or falling edges. The edge on which to delay is selected by the Edge select parameter and can be configured as:

• Rising: only delay on rising edges of IN.
• Falling: only delay on falling edges of IN.
• Both: delay on both rising and falling edges of IN. For delay applications, TI recommends to use larger counter data values for less error. If an input pulse width is shorter than the specified delay time, the pulse is filtered out. This feature can be useful for deglitching. If the on-chip oscillator is used, a delay error or offset is introduced depending on whether the OSC is set to "forced power on" or "auto power on". An additional 2 clock cycles are included in the delay calculation for clock synchronization. The delay time is calculated by: DEL AY = DATA + t d _ er or t d _ os + 2 ÷ f CL K (1) When the OSC is set to "auto power on" and DLY macro-cells are triggered subsequently before the previous output is present, the OSC continues to clock and the DLY begins on the next rising edge. Thus, the subsequent delays can be calculated as if the OSC are set to "forced power on". Figure 7-11 shows an example of the Delay macro-cell operation set to both edge delay and data = 1. www.ti.com TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TPLD1201

OSC (forced power on) OSC (auto power on) DLY OUT Divided OSC (auto power on) ttdt td_err ttdt ttdt td_os td_err td_os ttdt DLY OUT Figure 7-11. Delay Output Timing Example (Both Edge Delay and DATA = 1) Figure 7-12 shows an example timing of Delay macro-cells with respect to the edge selected and data = 3. IN CLK OUT (edge = rising) OUT (edge = falling) OUT (edge = both) t2 clk synct ttdt t2 clk synct ttdt Figure 7-12. Delay Output Timing Example (DATA = 3) TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 www.ti.com

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7.3.4.2 Edge Detector Mode

When CNT/DLY3 is configured as a Delay, this macro-cell has the option to generate a pulse of approximately 20ns width when a valid edge is detected. The edge on which the Edge detector generates a pulse is determined by the Edge select parameter and can be configured as:

• Rising: only rising edges of IN generate a pulse.
• Falling: only falling edges of IN generate a pulse.
• Both: both rising and falling edges of IN generate a pulse. The image below shows an example of how the EDET option operates with respect to the Edge select parameter. IN CLK OUT (edge = falling) OUT (edge = both) OUT (edge = rising) Figure 7-13. Edge Detector Output Timing Example

7.3.4.3 Reset Counter Mode

When configured as a Counter (CNT) and a valid edge appears on the IN input, this macro-cells resets the internal counter to 0 and begins counting down from DATA on the next rising clock edge. Then, the macro-cell outputs a pulse for the duration of one CLK period when the count reaches 0 and wrap around to the value in DATA. The counter will continually operate until another reset is received. The edge on which the Counter is reset is determined by the Edge select parameter and can be configured as:

• Rising: only rising edges of IN reset the counter.
• Falling: only falling edges of IN reset the counter.
• Both: both rising and falling edges of IN reset the counter.
• High Level Reset: the counter is reset to 0 whenever IN is High; after reset, the counter output stays Low until the next rising CLK edge, then operates normally. The counter time is calculated by: COUN T = DAT A + 1 ÷ f C LK (2) After a reset, an additional 2 clock cycles is added for clock synchronization. Note Counters are initialized with DATA = 0 after POR. Figure 7-14 and Figure 7-15 show examples of Counter output timing diagrams with respect to the Edge select parameter with DATA = 1 and DATA = 3, respectively. www.ti.com TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TPLD1201

(edge = rising) OUT (edge = falling) OUT (edge = both) OUT (edge = HLR) Figure 7-14. Counter Output Timing Example (DATA = 1) IN CLK OUT (edge = rising) OUT (edge = falling) OUT (edge = both) OUT (edge = HLR) Figure 7-15. Counter Output Timing Example (DATA = 3) Figure 7-16 shows an example of how the Counter macro-cell operates when the IN signal is shorter than the counter length (shown when edge select parameter is set to "both"). TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 www.ti.com

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(edge = rising) OUT (edge = falling) OUT (edge = both) OUT (edge = HLR) Figure 7-16. Counter Output Timing Example with RST < DATA (DATA = 3)

7.3.5 Programmable Deglitch Filter or Edge Detector Macro-Cell

The TPLD1201 has one macro-cell that can be configured as a programmable filter (PFLT) or edge detector (EDET). The PFLT macro-cell can be used to generate a delay (t pflt_d) characterized by t pflt_pw and t pflt_pd. tpflt_pw can be set to 125ns, 250ns, 375ns, or 500ns and t pflt_pd is a fixed value. Furthermore, the output of the macro-cell can be configured to one of four options: rising edge detection, falling edge detection, both edge detection, or both edge delay. Lastly, the filter operates as a short low-pass filter and its output can be set as non-inverted or inverted. CMX_OUT CMX_IN EDGE DETECT LOGIC Rise edge Fall edge Both edge CFG Programmable Filter R C R C R C R C CFG CFG Figure 7-17. Programmable Filter and Edge Detector Block Diagram Note The input signal must be longer than tpflt_d, otherwise it will be filtered out. www.ti.com TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TPLD1201

tpdly_pd tpdly_pw td Falling Edge Detect Both Edge Delay Both Edge Detect IN Rising Edge Detect td Figure 7-18. Programmable Filter and Edge Detector Output Timing Diagram Example

7.3.6 Selectable Frequency Oscillator

The TPLD1201 has one internal oscillator, selectable to operate at 25kHz or at 2MHz. The user can select one of these operating frequencies for the OSC macro-cell, or the internal oscillator could be bypassed and the operating frequency can come from an external clock. FREQ1 EXT FREQ FREQ0 to CNT/ DLY blocks CMX_IN CMX_IN CFG CFG Pre-Divider Block Output Divider Blocks CMX_OUT Output Divider Blocks Figure 7-19. Oscillator Block Diagram Following the operating clock input, there are two divider stages that allow users the flexibility of various clock frequencies for use throughout the device. The first stage divider allows the selection of up to four options from the operating oscillator frequency as listed in Oscillator Frequency Modes. The output of the first divider stage is routed directly to the counter/delay generator macro-cell CLK inputs, where a separate second divider stage is available. The output of the first divider stage is also routed into a second divider stage within the oscillator macro-cell. The oscillator macro-cell has two separate second stage dividers, allowing for the output of two separate clocks (OUT0 and OUT1) into the connection mux. See Oscillator Frequency Modes. TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 www.ti.com

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7.3.7 Analog Comparators (ACMP)

There are two analog comparator (ACMP) macro-cells in the TPLD1201. The analog comparator compares two voltages (IN+ and IN-) and outputs a digital signal (OUT) indicating which input is larger, a High signal for IN+ and a Low for IN-. GAIN SEL GAIN SEL VCC ACMP0 IN ACMP1 IN IN- SEL IN- SEL ACMP1 ACMP0 CFG CFG CMX_OUT VCC CMX_OUT CMX_IN CMX_IN 00h~17h 1Ah CFG CFG 18h 19h Internal VREF VCC/3 VCC/4 VREF IN IN- SEL to VREF to VREF GAIN SEL 0.5x 0.33x 0.25x Figure 7-20. ACMP Block Diagram For the ACMP macro-cell to operate, the power up signal (PWR UP) needs to be asserted high. By connecting to signals coming from the connection mux, it is possible to have each ACMP always on, always off, or switched on dynamically based on a digital signal coming from the connection mux. When powered down, the ACMP will output a low signal.

• PWR UP = 1: ACMP is powered up.
• PWR UP = 0: ACMP is powered down. Upon power-up, the ACMP output will remain low, and then become valid 100 μs (typical) after POR signal goes high. During this time, ensure the internal oscillator is not powered down. Each of the ACMP cells has a positive input signal that can be provided by a variety of external sources with a selectable gain stage before going into the analog comparator. ACMP1 also has a 100µA pullup current source option for external sensor excitation purposes. The negative input signal is either created from an internal VREF or from an external source. www.ti.com TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: TPLD1201

Table 7-12. ACMP0 and ACMP1 Input Sources Parameters ACMP0(1) ACMP1(2) IN+ source Analog Input 0 (shared with IO1) Analog Input 1 (shared with IO4) VCC ACMP0 IN+ IN- source 150mV 150mV 1200mV 1200mV VCC/3 VCC/3 VCC/4 VCC/4 VREF Analog Input (shared with IO2) VREF Analog Input (shared with IO2) (1) Positive Analog input source to ACMP. (2) Negative Analog input source to ACMP. Internal VREF thresholds are optimized near 1200mV. IN+ gain : Each of the ACMP cells has a positive input signal that can be provided by a variety of external sources, and can also have a selectable gain stage (1X, 0.5X, 0.33X, 0.25X) before connection to the analog comparator. IN- voltage range: 150mV to 1.2V through the internal VREF, VCC/3, VCC/4, or external source. Hysteresis: Each ACMP has four selectable hysteresis options 0mV, 25mV, 50mV and 200mV. The hysteresis is selectable if the internal VREF macro-cell or an external VREF input is used.

• 0mV: will disable the input signal hysteresis.
• 50mV: is a +25mV and -25mV hysteresis. For VREF = 1V, the trigger points will be 1.025V and 0.975V.
• 200mV: is a +100mV and -100mV hysteresis. For VREF = 1V, the trigger points will be 1.1V and 0.9V. If hysteresis is desired, ensure the hysteresis is less than the VREF, otherwise the negative trigger point will be pushed below device ground which may stress the device beyond the Recommended Operating Conditions and reduce the lifetime of the device. Low bandwidth: The ACMP cell has a selection for the bandwidth of the input signal, which can be used to save power and reduce noise impact when lower bandwidth signals are being compared. If VCC/3 and VCC/4 are not used at ACMP negative input, they can be disabled to reduce power consumption.

7.3.8 Voltage Reference (VREF)

The voltage reference (VREF) produces a fixed (constant) voltage, providing references to the analog comparators and external circuitry. The TPLD1201 has a voltage reference macro-cell to provide references to the two analog comparators. This macro-cell can supply a user selection of fixed voltage references, /2, /3 and /4 reference off of the V CC power supply to the device, and externally supplied voltage references from the VREF Analog Input (shared with IO4). The macro-cell also has the option to output a reference voltage on the VREF Analog Output (shared with IO7). TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 www.ti.com

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Figure 7-21. Voltage Reference Block Diagram If VCC/2, VCC/3, and VCC/4 are not used at VREF select, they can be disabled to reduce power consumption. Force bandgap on keeps the bandgap on while the chip is powered. Output active buffer parameter enables the active output buffer on VREF. Table 7-13. VREF Range VCC VREF Range 1.71V - 5.5V 150mV - 1.2V

7.4 Device Functional Modes

7.4.1 Power-On Reset

The TPLD1201 has a power-on reset (POR) macro-cell that provides correct device initialization and operation of all macro-cells in the device. The purpose of the POR circuit is to have consistent behavior and predictable results when the V CC power is first ramping to the device, and also while the V CC is falling during power-down. To accomplish this goal, the POR drives a defined sequence of internal events that trigger changes to the states of different macro-cells inside the device, and finally to the state of the I/O pins. The power-on Reset (POR) macro-cell produces a logic High signal as an output when the device power supply (VCC) rises to approximately VPORR and device completely starts up. All outputs are in high impedance state and chip starts loading data from OTP. The reset signal is released for internal macro-cells and all the registers are initialized to their default states. Figure 7-22 shows POR system generates a sequence of signals that enable certain macro-cells. www.ti.com TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: TPLD1201

– VCC OTP_POR OTP out GPI_POR LUT_POR CORE_POR POR out GPO_POR VPORR ttSUt Figure 7-22. POR Sequence As shown in Figure 7-22, after the VCC has start ramping up and crosses the VPORR threshold:

• First, the on-chip OTP memory is reset.
• Next, the device reads the data from OTP memory, and transfers this information to configure each macro- cell and the connection mux.
• The third stage resets the GPIOs that are configured as inputs and then enables them.
• After that, the LUTs are reset and become active. After LUTs, the delay cells, OSC, DFFs, latches and pipe delay are initialized.
• After all macro-cells are initialized, the internal POR signal generated by the POR macro-cell goes from low to high.
• The last portion of the device to be initialized are the output PINs, which transition from high impedance to active at this point. GPIO quick charge: There is an option to connect a 2k Ω resistor in parallel to any configured pull up/pull down resistors to help inputs get to the right voltage faster, especially if there is significant capacitance. The 10k Ω, 100kΩ and 1MΩ GPIO pull up/pull down resistors are not enabled until the POR sequence is completed. Initialization: All internal macro-cells are initialized to a low level by default. Starting from when V CC exceeds VPORR, macro-cells in the TPLD1201 are powered on and forced into a reset state. The VREF output pin driving signal can precede POR output signal going high by 3µs to 5µs. The POR signal going high indicates the mentioned power-up sequence is complete. TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 www.ti.com

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8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The configurable logic and timing blocks of TPLD1201 allow for the device to provide symmetric power-up and power-down signals for numerous components. In this application the device is configured to output the maximum amount of power- up and power-down sequencing signals based on a counter/delay macro-cell.

8.2 Typical Application

D CLK Q D CLK Q D CLK Q D CLK Q IN CLK OUT1 OUT0 NRST RST CLK OUT cnt dff dff dff dff pipedelay EN (IO) POW1 (IO) POW2 (IO) POW3 (IO) POW4 (IO) POW5 (IO)OUT por osc lut lut lut lut Figure 8-1. Typical Application Block Diagram

8.2.1 Design Requirements

8.2.1.1 Power Considerations

Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions . The supply voltage sets the device's electrical characteristics of the device as described in the Electrical Characteristics section. www.ti.com TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: TPLD1201

The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the TPLD1201 plus the maximum static supply current, ICC, listed in the Electrical Characteristics, and any transient current required for switching. The device can only source as much current that is provided by the positive supply source. Ensure the maximum total current through V CC listed in the Absolute Maximum Ratings is not exceeded. The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the TPLD1201 plus the maximum supply current, I CC, listed in the Electrical Characteristics , and any transient current required for switching. The logic device can only sink as much current that can be sunk into its ground connection. Ensure the maximum total current through GND listed in the Absolute Maximum Ratings is not exceeded. The TPLD1201 can drive a load with a total capacitance less than or equal to 15pF while still meeting all of the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to exceed 15pF. The TPLD1201 can drive a load with total resistance described by R L ≥ VO / I O, with the output voltage and current defined in the Electrical Characteristics table with VOH andVOL. When outputting in the HIGH state, the output voltage in the equation is defined as the difference between the measured output voltage and the supply voltage at the VCC pin. Total power consumption can be calculated using the information provided in CMOS Power Consumption and Cpd Calculation. Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices. CAUTION The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum Ratings. These limits are provided to prevent damage to the device. TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 www.ti.com

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8.2.1.2 Input Considerations

Input signals must cross VIL(max) or Vt-(min) to be considered a logic LOW, and VIH(min) or Vt+(max) to be considered a logic HIGH. Do not exceed the maximum input voltage range found in the Absolute Maximum Ratings. Unused inputs must be terminated to either V CC or ground. The unused inputs can be directly terminated if the input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used for a default state of LOW. The drive current of the controller, leakage current into the TPLD1201 (as specified in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10k Ω resistor value is often used due to these factors. The TPLD1201 has CMOS inputs and thus requires fast input transitions to operate correctly, as defined in the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power consumption, and reduction in device reliability. The TPLD1201 can be used with no signal transition rate requirements because it has Schmitt-Trigger inputs. Another benefit to having Schmitt-Trigger inputs is the ability to reject noise. Noise with a large enough amplitude can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical Characteristics. This hysteresis value will provide the peak-to-peak limit. Unlike what happens with standard CMOS inputs, Schmitt-Trigger inputs can be held at any valid value without causing huge increases in power consumption. The typical additional current caused by holding an input at a value other than VCC or ground is plotted in the Typical Characteristics. Refer to the Feature Description section for additional information regarding the inputs for this device.

8.2.1.3 Output Considerations

The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will decrease the output voltage as specified by the V OH specification in the Electrical Characteristics.The ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output voltage as specified by the VOL specification in the Electrical Characteristics. Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected directly together. This can cause excessive current and damage to the device. Two channels within the same device with the same input signals can be connected in parallel for additional output drive strength. Open-drain outputs can be connected together directly to produce a wired-AND configuration or for additional output drive strength. Unused outputs can be left floating. Do not connect outputs directly to VCC or ground. Refer to the Feature Description section for additional information regarding the outputs for this device.

8.2.2 Detailed Design Procedure

1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout section. 2. Verify that the capacitive load at the output is ≤ 50pF. Low load capacitance can be accomplished by providing short, appropriately sized traces from the TPLD1201 to the receiving device. 3. Verify that the resistive load at the output is larger than (VCC / IO(max))Ω. Never violate the maximum output current from the Absolute Maximum Ratings. Most CMOS inputs have a resistive load measured in MΩ; much larger than the minimum calculated previously. 4. Thermal issues are rarely a concern for logic gates; however, the power consumption and thermal increase can be calculated using the steps provided in the CMOS Power Consumption and Cpd Calculation application note. www.ti.com TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: TPLD1201

8.2.3 Application Curves

Figure 8-2. Application Timing Diagram

8.3 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions . Each V CC terminal must have a good bypass capacitor to prevent power disturbance. A 0.1 μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. The 0.1 μF and 1μF capacitors are commonly used in parallel. The bypass capacitor must be installed as close to the power terminal as possible for best results.

8.4 Layout

8.4.1 Layout Guidelines

When using multiple-input and multiple-channel logic devices, inputs must never be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or V CC, whichever makes more sense for the logic function or is more convenient. TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 www.ti.com

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8.4.2 Layout Example

≥ W W W ≥ 5W WORST BETTER BEST Figure 8-3. Example trace corners for improved signal integrity GND V CC GND VCC 0.1 F Figure 8-4. Example bypass capacitor placement for TSSOP and similar packages 0.1 F VCC GND 1 20 10 11 9 12 GNDVCC GND Figure 8-5. Example bypass capacitor placement for WQFN and similar packages GND GND VCC 0.1 F VCC Figure 8-6. Example bypass capacitor placement for SOT, SC70 and similar packages Long controlled-impedance trace Receiving PortTransmitting Port Figure 8-7. Example damping resistor placement for improved signal integrity www.ti.com TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: TPLD1201

9 Device and Documentation Support

9.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. Changes from Revision E (December 2025) to Revision F (April 2026) Page Changes from Revision D (August 2025) to Revision E (December 2025) Page

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TPLD1201 SCPS287F – NOVEMBER 2023 – REVISED APRIL 2026 www.ti.com

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www.ti.com 24-Jun-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPLD1201DGSR Active Production VSSOP (DGS) | 10 3000 | LARGE T&R - Call TI Level-1-260C-UNLIM -40 to 125 1201 TPLD1201RWBR Active Production X2QFN (RWB) | 12 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 QW TPLD1201RWBR.A Active Production X2QFN (RWB) | 12 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 QW TPLD1201RWSR Active Production X2QFN (RWS) | 12 3000 | LARGE T&R Yes Call TI Level-1-260C-UNLIM -40 to 125 TE (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPLD1201 : Addendum-Page 1

www.ti.com 24-Jun-2026

• Automotive : TPLD1201-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 1-Apr-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 1-Apr-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPLD1201DGSR VSSOP DGS 10 3000 353.0 353.0 32.0 TPLD1201RWBR X2QFN RWB 12 3000 210.0 185.0 35.0 TPLD1201RWSR X2QFN RWS 12 3000 210.0 185.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE 1.7 1.5 1.7 1.5 0.4 0.3 0.05 0.00 2X 1.2 6X 0.4 2X 0.4 8X 0.4 0.2 12X 0.25 0.15 4X 0.6 0.4 (0.127) TYP X2QFN - 0.4 mm max heightRWS0012A PLASTIC QUAD FLATPACK - NO LEAD 4231917/A 05/2025 0.05 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID (45 X0.1) SYMM SYMM 5 6 1112

0.07 C A B

0.05 C SCALE 8.000 AB C

www.ti.com EXAMPLE BOARD LAYOUT 8X (0.4) (R0.05) TYP

0.05 MAX

0.05 MIN

8X (0.5) 12X (0.2) (1.5) (1.3) 4X (0.7) X2QFN - 0.4 mm max heightRWS0012A PLASTIC QUAD FLATPACK - NO LEAD 4231917/A 05/2025 NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 40X SEE SOLDER MASK DETAIL 5 6 1112 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN 8X (0.5) 12X (0.2) 8X (0.4) (1.5) (1.3) (R0.05) TYP 4X (0.7) X2QFN - 0.4 mm max heightRWS0012A PLASTIC QUAD FLATPACK - NO LEAD 4231917/A 05/2025 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.1 MM THICK STENCIL SCALE: 40X SYMM SYMM 5 6 1112

www.ti.com PACKAGE OUTLINE C TYP5.05 4.75

1.1 MAX

8X 0.5 10X 0.27 0.17 0.15 0.05 TYP0.23 0.13 0 - 8 0.25 GAGE PLANE 0.7 0.4 A NOTE 3 3.1 2.9 B NOTE 4 3.1 2.9 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187, variation BA.

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 3.200

www.ti.com EXAMPLE BOARD LAYOUT (4.4) 10X (1.45) 10X (0.3) 8X (0.5) (R ) TYP 0.05 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 5 6 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (4.4) 8X (0.5) 10X (0.3) 10X (1.45) (R ) TYP0.05 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 5 6 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

www.ti.com PACKAGE OUTLINE C0.4 MAX 2X 1.2 0.4 6X 0.4 8X 0.4 0.2 12X 0.25 0.15 4X 0.6 0.4 0.05 0.00 B 1.65 1.55 A 1.65 1.55 (0.13) TYP X2QFN - 0.4 mm max heightRWB0012A PLASTIC QUAD FLATPACK - NO LEAD 4221631/B 07/2017 PIN 1 INDEX AREA SEATING PLANE 0.05 C

0.07 C B A

0.05 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. SYMM SYMM SCALE 6.500

www.ti.com EXAMPLE BOARD LAYOUT (R0.05) TYP 12X (0.2) 8X (0.5) (1.3) (1.5)2X (0.4) 4X (0.7) 6X (0.4) X2QFN - 0.4 mm max heightRWB0012A PLASTIC QUAD FLATPACK - NO LEAD 4221631/B 07/2017 SYMM 2 7 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:30X 3 6 NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 12X (0.2) 8X (0.5) 4X (0.67) 2X (0.4) (1.5) (1.3) 6X (0.4) (R0.05) TYP X2QFN - 0.4 mm max heightRWB0012A PLASTIC QUAD FLATPACK - NO LEAD 4221631/B 07/2017 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL PADS 1,2,7 & 8 96% PRINTED SOLDER COVERAGE BY AREA SCALE:50X 3 6 912 SYMM METAL

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