TNY380GN POWERINT

Document overview

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Technical content

www.powerint.com September 2012 Energy-Efficient, Off-Line Switcher With Enhanced Peak Power Performance Obsolete Product – Not Recommended for New Designs PI-4266-012009 D AC IN DC OUT TinySwitch-PK D S EN/UV BP/M Output Power Table Product3

230 VAC ± 15% 85-265 VAC

TNY375P/G/D4 8.5 W 15 W 16.5 W 6 W 11.5 W 12.5 W TNY376P/G/D4 10 W 19 W 22 W 7 W 15 W 17 W TNY377P/G 13 W 23.5 W 28 W 8 W 18 W 23 W TNY378P/G 16 W 28 W 34 W 10 W 21.5 W 27 W TNY379P/G 18 W 32 W 39 W 12 W 25 W 31 W TNY380P/G 20 W 36.5 W 45 W 14 W 28.5 W 35 W Table 1. Output Power Table.

  1. Minimum continuous power in a typical non-ventilated enclosed adapter
  2. Minimum continuous power in an open frame design (see Key Applications
  3. Packages: P: DIP-8C, G: SMD-8C, D: SO-8C. Lead free only. See Part Ordering
  4. See Key Application Considerations.
  • Simple ON/OFF control, no loop compensation needed
  • Unique Peak Mode feature extends power range without increasing transformer size
  • Maximum frequency and current limit boosted at peak loads
  • Selectable current limit through BP/M capacitor value
  • Higher current limit extends maximum power in open frame
  • Lower current limit improves efficiency in enclosed adapters
  • Allows optimum TinySwitch-PK choice by swapping devices with no other circuit redesign
  • Tight I2f parameter tolerance reduces system cost
  • Maximizes MOSFET and magnetics power delivery
  • ON time extension – typically extends low line regulation range/ hold-up time to reduce input bulk capacitance
  • Self-biased: no bias winding required for TNY375-376; winding required for TNY377-380
  • Frequency jittering reduces EMI filter costs
  • Optimized pin out eases pcb/external heat sinking
  • Quiet source-connected heat sink pins for low EMI Enhanced Safety and Reliability Features
  • Accurate hysteretic thermal shutdown with automatic recovery provides complete system level overload protection and eliminates need for manual reset
  • Auto-restart delivers <3% maximum power in short circuit and open loop fault conditions
  • Output overvoltage shutdown with optional Zener
  • Line undervoltage detect threshold set using a single resistor
  • Very low component count enhances reliability and enables single sided printed circuit board layout
  • High bandwidth provides fast turn on with no overshoot and excellent transient load response
  • Extended creepage between DRAIN and all other pins improves field reliability EcoSmart – Extremely Energy Efficient
  • Easily meets all global energy efficiency regulations
  • No-load <170 mW at 265 VAC without bias winding, <60 mW with bias winding
  • ON/OFF control provides constant efficiency down to very light loads – ideal for mandatory CEC efficiency regulations and 1 W PC standby requirements

Applications

  • Applications with high peak-to-continuous power demands – DVDs, PVRs, active speakers (e.g. PC audio), audio amplifiers, modems, photo printers
  • Applications with high power demands at startup (large output capacitance or motor loads) – PC standby, low voltage motor drives

Description

TinySwitch-PK incorporates a 700 V MOSFET, oscillator, high- voltage switched current source, current limit (user selectable), and thermal shutdown circuitry. A unique peak mode feature boosts current limit and frequency for peak load conditions. The boosted current limit provides the peak output power while the increased peak mode frequency ensures the transformer can be sized for continuous load conditions rather than peak power demands. Figure 1. Typical Peak Power Application.

  1. It is the connection point for an external bypass capacitor for

the internally generated 5.85 V supply.

  1. It is a mode selector for the current limit value, depending on
  2. It provides a shutdown function. When the current into the

connected from the BP/M pin to a bias winding supply.

1.0 V + V T

Figure 2 Functional Block Diagram. Figure 3. Pin Configuration.

threshold current is between 75 mA and 115 mA. high voltage power return and control circuit common. OFF control to regulate the output voltage. functional block diagram with the most important features. clock signal that indicates the beginning of each cycle. frequency jitter with an oscillator frequency of 264 kHz. beginning of each cycle on the rising edge of the clock signal. If high, the power MOSFET is turned on for that cycle (enabled). being required to wait for completion of the full period. adjusts the current limit level accordingly in discrete amounts. optocoupler that is usually connected to this pin. both high frequency decoupling and energy storage. no-load consumption to below 60 mW. Figure 4. Frequency Jitter.

output voltages are 3.3 V, 5 V, 12 V, and –12 V. optimizes both EMI and energy efficiency. energy efficiency requirements. EN55022 Class B conducted EMI limits. designer to select the current limit appropriate for the application.

  • Standard current limit is selected with a 0.1 mF BP/M pin capacitor and is the normal choice for typical applications.
  • When a 1 mF BP/M pin capacitor is used, the current limit is reduced, offering reduced RMS device currents and therefore improved efficiency, but at the expense of maximum power capability. This is ideal for thermally challenging designs where dissipation must be minimized.
  • When a 10 mF BP/M pin capacitor is used, the current limit is increased, extending the power capability for applications requiring higher peak power or continuous power where the thermal conditions allow. Further flexibility comes from the current limits between adjacent TinySwitch-PK family members being compatible. The reduced current limit of a given device is equal to the standard current limit of the next smaller device, and the increased current limit is equal to the standard current limit of the next larger device.

Figure 14. TNY376PN, Four Output, 7.5 W, 13 W Peak Universal Input Power Supply.

400 V C3

250 VAC

  1. The minimum DC input voltage is 100 V or higher for 85 VAC

be sized to meet these criteria for AC input designs.

  1. Minimum data sheet value of I
  2. Transformer primary inductance tolerance of ±10%.
  3. Reflected output voltage (V OR) of 135 V.
  4. Voltage only output of 12 V with an ultrafast PN rectifier diode.
  5. Continuous conduction mode operation with transient KP*
  6. Increased current limit is selected for peak and open frame
  7. The part is board mounted with SOURCE pins soldered to

G package and 100 °C for D packaged devices.

  1. Ambient temperature of 50 °C for open frame designs and

average) output power in two common thermal environments. Table 2. Peak Output Power Capability vs Current Limit Mode Selection.

11 V, 2%

Figure 15. Single 230 VAC Input 20 W Continuous and 45 W Peak Power Supply Using TNY380PN.

adjusted to compensate for variations in leakage inductance. Figure 15. The resistor in series with the OVP Zener also limits the maximum current into the BYPASS pin. high primary capacitance and increased losses that results. dielectric or construction such as the film foil or metallized foil type. capacitor to the area of copper connected to the SOURCE pins. device during common mode line surge events. the package directly between BP and SOURCE pins. presence of a UV resistor which may prevent correct start-up. flux suppliers guidance, specifically avoiding flux contamination. should be kept as small as possible. to act not only as a single point ground, but also as a heat sink. diodes, maximize the PCB area connected to the cathode.

between the negative terminals on the input filter capacitors. optocoupler to prevent noise pick up. increase high frequency radiated EMI. specifications are not exceeded under worst case conditions.

  1. Maximum drain voltage – Verify the V

650 V at highest input voltage and peak (overload) output

gives margin for design variation.

  1. Maximum drain current – At maximum ambient temperature,
  2. Thermal Check – At specified maximum output power,

Power Integrations web site: www.powerint.com. Figure 16. Layout Considerations for TinySwitch-PK Using P Package.

Rev. C 09/12 TNY375-380 www.powerint.com Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C See Figure 17 (Unless Otherwise Specified) Min Typ Max Units Control Functions Output Frequency See Note A fOSC State Machine at Highest Current Limit Level TJ = 25 °C Average 248 264 280 kHz pk-pk Jitter 16 fOSC-Low All Lower Current Limit Levels TJ = 25 °C Average 132 pk-pk Jitter 8 Maximum Duty Cycle DCMAX S1 Open 62 65 % EN/UV Pin Upper Turnoff Threshold Current I DIS -150 -115 -90 mA EN/UV Pin Voltage VEN IEN/UV = 25 mA 1.8 2.2 2.6 V IEN/UV = -25 mA 0.8 1.2 1.6 DRAIN Supply Current IS1 EN/UV Current > IDIS (MOSFET Not Switching) See Note B 290 mA IS2 EN/UV Open (MOSFET Switching at fOSC) See Note C TNY375 385 520 mA TNY376 460 600 TNY377 570 710 TNY378 740 900 TNY379 870 1060 TNY380 1100 1350 Absolute Maximum Ratings(1,4) (5) Operating Junction Temperature Notes: 1. All voltages referenced to SOURCE, T A = 25 °C. 2. Normally limited by internal circuitry. 3. 1/16 in. from case for 5 seconds. 4. Maximum ratings specified may be applied one at a time without causing permanent damage to the product. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect product reliability. 5. The peak DRAIN current is allowed while the DRAIN voltage is simultaneously less than 400 V. Thermal Impedance Thermal Impedance: P or G Package: D Package: Notes: 1. Measured on the SOURCE pin close to plastic interface. 2. Soldered to 0.36 sq. in. (232 mm 2), 2 oz. (610 g/m2) copper clad. 3. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.

Rev. C 09/12 TNY375-380 www.powerint.com Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C See Figure 17 (Unless Otherwise Specified) Min Typ Max Units Control Functions (cont.) BP/M Pin Charge Current ICH1 VBP/M = 0 V, TJ = 25 °C See Note D, E mA ICH2 VBP/M = 4 V, TJ = 25 °C See Note D, E BP/M Pin Voltage VBP/M See Note D 5.6 5.85 6.15 V BP/M Pin Voltage Hysteresis VBP/MH 0.80 0.95 1.20 V BP/M Pin Shunt Voltage V SHUNT IBP = 2 mA 6.0 6.4 6.7 V EN/UV Pin Line Under- voltage Threshold I LUV TJ = 25 °C 22.5 25 27.5 mA Circuit Protection Peak Current Limit (BP/M Capacitor = 0.1 mF) See Note E I LIMITPEAK di/dt = 72 mA/ms TJ = 25 °C See Note F TNY375P 330 355 380 mA TNY375G/D 330 355 387 di/dt = 91 mA/ms TJ = 25 °C See Note F TNY376P 423 455 487 TNY376G/D 423 455 496 di/dt = 117 mA/ms TJ = 25 °C See Note F TNY377P 544 585 626 TNY377G 544 585 638 di/dt = 143 mA/ms TJ = 25 °C See Note F TNY378P 665 715 765 TNY378G 665 715 779 di/dt = 169 mA/ms TJ = 25 °C See Note F TNY379P 786 845 904 TNY379G 786 845 921 di/dt = 195 mA/ms TJ = 25 °C See Note F TNY380P 907 975 1043 TNY380G 907 975 1063 Peak Current Limit (BP/M Capacitor = 1 mF) See Note E I LIMITPEAKred di/dt = 72 mA/ms TJ = 25 °C See Note F TNY375P 302 325 361 mA TNY375G/D 302 325 367 di/dt = 91 mA/ms TJ = 25 °C See Note F TNY376P 330 355 391 TNY376G/D 330 355 401 di/dt = 117 mA/ms TJ = 25 °C See Note F TNY377P 423 455 501 TNY377G 423 455 514 di/dt = 143 mA/ms TJ = 25 °C See Note F TNY378P 544 585 644 TNY378G 544 585 661 di/dt = 169 mA/ms TJ = 25 °C See Note F TNY379P 665 715 787 TNY379G TNY380GN 665 715 808 di/dt = 195 mA/ms TJ = 25 °C See Note F TNY380P TNY380G 786 845 930 786 845 955

Rev. C 09/12 TNY375-380 www.powerint.com Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C See Figure 17 (Unless Otherwise Specified) Min Typ Max Units Circuit Protection (cont.) Peak Current Limit (BP/M Capacitor = 10 mF) See Note E I LIMITPEAKinc di/dt = 72 mA/ms TJ = 25 °C See Note F TNY375P 349 375 413 mA TNY375G/D 349 375 424 di/dt = 91 mA/ms TJ = 25 °C See Note F TNY376P 465 500 550 TNY376G/D 465 500 565 di/dt = 117 mA/ms TJ = 25 °C See Note F TNY377P 665 715 787 TNY377G 665 715 808 di/dt = 143 mA/ms TJ = 25 °C See Note F TNY378P 786 845 930 TNY378G 786 845 955 di/dt = 169 mA/ms TJ = 25 °C See Note F TNY379P 907 975 1073 TNY379G 907 975 1102 di/dt = 195 mA/ms TJ = 25 °C See Note F TNY380P 1028 1105 1216 TNY380G 1028 1105 1249 Power Coefficient I2f I2f = ILIMITPEAK(TYP) 2 × fOSC(TYP) TJ = 25 °C BP/M Capacitor = 0.1 mF TNY375-380P 0.9 × I2f I2f 1.12 × I2f A2Hz TNY375-376D 0.9 × I2f I2f 1.16 × I2f TNY375-380G 0.9 × I2f I2f 1.16 × I2f I2f = ILIMITPEAKred(TYP) 2 × fOSC(TYP) TJ = 25 °C BP/M Capacitor = 1 mF TNY375-380P 0.9 × I2f I2f 1.16 × I2f TNY375-376D 0.9 × I2f I2f 1.20 × I2f TNY375-380G 0.9 × I2f I2f 1.20 × I2f I2f = ILIMITPEAKinc(TYP) 2 × fOSC(TYP) TJ = 25 °C BP/M Capacitor = 10 mF TNY375-380P 0.9 × I2f I2f 1.16 × I2f TNY375-376D 0.9 × I2f I2f 1.20 × I2f TNY375-380G 0.9 × I2f I2f 1.20 × I2f Initial Current Limit IINIT See Figure 20 TJ = 25 °C, See Note G 0.75 × ILIMIT(MIN) mA Leading Edge Blanking Time t LEB TJ = 25 °C See Note G TNY375-377 190 235 ns TNY378-380 145 190 Current Limit Delay tILD TJ = 25 °C See Note G, H 200 ns Thermal Shutdown Temperature T SD 135 142 150 °C Thermal Shutdown Hysteresis T SDH 75 °C BP/M Pin Shutdown Threshold Current I SD 4 7 9 mA BP/M Pin Power-Up Reset Threshold Voltage V BP/M(RESET) 1.6 2.6 3.6 V

Rev. C 09/12 TNY375-380 www.powerint.com Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C See Figure 17 (Unless Otherwise Specified) Min Typ Max Units Output ON-State Resistance RDS(ON) TNY375 ID = 28 mA TJ = 25 °C 19 22 W TJ = 100 °C 29 33 TNY376 ID = 35 mA TJ = 25 °C 14 16 TJ = 100 °C 21 24 TNY377 ID = 45 mA TJ = 25 °C 7.8 9.0 TJ = 100 °C 11.7 13.5 TNY378 ID = 55 mA TJ = 25 °C 5.2 6.0 TJ = 100 °C 7.8 9.0 TNY379 ID = 65 mA TJ = 25 °C 3.9 4.5 TJ = 100 °C 5.8 6.7 TNY380 ID = 75 mA TJ = 25 °C 2.6 3.0 TJ = 100 °C 3.9 4.5 OFF-State Drain Leakage Current IDSS1 VBP/M = 6.2 V VEN/UV = 0 V VDS = 560 V TJ = 125 °C See Note I TNY375-376 50 mA TNY377-378 100 TNY379-380 200 IDSS2 VBP/M = 6.2 V VEN/UV = 0 V VDS = 375 V, TJ = 50 °C See Note G, I Breakdown Voltage BVDSS VBP = 6.2 V, VEN/UV = 0 V, See Note J, TJ = 25 °C 700 V DRAIN Supply Voltage 50 V Auto-Restart ON-Time At f OSC tAR TJ = 25 °C See Note K 32 ms Auto-Restart Duty Cycle DC AR TJ = 25 °C 3 %

Rev. C 09/12 TNY375-380 www.powerint.com NOTES: A. For all BP/M pin capacitor values. B. IS1 is an accurate estimate of device controller current consumption at no-load, since operating frequency is so low under these conditions. Total device consumption at no-load is the sum of IS1 and IDSS2. C. Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the DRAIN. An alternative is to measure the BP/M pin current at 6.1 V. D. BP/M pin is not intended for sourcing supply current to external circuitry. E. To ensure correct current limit, it is recommended that nominal 0.1 mF / 1 mF / 10 mF capacitors are used. In addition, the BP/M capacitor value tolerance should be equal to or better than indicated below across the ambient temperature range of the target application. The minimum and maximum capacitor values are guaranteed by characterization. F. For current limit at other di/dt values, refer to Figure 24. Measurements made with device self-biased. G. This parameter is derived from characterization. H. This parameter is derived from the change in current limit measured at 1X and 4X of the di/dt shown in the I LIMIT specification. I. IDSS1 is the worst-case OFF state leakage specification at 80% of BVDSS and maximum operating junction temperature. IDSS2 is a typical specification under worst-case application conditions (rectified 265 VAC) for no-load consumption calculations. J. Breakdown voltage may be checked against minimum BVDSS specification by ramping the DRAIN pin voltage up to but not exceeding minimum BVDSS. K. Auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to frequency). Nominal BP/M Pin Cap Value Tolerance Relative to Nominal Capacitor Value Min Max 0.1 mF -60% +100% 1 mF -50% +100% 10 mF -50% NA

5 W S2

NOTE: This test circuit is not applicable for current limit or output characteristic measurements. Figure 17. General Test Circuit. Figure 18. Duty Cycle Measurement. Figure 19. Output Enable Timing. Figure 20. Current Limit Envelope at fOSC = 132 kHz.

Rev. C 09/12 TNY375-380 www.powerint.com Notes: 1. Package dimensions conform to JEDEC specification MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP) package with .300 inch row spacing. 2. Controlling dimensions are inches. Millimeter sizes are shown in parentheses. 3. Dimensions shown do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15) on any side. 4. Pin locations start with Pin 1, and continue counter-clock- wise to Pin 8 when viewed from the top. The notch and/or dimple are aids in locating Pin 1. Pin 3 is omitted. 5. Minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 6. Lead width measured at package body. 7. Lead spacing measured with the leads constrained to be perpendicular to plane T. .008 (.20) .015 (.38) .300 (7.62) BSC (NOTE 7) .300 (7.62) .390 (9.91) .367 (9.32) .387 (9.83) .240 (6.10) .260 (6.60) .125 (3.18) .145 (3.68) .057 (1.45) .068 (1.73) .120 (3.05) .140 (3.56) .015 (.38) MINIMUM .048 (1.22) .053 (1.35) .100 (2.54) BSC .014 (.36) .022 (.56) -E- Pin 1 SEATING PLANE -D- -T- P08C PDIP-8C (P Package) PI-3933-040110 D S .004 (.10) ⊕ T E D S .010 (.25) M ⊕ (NOTE 6) .137 (3.48) MINIMUM SMD-8C (G Package) PI-4015-101507 .004 (.10) .012 (.30) .036 (0.91) .044 (1.12) .004 (.10) 0 - ° 8 ° .367 (9.32) .387 (9.83) .032 (.81) .037 (.94) .125 (3.18) .145 (3.68) -D- Notes: 1. Controlling dimensions are inches. Millimeter sizes are shown in parentheses. 2. Dimensions shown do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15) on any side. 3. Pin locations start with Pin 1, and continue counter-clock- wise to Pin 8 when viewed from the top. Pin 3 is omitted. 4. Minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 5. Lead width measured at package body. 6. D and E are referenced datums on the package body. .057 (1.45) .068 (1.73) (NOTE 5) E S .100 (2.54) (BSC) -E- Pin 1 D S .004 (.10) ⊕ G08C .420 .046 .060 .060 .046 .080 Pin 1 .086 .186 .286 Solder Pad Dimensions .137 (3.48) MINIMUM

Rev. C 09/12 TNY375-380 www.powerint.com PI-4526-040110D07C 3.90 (0.154) BSC Notes: 1. JEDEC reference: MS-012. 2. Package outline exclusive of mold flash and metal burr. 3. Package outline inclusive of plating thickness. 4. Datums A and B to be determined at datum plane H. 5. Controlling dimensions are in millimeters. Inch dimensions are shown in parenthesis. Angles in degrees. 0.20 (0.008) C 1 4 2 6.00 (0.236) BSC D 4.90 (0.193) BSC 0.10 (0.004) C D 0.10 (0.004) C 2X A-B 1.27 (0.050) BSC 0.25 (0.010) M C A-B D 0.25 (0.010) 0.10 (0.004) (0.049 - 0.065) 1.25 - 1.65 1.75 (0.069) 1.35 (0.053) 0.10 (0.004) C C H o 1.27 (0.050) 0.40 (0.016) GAUGE PLANE 0 - 8 BSC SEATING PLANE 0.25 (0.010) 0.17 (0.007) DETAIL A DETAIL A C SEATING PLANE Pin 1 ID + + 4.90 (0.193) 2.00 (0.079) Reference Solder Pad Dimensions SO-8C (D Package) Part Ordering Information

  • TinySwitch Product Family
  • Series Number
  • Package Identifier G Plastic Surface Mount SMD-8C P Plastic DIP-8C D Plastic Surface Mount SO-8C
  • Lead Finish N Pure Matte Tin (Pb-Free) (Not available in D Package) G RoHS Compliant and Halogen Free (D Package only)
  • Tape & Reel and Other Options Blank Standard Configuration TL Tape & Reel, 1000 pcs min./mult., G Package, 2500 pcs min./mult., D PackageTNY 278 G N - TL

For the latest updates, visit our website: www.powerint.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. Life Support Policy POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. The PI logo, TOPSwitch, TinySwitch, LinkSwitch, LYTSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, LinkZero, HiperPFS, HiperTFS, HiperLCS, Qspeed, EcoSmart, Clampless, E-Shield, Filterfuse, StakFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2012, Power Integrations, Inc. Power Integrations Worldwide Sales Support Locations World Headquarters

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