TMG49037 OSRAM
Document overview
- Manufacturer or author: Provided By www.digicamel.com(free datasheet download site)
- PDF pages: 79
Technical content
[v1-01] 2019-Aug-20 Document Feedback TMG49037 Gesture, Color and Proximity Sensor Module The TMG49037 features gesture, ambient light and color (RGB) sensing and proximity. In addition, the device integrates an IR LED and advanced LED driver, all within a low-profile and small footprint, 2.0mm x 5.0mm x 1.0mm package. The Gesture and Proximity sens ing function synchronizes IR emission and detection to sense gesture and proximity events. The architecture of the engine features automatic high sample rate activation, self-maximizin g dynamic range, ambient light subtraction, advanced crosstalk cancelation, 14-bit data output, 32-dataset FIFO, and interrupt-driven I²C communication. Sensitivity, powe r consumption, and noise can be optimized with adjustable IR LED timing and power. The gesture engine is capable of 3D detection of motion and position. Gesture interrupts ar e configurable to reduce I²C communication load.The proximity engine recognizes detect/release events and produces a configurable interrupt whenever proximity result cro sses upper or lo wer threshold settings. The Ambient Light and Color Sensing function provides Red, Green, and Blue (RGB) ambien t light sensing with a Clear reference (C). The color diode array has a UV/IR blocking filter and parallel ADCs to produce simultaneous 16-bit results. This architecture accurately measures ambient light and enables the calculation of illuminance, chromaticity, and color temperature to manage display appearance. Ordering Information and Content Guide appear at end of datasheet. General Description
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − General Description Key Benefits & Features The benefits and features of TMG49037, Gesture, Color and Proximity Sensor Module are listed below: Figure 1: Added Value of Using TMG49037 Note(s): 1. While an object is detected , the sample rate increases autom atically to improve response. 2. Device sensitivity is automatically adjusted based on reflected response to support a wide detection distance.
Applications
The TMG49037 applic ations include:
- Gesture detection
- Color sensing
- Ambient light sensing
- Cell phone touch screen disable
- Mechanical switch replacement Benefit Feature
- 2D and 3D gesture and proximity detection
- Automatic sample rate adjustment (1)
- Self-maximizing dynamic range (2)
- 2D and 3D gesture detect
- Ambient light rejection
- Advanced crosstalk compensation
- AFE saturation flag
- Programmable LED driver
- Interrupt-driven I²C communication
- Ambient light and color sensing
- Variable sensitivity
- Designed to operate behind inked glass
- UV/IR blocking filter
- Programmable gain and integration time
- 6.7M:1 dynamic range by gain adjustment only
- Interrupt-driven I²C communication
- Integrated LED and driver • Calibrated emission and response
- Invisible 950nm emission
- Low supply voltage • 1.8V operation
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − General Description Block Diagram The functional blocks of this device are shown below: Figure 2: TMG49037 Block Diagram TMG4903 VDD VDD GND I2CSDA SCL OSCILLATOR Color ALS Red Green Blue Clear North South West East Gesture and Proximity Engine Pulse Control LEDA LDR
256 Byte FIFO
(2048 Bit Pattern RAM) Registers Digital Core INT Flags +Lim it -Lim it PROX +Lim it -Lim it CLEAR INT GPIO TMG49037
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Pin Assignment The device pin assignments are described below. Figure 3: Pin Diagram Pin Description Figure 4: Pin Description Pin Number Pin Name Description 1 VDD Supply voltage (1.8V)
2 SCL I²C serial clock terminal
3 GND Ground. All voltages are referenced to GND
4 LEDA LED anode
5 LDR LED driver (sinks current) and LED cathode (for direct access to LED)
6 GPIO Open drain output or alternate interrupt
7I N T Interrupt. Open drain output and logic level output for external IR LED circuit
8 SDA I²C serial data I/O terminal
R
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 5: Absolute Maximum Ratings Note(s): 1. All voltages with respect to GND 2. Measured with LDR = OFF or LDR = ON and LDRIVE = 310mA. Symbol Parameter Min Max Units Comments VDD Supply voltage -0.3 2.2 V VLEDA LED anode supply -0.3 3.6 V VIO Digital I/O terminal voltage -0.3 3.6 V VLDR Terminal voltage -0.3 3.6 V See note (2) IIO Output terminal current -1 20 mA Tstrg Storage temperature range -40 85 ºC ESDHBM ESD tolerance, human body model ±2000 V Absolute Maximum Ratings
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Electrical Characteristics Figure 8: ALS/Color Operating Characteristics, VDD = 1.8 V, T A = 25ºC, AGAIN = 16x, ATIME = 0xF6 (unless otherwise noted) Note(s): 1. Integration time is configured from 1 step (0xFF) to 256 st eps (0x00) for a typical range of 2.78ms to 711.11ms. An ATIME se tting of 0xFF results in a full-scale count value of 1024. Each additional integration step adds 1024 coun ts to full scale. To enable 16 -bit ADC range, 64 or more integration steps (177.8ms or more) are required (ATIME <= 0xC0). 2. The typical 3-sigma distribution is between 0 and 1 count for an AGAIN setting of 16x. 3. Lux accuracy is function of red, green, blue and clear channels, and not 100% production tested. 4. ADC noise is calculated as the standard deviation of 1000 data samples. Parameter Conditions Min Typ Max Units Integration time step size(1), (2) 2.68 2.78 2.90 ms Dark ADC count value (2) Ee = 0 μW/ cm2 AGAIN: 64x ATIME: 100ms (0xDC) 01 3 c o u n t s Gain scaling, relative to 16x gain setting AGAIN: 1/4x 0.0135 0.0175 x AGAIN: 1x 0.058 0.067 AGAIN: 4x 0.237 0.263 AGAIN: 64x 3.75 4.37 Clear channel irradiance responsivity White LED, 2700K 8.94 10.28 11.62 counts/ (μW/ cm2) Lux accuracy (3) White LED, 2700K 90 100 110 % ADC Noise (4) AGAIN: 16x 0.005 % Full Scale
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Electrical Characteristics Figure 9: Color Ratio Characteristics, VDD = 1.8V, T A = 25ºC Note(s): 1. The 465 nm input irradiance is supplied by an InGaN light-em itting diode with the following characteristics: dominant wavele ngth λD = 465 nm, spectral halfwidth Δλ½ = 22 nm. 2. The 525 nm input irradiance is supplied by an InGaN light-em itting diode with the following characteristics: dominant wavele ngth λD = 525 nm, spectral halfwidth Δλ½ = 35 nm. 3. The 615 nm input irradiance is supplied by an AlInGaP light- emitting diode with the following characteristics: dominant wave length λD = 615 nm, spectral halfwidth Δλ½ = 15 nm. Parameter Test Conditions Ratio of Color to Clear Channel Red Channel Green Channel Blue Channel Min Max Min Max Min Max Color ADC count value ratio: Color/Clear White LED, 2700 K 45% 65% 19% 39% 15% 40% λD = 465 nm (1) 0% 15% 10% 42% 70% 90% λD = 525 nm (2) 4% 25% 60% 85% 10% 45% λD = 615 nm (3) 80% 110% 0% 14% 5% 24%
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Electrical Characteristics Figure 10: Gesture and Proximity Operating Characteristics, VDD = 1.8 V, T A = 25ºC (unless otherwise noted) Note(s): 1. Offset varies with power supply characteristics and system noise. 2. Production tested result is the average of 5 readings expressed relative to a calibrated response. 3. Representative result by characterization . Device settings can vary from 1 to 64 pulse count, 4μs to 32μs pulse width, 10mA to 310mA current setting, and 1x to 8x electrical gain. Refer to Figure 21 for device performance with different settings. 4. Relative mismatch in the response between opposing channels. 5. Production tested result is the standard deviation of 20 readings as a percentage of full scale response. Parameter Conditions Min Typ Max Unit ADC conversion time step size 20 μs Offset (no target response) (1) PGAIN = 2 (4x) PGLDRIVE = 7 (150mA) PGPULSE_LEN = 1 (8μs) No target present After electrical calibration 16 36 counts Part to part variation (2) PGAIN = 2 (4x) PGLDRIVE = 1 (30mA) PGPULSE_LEN = 1 (8μs) d=23mm round target 30mm target distance After electrical calibration 75 100 125 % Response, absolute (3) PGAIN = 2 (4x) PGLDRIVE = 7 (150mA) PGPULSE_LEN = 1 (8μs) 100x100mm, 90% reflective Kodak gray card 100mm target distance After electrical calibration 670 840 1010 counts Photodiode relative deviation, north and south channels (4) -25 25 Photodiode relative deviation, east and west channels (4) -25 25 Noise/Signal (5) PGAIN = 2 (4x) PGLDRIVE = 2 (50mA) PGPULSE_LEN = 1 (8μs) PGPULSE = 7 (8 pulses)
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Typical Operating Characteristics Figure 23: Gesture Differential Note(s): 1. The East-West Response (%) is the same vs Target Angula r Direction when the target is rotated from East to West. -50% -40% -30% -20% -10% 10% 20% 30% 40% 50% -50 -40 -30 -20 -10 0 10 20 30 40 50 Target Angular Direction (degrees) Normalized Gesture Differential Rotate target from North to South North-South Response (%)
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − I²C Protocol The device uses I²C serial communication protocol for communication. The device support s 7-bit chip addressing and both standard and full-speed cl ock frequency modes. Read and Write transactions comply with th e standard set by Philips (now NXP). Internal to the device, an 8-bit buffer stores the register address location of the desired byte to read or write. This buffer auto-increments upon each byte transfer and is retained between transaction events (I.e. valid even after the master issues a STOP command and the I²C bus is released). During consecutive Read transactions, the future/repeated I²C Read transaction may omit the memory address byte normally following the chip address byte; the buffer retains the last register address +1. All 16-bit fields have a latching scheme for reading and writing. In general it is recommended to use I²C bursts whenever possible, especially in this ca se when accessing two bytes of one logical entity. When reading these fields, the low byte must be read first, and it triggers a 16-bit latch that stores the 16-bit field. The high byte must be read immediately afterwards. When writing to these fields, the low byte must be written first, immediately followed by the high byte. Reading or writing to these registers without following these requirements will cause errors. I²C Write Transaction A Write transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS WRITE, DATA BYTE(S), and STOP . Following each byte (9TH clock pulse) the slave places an ACKNOWLEDGE/NOT- ACKNOWLEDGE (ACK/NACK) on the bus. If NACK is transmitted by the slave, the master may issue a STOP . I²C Read Transaction A Read transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS, RESTART, CHIP-ADDRESSREAD, DATA BYTE(S), and STOP . Following all but the final byte the master places an ACK on the bus (9TH clock pulse). Termination of the Read transaction is indicated by a NACK being placed on the bus by the master, followed by STOP . The I²C bus protocol was develo ped by Philips (now NXP). For a complete description of the I²C protocol, please review the NXP I²C design specification. I²C Protocol
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − I²C Protocol Figure 24: Simplified State Diagram PARALLEL FUNCTIONS PEN AEN IDLE ALS/ COLOR GEST/PROX CALIBRATION GESTURE/ PROXIMITY I2C SLEEP PON I2C
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − I²C Protocol Figure 25: Detailed State Diagram ALS/COLOR CALIBRATION GEST/PROX GMODE INTERRUPT POR INITIALIZE (200 μs) PON = 1?SLEEPSAI = 1? EXIT SLEEPY IDLE AEN = 1AEN = 0 AUTOZERO (every nth time) INTEGRATE (ATIME)CRGB DATA WA IT (WTIME) I2C GENERATE INTERRUPT I2C UPDATE STATUS EVALUATE: INTERRUPT? N Y N Y N DONE CALIBRATE OFFSETS SET THRESHOLDS PEN | GEN = 1PEN & GEN = 0 ACCU MU LATE GDATA/PDATA WA IT (PTIME) GEN = 1 & PDATA > GENTH? ACCU MU LATEGDATA < GEXTH? GDATA/PDATAWA IT (GTIME) Y Y N N CLEAR INTERRUPTS TMG49037 Operational States
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Detailed Description Upon power-up, POR, the device init ializes. During initialization (typically 200μs), the device will deterministically send NAK on I²C and cannot accept I²C transactions. All communication with the device must be delayed, and all outputs from the device must be ignored including interr upts. After initialization, the device enters the SLEEP state. In this operational state the internal oscillator and other circ uitry are not active, resulting in ultra-low power consumption. If I²C transaction occurs during this state, the I²C core wake up temporarily to service the communication. Once the Power ON bit, PON, is enabled, the device enters the IDLE state in which the internal oscillator and attendant circuitry are active, but power consumption remains low. The first time the SLEEP state is exited and any functions are enabled (PEN | GEN | AEN = 1) an EXIT SLEEP pause occurs followed by an immediate entry into the selected engines. If all functions are disabled (PEN = 0 & AEN = 0), the device returns to the IDLE state. As depicted in Figure 24 and Figure 25 , the gesture/proximity and CRGB color sensing functions operate in parallel when enabled (PEN | GEN | AEN = 1). A simplified state diagram for each function is depicted in Figure 25 . Each function is individually configured (e.g. Gain, ADC integration time, wait time, persistence, thresholds, etc.). Sleep After Interrupt Operation If Sleep After Interrupt is enabled (SAI = 1), the state machine will enter SLEEP when non-gesture interrupts occur. However, for gesture, the state machine re mains in these active modes to continue to support these functions. Entering SLEEP does not automatically change any of the register settings (e.g. PON bit is still high, but the normal oper ational state is over-ridden by SLEEP state). SLEEP state is te rminated when the SAI bit is cleared. Detailed Description
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Register Description 0x98 GDATAL R Green ADC low data register 0x00 0x99 GDATAH R Green ADC high data register 0x00 0x9A BDATAL R Blue ADC low data register 0x00 0x9B BDATAH R Blue ADC high data register 0x00 0x9C PDATAL R Proximity ADC low data register 0x00 0x9D PDATAH R Proximity ADC high data register 0x00 0x9E STATUS2 R Additional device status 0x00 0x9F CFG2 R/W Configuration register two 0x04 0xAB CFG3 R/W Configuration register three 0x00 0xAC CFG4 R/W Configuration register four 0x07 0xAD CFG5 R/W Configuration register five 0x08 0xB0 GCFG0 R/W Gesture configuration register zero 0x00 0xB1 GCFG1 R/W Gesture configuration register one 0x8F 0xB2 GCFG2 R/W Gesture configuration register two 0x80 0xB3 STATUS3 R Status register three 0x00 0xB4 GTIME R/W Gesture time 0x0A 0xB5 GST_CTRL R/W Gesture control 0x00 0xB6 GTHR_INL R/W Gesture entry threshold low byte 0x00 0xB7 GTHR_INH R/W Gesture entry threshold high byte 0x00 0xB8 GTHR_OUTL R/W Gesture exit threshold low byte 0x00 0xB9 GTHR_OUTH R/W Gesture exit threshold high byte 0x00 0xBA GFIFO_LVL R Gesture FIFO entries waiting for readout 0x00 0xBB GSTATUS R Gesture status 0x00 0xBC CONTROL R/W Control register 0x00 0xBD AUXID R Auxiliary ID 0x00 0xC0 OFFSETNL R/W North channel offset low byte 0x00 0xC1 OFFSETNH R/W North channel offset high byte 0x00 0xC2 OFFSETSL R/W South channel offset low byte 0x00 0xC3 OFFSETSH R/W South channel offset high byte 0x00 0xC4 OFFSETWL R/W West channel offset low byte 0x00 Address Register Name R/W Register Function Reset Value
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Register Description 0xC5 OFFSETWH R/W West channel offset high byte 0x00 0xC6 OFFSETEL R/W East channel offset low byte 0x00 0xC7 OFFSETEH R/W East channel offset high byte 0x00 0xD0 PBSLN_MEASL R Measured baseline low byte 0x00 0xD1 PBSLN_MEASH R Measured baseline high byte 0x00 0xD2 PBSLNL R Stored baseline low byte 0x00 0xD3 PBSLNH R Stored baseline high byte 0x00 0xD6 AZ_CONFIG R/W Configure CRGB autozero frequency 0xFF 0xD7 CALIB R/W Start offset calibration 0x00 0xD8 CALIBCFG0 R/W Calibration configuration register zero 0x44 0xD9 CALIBCFG1 R/W Calibration configuration register one 0x0C 0xDA CALIBCFG2 R/W Calibration configuration register two 0x20 0xDB CALIBCFG3 R/W Calibration conf iguration register three 0x10 0xDC CALIBSTAT R/W Calibration status 0x00 0xDD INTENAB R/W Interrupt enable 0x00 0xDE INCLEAR R/W Interrupt clear 0x00 0xF8 GFIFO0L R Gesture FIFO North low byte 0x00 0xF9 GFIFO0H R Gesture FIFO North high byte 0x00 0xFA GFIFO1L R Gesture FIFO South low byte 0x00 0xFB GFIFO1H R Gesture FIFO South high byte 0x00 0xFC GFIFO2L R Gesture FIFO West low byte 0x00 0xFD GFIFO2H R Gesture FIFO West high byte 0x00 0xFE GFIFO3L R Gesture FIFO East low byte 0x00 0xFF GFIFO3H R Gesture FIFO East high byte 0x00 Address Register Name R/W Register Function Reset Value
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Register Description Enable Register (ENABLE 0x80) Enable has fields that power on the device and enable the functions. Before enabling any functions, all of the bits associated with each function mu st be set. Changing control register values while operating may result in invalid results. Figure 27: Enable Register 76543210 Reserved GEN PIEN AIEN WEN PEN AEN PON Field Bits Description Reserved 7 Reserved. GEN 6 Gesture Enable. When asserted, the gesture state machine can be activated by setting GMODE = 1 or when a proximity value is above the gesture entry threshold. PIEN 5 Proximity Interrupt Enable. When asserted permits proximity interrupts to be generated, subject to the proximity thresholds and persistence filter. AIEN 4 ALS Interrupt Enable. When asserted permits ALS interrupts to be generated, subject to the ALS thresholds and persistence filter. WEN 3 Wait Enable. This bit activates the wait feature. Writing a 1 activates the wait timer. Writing a 0 disables the wait timer. PEN 2 Proximity Enable. This bit activates the proximity function. Writing a 1 enables proximity. Writing a 0 disables proximity. AEN 1 ALS Enable. This bit activates the ALS/Color functionality. Writing a 1 enables ALS/Color. Writing a 0 disables ALS/Color. PON 0 Power ON. This bit activates the internal oscillator to permit the timers and ADC channels to operate. Writing a 1 activates the oscillator. Writing a 0 disables the oscillator and clears, PEN, and AEN. Only set this bit after all other registers have been initialized by the host.
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Register Description ALS Integration Time Register (ATIME 0x81) Figure 28: ALS Integration Time Register 76 5 4 3 2 10 ATIME Field Bits Description ATIME 7:0 ALS Integration Time. Sets the internal integration time of ALS/Color analog to digital converters in increments of 2.78ms. The power on reset value is 0xFF . The ADC maximum count (or saturation) value depends on the integration time. It is the lesser of either: 65535 (16-bit saturation) or The result of equation: Count MAX = 1024 X CYCLES VALUE INTEGRATION TIME MAX COUNTS 0xFF 2.78ms 1024 0xF6 27.8ms 10240 0xDC 100ms 36864 … 2.78ms X (256 - ATIME) … 0xC0 178ms 65535 0x00 711ms 65535
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Register Description Proximity Sample Time Register (PTIME 0x82) Figure 29: Proximity Sample Time Register 76 5 4 3 2 10 PTIME Field Bits Description PTIME 7:0 Proximity Sample Time. Sets the proximity sample rate. The power on reset value is 0x00. Proximity is executed once for each sample time. VALUE SAMPLE TIME FREQUENCY 0x00 2.78ms 360Hz 0x01 5.56ms 180Hz 0x03 11.1ms 90Hz 0x23 100ms 10Hz … 2.78ms X (PTIME +1) 1/Proximity Sample Time 0xFF 711ms 1.41Hz
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Register Description Wait Time Register (WTIME 0x83) Figure 30: Wait Time Register 76 5 4 3 2 10 WTIME Field Bits Description WTIME 7:0 Wait Time. Sets the wait time between ALS cycles. Wait mode reduces current consumption. It is set in 2.78ms increments unless the WLONG bit is asserted in which case the wait times are 12x longer. The power on reset value is 0xFF. Wait time should be configured before AEN is asserted. VALUE WAIT TIME (WLONG=0) WAIT TIME (WLONG=1) 0xFF 2.78ms 0.03s 0xDC 100ms 1.20s … 2.78ms X (256 - WTIME) 33.3ms X (256 - WTIME) 0x6A 417ms 5.00s 0x00 711ms 8.53s
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Register Description ALS Interrupt Threshol d Registers (0x84 – 0x87) ALS level detection uses data generated by the Clear Channel. The ALS Interrupt Threshold registers provide 16-bit values to be used as the high and low thresholds for comparison to the 16-bit CDATA values. If AIEN is enabled and CDATA is not between AILT and AIHT for the number of consecutive samples specified in APERS an interrupt is asserted on the interrupt pin. Figure 31: ALS Interrupt Threshold Registers Field Register Bits Description AILT 0x84 7:0 ALS low threshold low byte 0x85 15:8 ALS low threshold high byte AIHT 0x86 7:0 ALS high threshold low byte 0x87 15:8 ALS high threshold high byte
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Register Description Proximity Interrupt Threshold Registers (0x88 – 0x8B) The Proximity Interrupt Threshol d Registers set the high and low trigger points for the comp arison function which generates an interrupt. If PDATA, the value generated by proximity channel, crosses from above to below the lower threshold or from below to above the upper threshold, an interrupt may be signaled to the host processor. Interrupt generation is subject to the value set in persistence filter (PPERS). Figure 32: Proximity Interrupt Threshold Registers Field Register Bits Description PILT 0x88 7:0 Proximity low threshold low byte 0x89 15:8 Proximity low threshold high byte PIHT 0x8A 7:0 Proximity high threshold low byte 0x8B 15:8 Proximity high threshold high byte
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Register Description Interrupt Persistence Register (PERS 0x8C) Figure 33: Interrupt Persistence Register 7 6 543 21 0 PPERS APERS Field Bits Description PPERS 7:4 Proximity Interrupt Persistence. Defines a filter for the number of consecutive occurrences that PDATA must remain outside the threshold range between PILT and PIHT before an interrupt is generated. Any sample that is inside the threshold range resets the counter to 0. VALUE CONSECUTIVE OCCURENCES OUT OF RANGE
0 Every proximity cycle generates an interrupt
1 Generate interrupt after every occurrence. 2 Generate interrupt after 2 occurrences. ... Generate interrupt after PPERS occurrences. 15 Generate interrupt after 15 occurrences. APERS 3:0 ALS Interrupt Persistence. Defines a filter for the number of consecutive occurrences that CDATA must remain outside the threshold range between AILT and AIHT before an interrupt is generated. Any sample that is inside the threshold range resets the counter to 0. VALUE CONSECUTIVE OCCURENCES OUT OF RANGE
0 Every ALS cycle generates an interrupt
1 Generate interrupt after every occurrence. 2 Generate interrupt after 2 occurrences. 3 Generate interrupt after 3 occurrences. 4 Generate interrupt after 5 occurrences. 5 Generate interrupt after 10 occurrences. … Generate interrupt after 5 X (APERS -3) occurrences. 14 Generate interrupt after 55 occurrences. 15 Generate interrupt after 60 occurrences.
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Register Description Configuration Register Zero (CFG0 0x8D) Figure 34: Configuration Register Zero 76 5 4 3 2 1 0 Reserved LOWPOWER_IDLE Reserved WLONG Reserved Field Bits Description Reserved 7:6 Reserved. LOWPOWER_IDLE 5 Low Power Idle. When asserted, the device will run in a low power mode if all functions are in wait states or disabled. Reserved 4:3 Reserved. WLONG 2 Wait Long Enable. When asserted, the wait cycles are increased by a factor 12x. Reserved 1:0 Reserved.
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Register Description Proximity/Gesture Configuration Register Zero (PGCFG0 0x8E) PGCFG0 has fields that set the am ount of time the LED driver is sinking current during a proximity pulse and set the maximum number of pulses for each proximity sample. Figure 35: Proximity Configuration Register Zero 7 6 5 4 3 2 1 0 PGPULSE_LEN PPULSE Field Bits Description PGPULSE_LEN 7:6 Proximity Pulse Length. Sets the LED-ON pulse width during a Proximity pulse. VALUE LED ON 04 μ s 18 μ s 21 6 μ s 33 2 μ s PPULSE 5:0 Proximity Pulse Count. Specifies the maximum number of Proximity pulses to be generated on LDR. The pulse count can be set between 1 and 64 pulses. The number of pulses is equal to the PPULSE value plus 1.
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Register Description Proximity/Gesture Configuration Register One (PGCFG1 0x8F) PGCFG1 has fields that set the el ectrical gain of the proximity response and set the LED drive current during pulses. Figure 36: Proximity Configuration Register One 7 6 5 4 3 210 PGGAIN Reserved PGLDRIVE Reserved Field Bits Description PGGAIN 7:6 Proximity Gain Control. VALUE GAIN VALUE 0 1x Gain 1 2x Gain 2 4x Gain 3 8x Gain Reserved 5 Reserved. Bit must be set to 0. PGLDRIVE 4:1 Proximity LED Drive Strength. Configures nominal LED current linearly in steps of 20mA (actual current depends on factory-configuration of LED drive strength). VALUE LED STRENGTH 01 0 m A 13 0 m A 25 0 m A … 10mA + (20mA * PGLDRIVE) 14 290mA 15 310mA Reserved 0 Reserved. Bit must be set to 0.
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Register Description Configuration Register One (CFG1 0x90) CFG1 has fields that enable or disable the saturation interrupts for Proximity and ALS and set th e electrical gain of the ALS response. Figure 37: Configuration Register One 765 43 210 PGSIEN ASIEN Reserved AGAIN Field Bits Description PGSIEN 7 Proximity Saturation Interrupt Enable. When asserted permits proximity saturation interrupts to be generated. ASIEN 6 ALS Saturation Interrupt Enable. When asserted permits ALS saturation interrupts to be generated. Reserved 5:2 Reserved. Bits must be set to 0. AGAIN 1:0 ALS and Color Gain Control. FIELD VALUE CRGB GAIN VALUE 0 1x Gain 1 4x Gain 21 6 x G a i n 36 4 x G a i n
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Register Description Status Register (STATUS 0x93) The read-only Status Register provides the status of the device. Figure 40: Status Register 7 65 43 21 0 ASAT PGSAT PINT AINT Reserved GINT CINT Reserved Field Bits Description ASAT 7 ALS Saturation. If ASIEN is set, indicates ALS saturation. Check the STATUS2 register to differentiate between analog or digital saturation. PGSAT 6 Proximity/Gesture Saturation. If PGSIEN is set, indicates analog saturation during a previous proximity cycle. Check the STATUS2 register to differentiate between ambient or reflected light saturation. PINT 5 Proximity Interrupt. If PIEN is set, indicates that a proximity detect or release event that met the programmed proximity thresholds (PILT or PIHT) and persistence (PPERS) occurred. AINT 4 ALS Interrupt. If ASIEN is set, indicates that an ALS event that met the programmed ALS thresholds (AILT or AIHT) and persistence (APERS) occurred. Reserved 3 Reserved. GINT 2 Gesture Interrupt. If GIEN is set, indicates that one or more gesture event conditions have been met. GINT indicates that there is data available in the FIFO buffer for readout and GFIFO_LVL is greater than GFIFOTHR or that GVALID has become asserted when GMODE transitioned to zero. The bit is reset whenever the FIFO buffer is completely emptied (read). CINT 1 Calibration Interrupt. Indicates that either calibration is finished or that one of certain events have occurred during normal operation. If each function is enabled, CINT will be asserted if too many zeroes occur too often in a period of samples, if the proximity baseline has decreased, or if at least one offset register has been adjusted. Check the CALIBSTAT register to identify the triggering event(s). Reserved 0 Reserved.
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Register Description CRGB Data Registers (0x94 − 0x9B) Red, green, blue, and clear data are stored as 16-bit values. The read sequence must read byte pairs (low followed by high) starting on an even address boundary (0x94, 0x96, 0x98, or 0x9A) inside the CRGB Data Regist er block. In addition, reading the Clear channel data low byte (0x94) latches all 8 data bytes. Reading these 8 bytes consecutively (0x94 - 0x9A) ensures that the data is concurrent. Figure 41: CRGB Data Registers Field Register Bits Description CDATA 0x94 7:0 Clear channel data low byte 0x95 15:8 Clear channel data high byte RDATA 0x96 7:0 Red channel data low byte 0x97 15:8 Red channel data high byte GDATA 0x98 7:0 Green channel data low byte 0x99 15:8 Green channel data high byte BDATA 0x9A 7:0 Blue channel data low byte 0x9B 15:8 Blue channel data high byte
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Register Description Proximity Data Registers (0x9C – 0x9D) Proximity data is stored as a 14-bit value (two bytes). Proximity detection uses an Automatic Pulse Control (APC) mechanism that adjusts the number of pulses per measurement based on the magnitude of the reflected IR signal. As the magnitude of the signal increases, the number of pulses decreases. Proximity detection uses a 10-bit ADC that is extended to a 14-bit dynamic range for PDATA using the following formula: PDATA = ADC value x (16 / proximity pulses) PDATA is the average response of the non-masked proximity photodiodes. If one or more photodiodes are masked (CFG2 register 0x9F), the proximity response will remain the same since it is an average of the active photodiodes. PDATA is therefore proportional to the reflected energy per pulse, independent of the number of pulses used. Figure 42: Proximity Data Register Field Register Bits Description PDATA 0x9C 7:0 Proximity data low byte 0x9D 13:8 Proximity data high byte
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Register Description Status Register Two (STATUS2 0x9E) Figure 43: Status Register Two 7 6 5432 1 0 PVALID AVALID Reserved ASAT_ DIGITAL ASAT_ ANALOG PGSAT_ ADC PGSAT_ REFLECTIVE PGSAT_ AMBIENT Field Bits Description PVALID 7 Proximity Valid. Indicates that the ALS state has completed a cycle since either an assertion of PEN or the last readout of PDATA. AVALID 6 ALS Valid. Indicates that the proximity state has completed a cycle since either an assertion of AEN or the last readout of the CDATAL data register. Reserved 5 Reserved. ASAT_DIGITAL 4 ALS Digital Saturation. Indicates that the maximum counter value has been reached. Maximum counter value depends on integration time set in the ATIME register. ASAT_ANALOG 3 ALS Analog Saturation. Indicates that the intensity of ambient light has exceeded the maximum integration level for the ALS analog circuit. PGSAT_ADC 2 Proximity/Gesture ADC Saturation. Indicates that the maximum ADC value has occurred. PGSAT_REFLECTIVE 1 Proximity/Gesture Reflective Saturation. Indicates that the intensity of reflected light has exceeded the maximum integration level for the proximity analog circuit. PGSAT_AMBIENT 0 Proximity/Gesture Ambient Saturation. Indicates that the intensity of ambient light has exceeded the maximum integration level for the proximity analog circuit.
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Register Description Configuration Register Two (CFG2 0x9F) Figure 44: Configuration Register Two 7 6543210 PMASK_E PMASK_W PMASK_S PMASK_N AMASK Reserved Field Bits Description PMASK_E 7 Proximity Mask East. Writing a 1 disables the East photodiode. PMASK_W 6 Proximity Mask West. Writing a 1 disables the West photodiode. PMASK_S 5 Proximity Mask South. Writing a 1 disables the South photodiode. PMASK_N 4 Proximity Mask North. Writing a 1 disables the North photodiode. AMASK 3 ALS Mask. Writing a 1 reduces the ALS gain by a factor of the ALS photodiode pixels. Only the center 2x2 array of pixels remains enabled out of the 4x4 array. Reduces ALS sensitivity for measurement of maximum ambient light levels. Reserved 2:0 Reserved.
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Register Description Configuration Register Three (CFG3 0xAB) Figure 45: Configuration Register Three 76 5 4 3 2 1 0 Reserved LTF_USEPROX Reserved SAI Reserved Field Bits Description Reserved 7 Reserved. LTF_USEPROX 6 Use Proximity Photodiodes for ALS Measurement. Connects the IR-sensitive proximity/gesture photodiodes to the ALS engine in order to collect ALS data in the IR band. The data registers contain the following channel data depending on the LTF_USEPROX setting. 16-bit Output Registers L TF_USEPROX High Low 0 1 0x95 0x94 Clear North 0x97 0x96 Red South 0x99 0x98 Green West 0x9B 0x9A Blue East Reserved 5 Reserved. SAI 4 Sleep After Interrupt. Powers down the device at the end of a proximity/ALS cycle if an interrupt has been generated. Note that SAI does not modify any register bits directly, it rather uses the interrupt signal to turn off the oscillator. The only way to "wake up" the device from SAI-sleep is by clearing the SAI_ACTIVE flag. PON SAI INT (Low Active) Oscillator 0O f f
10 O n
1 1 0 Off (sleep after interrupt) Reserved 3:0 Reserved.
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Register Description Configuration Register Four (CFG4 0xAC) Figure 46: Configuration Register Four 76 5 4 3 2 1 0 ALS_INT_ DIRECT ALS_INT_ DIRECT_GPIO PROX_INT_ DIRECT PROX_INT_ DIRECT_GPIO Reserved Field Bits Description ALS_INT_DIRECT 7 ALS Interrupt Direct. If asserted, then the INT pin shows the ALS state directly and it is not necessary to clear the interrupt. If the CLEAR data exits the threshold range from within, the INT pin is asserted. The interrupt pin is de-asserted when the CLEAR data re-enters the threshold range. As long as the CLEAR data is within the thresholds, the INT pin is not asserted. ALS_INT_DIRECT_GPIO 6 ALS Interrupt Direct on GPIO Pin. If asserted, the GPIO pin shows the ALS interrupt state directly instead of the INT pin. This function operates in the same manner otherwise as ALS_INT_DIRECT. PROX_INT_DIRECT 5 Proximity Interrupt Direct. If asserted, then the INT pin shows the proximity state directly and it is not necessary to clear the interrupt. If PDATA crosses the upper threshold from below, the INT pin is asserted. The interrupt pin is only de-asserted when PDATA crosses the lower threshold from above. As long as PDATA is below the lower threshold, the INT pin is not asserted. PROX_INT_DIRECT_GPIO 4 Proximity Interrupt Direct on GPIO Pin. If asserted, the GPIO pin shows the proximity interrupt state directly instead of the INT pin. This function operates in the same manner otherwise as PROX_INT_DIRECT. Reserved 3:0 Reserved.
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Register Description Configuration Register Five (CFG5 0xAD) Figure 47: Configuration Register Five 76 5 4 3 2 1 0 Reserved LONG_LTFSTOP_ DISCARD_ALS Reserved DISABLE_IR_ CORRECTION PROX_FILTER_ DOWNSAMPLE PROX_FILTER_ SIZE PROX_ FILTER Field Bits Description Reserved 7:6 Reserved. LONG_LTFSTOP_DISCARD_ ALS 5 Long Disruption Discard ALS. Aborts ALS integration that is disrupted if the gesture state is entered (sensor field of view is obstructed). Immediately after gesture mode is exited, a new ALS integration is started. When restarting ALS, this function ignores wait configuration, which may cause more ALS measurements to occur than expected. Reserved 4 Reserved. DISABLE_IR_CORRECTION 3 Disable IR Correction. Default is 1. If bit is 0, then calculate IR=(R+G+B-C)/2 and store R'=R-IR, G' , B' , and C' in the color DATA registers. PROX_FILTER_ DOWNSAMPLE 2 Proximity Filter Downsample. If PROX_FILTER = 1, then, if asserted, PDATA and proximity interrupt check are performed only every n proximity samples. If not asserted, then proximity filtering uses a moving window: PDATA is updated every cycle and proximity interrupt is checked every cycle. PROX_FILTER_SIZE 1 Proximity Filter Size. Determines the number of consecutive proximity samples to average to filter out noise. VALUE FILTER 02 s a m p l e s PROX_FILTER 0 Proximity Filter. If asserted, enables proximity filter functionality. Depending on PROX_FILTER_SIZE, 2 or 4 consecutive proximity samples are averaged.
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Register Description Gesture Configuration Register Zero (GCFG0 0xB0) GCFG0 has fields that affect the exit of gesture mode, GMODE. Figure 48: Gesture Configuration Register Zero 76543 2 1 0 Reserved GTHR_MASK GTHR_OUT_NR Field Bits Description Reserved 7:6 Reserved. GTHR_MASK 5:2 Gesture Exit Mask. Controls which gesture channels will be compared to GTHR_OUT to exit gesture mode, GMODE. BIT EXIT MASK 5 Ignore E when exiting GMODE. 4 Ignore W when exiting GMODE. 3 Ignore S when exiting GMODE. 2 Ignore N when exiting GMODE. GTHR_OUT_NR 1:0 Gesture Exit Persistence. Defines how many consecutive times the gesture channel data must be below the gesture exit threshold, GTHR_OUT, for the device to exit gesture mode, GMODE. VALUE PERSISTENCE 0 Exit after first occurrence. 1 Exit after 2 consecutive occurrences. 2 Exit after 4 consecutive occurrences. 3 Exit after 8 consecutive occurrences.
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Register Description Gesture Configuration Register One (GCFG1 0xB1) Figure 49: Gesture Configuration Register One 76543 2 1 0 GFIFOTHR GPULSE Field Bits Description GFIFOTHR 7:6 Gesture FIFO Threshold. Defines the FIFO Level, the number of NSWE datasets, required to generate an interrupt (if enabled). VALUE FIFO LEVEL FOR INTERRUPT 31 6 GPULSE 5:0 Maximum Gesture Pulse Count. Specifies the maximum number of pulses to be generated for each gesture dataset. The maximum number of pulses is calculated as follows: n Pulses = GPULSE + 1
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Register Description Gesture Configuration Register Two (GCFG2 0xB2) Figure 50: Gesture Configuration Register Two 7 6 5 4 3 210 Reserved GEST_FILTER_SIZE GEST_FILTER Reserved Field Bits Description Reserved 7:6 Reserved. GEST_FILTER_SIZE 5 Proximity Filter Size. Determines the number of consecutive gesture samples to average to filter out noise. VALUE FILTER 02 s a m p l e s 14 s a m p l e s GEST_FILTER 4 Gesture Filter. If asserted, enables gesture filter functionality. Depending on GEST_FILTER_SIZE, 2 or 4 consecutive gesture samples are averaged. A moving window is used and gesture data is added to the buffer at every cycle. Reserved 3:0 Reserved.
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Register Description Proximity/Gesture Offset Registers (0xC0 − 0xC7) Proximity/gesture offset values have a range of ±255 and are expressed as 9-bit two’s-complement values. Do not program values outside of this range. Only the lower 9 bits are significant, but the high byte must only be programmed with values of 0x00 (indicates that the low byte has a positive value) or 0xFF (indicates that the low byte has a negative value). Figure 59: Proximity/Gesture Offset Registers Field Register Bits Description OFFSETN 0xC0 7:0 North channel offset low byte 0xC1 15:8 North channel offset high byte OFFSETS 0xC2 7:0 South channel offset low byte 0xC3 15:8 South channel offset high byte OFFSETW 0xC4 7:0 West channel offset low byte 0xC5 15:8 West channel offset high byte OFFSETE 0xC6 7:0 East channel offset low byte 0xC7 15:8 East channel offset high byte
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Register Description Proximity/Gesture Ba seline Registers (0xD0 − 0xD3) After proximity/gesture calibration is complete, the user may define a number of consecutiv e proximity cycles for which PDATA is averaged. The number of consecutive PDATA cycles to be averaged is defined by PXDCAVG_BASELINE_WINDOW (0xD9[2:0]). Averaging will repeat after every window of PDATA cycles. The latest averaged result is stored in the PBSLN_MEAS field. The second proximity baseline field, PBSLN, is first updated at the end of proximity/gesture cali bration. This value does not change unless the user se ts. PXDCAVG_AUTO_BASELINE (0xD9[3]) to 1. If asserted, PBSLN will be updated with the value of PBSLN_MEAS whenever PBSLN_MEAS is less than PBSLN. In addition, a multiple of PBSLN is used at the end of the calibration routine to set the gesture entry and exit thresholds if the user sets. PXDCAVG_AUTO_G THR field (0xD9[7]) to 1. The multiplication factor for setting the entry and exit thresholds is user-defined in the AUTO_GTHR_IN_MULT (0xDA[3:0]). Figure 60: Proximity/Gesture Baseline Registers Field Register Bits Description PBSLN_MEAS 0xD0 7:0 Measured baseline low byte 0xD1 15:8 Measured baseline high byte PBSLN 0xD2 7:0 Stored baseline low byte 0xD3 15:8 Stored baseline high byte
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Register Description Autozero Configuration Register (AZ_CONFIG 0xD6) Figure 61: Autozero Configuration Register 76 5 4 3 2 10 AZ_NTH_ITERATION Field Bits Description AZ_NTH_ITERATION 7:0 ALS Autozero Frequency. Sets the frequency at which the device performs autozero of the ALS pulse counter. VALUE AUTOZERO FREQUENCY
0 Never
…E v e r y (AZ_NTH_ITERATION) cycles
253 Every 253 cycles
254 Every 254 cycles
255 Only once (before 1
st cycle)
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Register Description Calibration Register (CALIB 0xD7) Figure 62: Calibration Register 765 4 32 1 0 Reserved START_OFFSET_CALIB Field Bits Description Reserved 7:1 Reserved. START_OFFSET_ CALIB 0 Start Offset Calibration. Starts the proximity/gesture offset register calibration routine. Results are stored in the Proximity/Gesture Offset Registers (0xC0 – 0xC7). The CALIB_FINISHED flag is asserted when calibration is complete and an interrupt (CINT) is asserted if CIEN is set. Calibration can be stopped by writing a 0 to this field.
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Register Description Calibration Configuration Register Zero (CALIBCFG0 0xD8) Figure 63: Calibration Configuration Register Zero 76 5 43 2 1 0 Reserved DCAVG_ AUTO_OFFSET_ ADJUST Reserved ELECTRICAL_ CALIBRATION BINSRCH_ SKIP DCAVG_ITERATIONS Field Bits Description Reserved 7 Reserved. DCAVG_AUTO_OFFSET_ADJUST 6 DC Averaging Auto Offset Adjust. If set, then during DC averaging, whenever an ADC measurement is zero, the appropriate offset register will be decreased and the OFFSET_ADJUSTED flag is set. Note also that DC averaging is not automatically restarted when this happens, so the calculated baseline might be wrong. Software could restart averaging in this case. Reserved 5 Reserved. ELECTRICAL_CALIBRATION 4 Enable Electrical Calibration. When asserted the calibration routine will perform an internal electrical calibration to adjust the proximity offset registers to remove electrical crosstalk – there is no optical response at all for this routine. When not asserted, calibration will measure both optical and electrical crosstalk during calibration. BINSRCH_SKIP 3 Binary Search Skip. When asserted the calibration routine will skip the binary search step. It is useful if zeroes are detected during the DC averaging process to manually reset the baseline and reduce the likelihood of zero counts.
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Register Description DCAVG_ITERATIONS 2:0 DC Averaging Iterations. Sets the number of proximity results during calibration that are averaged after the binary search is complete. During this period, whenever a result is zero, the appropriate offset register is automatically decremented. The default value is 4 (16 iterations). VALUE SAMPLES 0S k i p … n Iterations = 2DCAVG_ITERATIONS 66 4 71 2 8 Field Bits Description
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Register Description Calibration Configuration Register One (CALIBCFG1 0xD9) Figure 64: Calibration Configuration Register One 76 5 4 3 2 1 0 PXDCAVG_ AUTO_ GTHR PROX_ AUTO_OFFSET_ ADJUST Reserved PXDCAVG_ AUTO_ BASELINE PXDCAVG_BASELINE_WINDOW Field Bits Description PXDCAVG_AUTO_GTHR 7 Proximity Automatic Thresholds. When asserted, GTHR_IN and GTHR_OUT are automatically written with a multiple of the PBSLN every time PBSLN changes. The multiplication factor is set in AUTO_GTHR_IN_MULT. PBSLN can only change if PXDCAVG_AUTO_BASELINE is asserted and PBSLN_MEAS is less than PBSLN. PROX_AUTO_OFFSET_ADJUST 6 Proximity Auto Offset Adjust. If set, then during proximity/gesture mode, whenever an ADC measurement is zero, the appropriate offset register will be decreased. Will set the OFFSET_ADJUSTED flag if it happens. Reserved 5:4 Reserved. PXDCAVG_AUTO_BASELINE 3 Proximity Automatic Baseline. When asserted, PBSLN_MEAS is written to PBSLN whenever PBSLN_MEAS is less than PBSLN. When this happens, the BASELINE_ ADJUSTED flag is raised. The default value is 1. PXDCAVG_BASELINE_WINDOW 2:0 Prox Baseline Averaging Window. Sets the number of proximity samples averaged to calculate PBSLN_MEAS, which is updated at the end of each window. The default value is 16 samples. VALUE SAMPLES 0S k i p 66 4 71 2 8
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Register Description Calibration Configuration Register Two (CALIBCFG2 0xDA) Figure 65: Calibration Configuration Register Two 7 6543210 DCAVG_ AUTO_GTHR BINSRCH_TARGET AUTO_GTHR_IN_MULT Field Bits Description DCAVG_AUTO_GTHR 7 DC Averaging Automatic Thresholds. When asserted, GTHR_IN and GTHR_OUT are automatically written with a multiple of the PBSLN at the end of the calibration routine. The multiplication factor is set in AUTO_GTHR_IN_MULT. BINSRCH_TARGET 6:4 Binary Search Target. Sets the ADC target for proximity/gesture calibration. The default value is 2. VALUE SEARCH TARGET 66 3 71 2 7 AUTO_GTHR_IN_MULT 3:0 Automatic Gesture Threshold Multiplier. Sets the multiplication factor used if the gesture entry and exit thresholds are automatically calculated as a multiple of PBSLN. The default value is 0, but the recommended value is 8 (3x factor). VALUE MULTIPLIER 01 . 0 0 11 . 2 5 21 . 5 0 14 4.50 15 4.75
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Register Description Calibration Configuration Register Three (CALIBCFG3 0xDB) Figure 66: Calibration Configuration Register Three 76543210 Reserved ZERO_WEIGHT Field Bits Description ZERO_WEIGHT 3:0 Zero Detection Weighting Filter. Sets the frequency of detection of zeroes necessary to raise the ZERO_DETECTED flag. ZERO_WEIGHT should only be used if DCAVG_AUTO_OFFSET_ADJUST and PROX_AUTO_OFFSET_ADJUST are NOT used, in other words, when offset adjustments are handled only by software. If the automatic on-chip adjustments are made, ZERO_WEIGHT has no purpose. ZERO_DETECTED is raised when an internal counter reaches a value of 15. During normal proximity/gesture operation, if any of the ADC values on the four channels is zero, the counter increments by ZERO_WEIGHT. Every time there are no zeroes, it decrements by 1. At each weight, there is an equilibrium frequency that will rarely raise the ZERO_DETECTED flag. For example, if ZERO_WEIGHT is set to 3, zero detection will be at equilibrium if there are 3 non-zero cycles for every 1 zero cycle, a 25% frequency of zeroes. Even at equilibrium, there is a chance that enough zeroes will occur in a short period of time to raise the ZERO_DETECTED flag. For each weighting, there is a never flag frequency below which it is exceedingly unlikely that the flag will be raised. VALUE WEIGHT EQUILIBRIUM FREQUENCY NEVER FLAG FREQUENCY 0 0 Never (Ignored) Never (Ignored) 1 1 50% 35% 2 2 33% 16% 33 2 5 % 8 % 44 2 0 % 4 % 55 1 7 % 2 %
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Register Description Calibration Status Register (CALIBSTAT 0xDC) Figure 67: Calibration Status Register 7654 3 2 1 0 Reserved ZERO_ DETECTED BASELINE_ ADJUSTED OFFSET_ ADJUSTED CALIB_ FINISHED Field Bits Description Reserved 7:4 Reserved. ZERO_DETECTED 3 Zero Detected. Indicates that zeroes are being detected in proximity or gesture often enough to exceed the ZERO_WEIGHT conditions. Recalibration is recommended. Bit generates interrupt if CIEN is asserted. To prevent interrupt, set ZERO_WEIGHT to zero. Clear this bit by writing ‘1’ to it. BASELINE_ADJUSTED 2 Proximity/Gesture Baseline Adjusted. Indicates that the proximity baseline, PBSLN, has changed. This may occur in two ways: During DC averaging at calibration, if DCAVG_AUTO_BASELINE is asserted (independent of actual value). During regular proximity/gesture operation if DCAVG_AUTO_BASELINE is set and a new PBSLN_MEAS value is collected that is lower than previous PBSLN). Bit generates interrupt if CIEN is asserted. To prevent interrupt, set DCAVG_AUTO_BASELINE and PXDCAVG_AUTO_BASELINE to zero. Clear bit by writing '1' to it or by writing '1' to INTCLEAR_CINT. OFFSET_ADJUSTED 1 Proximity/Gesture Offset Adjusted. Indicates that one or more proximity/gesture offset register values were automatically adjusted. Bit generates interrupt if CIEN is asserted. To prevent interrupt, set DCAVG_AUTO_OFFSET_ADJUST and PROX_AUTO_OFFSET_ADJUST to zero. Clear bit by writing '1' to it. CALIB_FINISHED 0 Calibration Finished. Indicates that calibration is complete. Bit generates interrupt if CIEN is asserted. Clear bit by writing '1' to it.
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Register Description Interrupt Enable Regi ster (INTENAB 0xDD) Figure 68: Interrupt Enable Register 7654321 0 ASIEN PGSIEN PIEN AIEN Reserved GIEN CIEN Reserved Field Bits Description ASIEN 7 ALS Saturation Interrupt Enable. When asserted permits ALS saturation interrupts to be generated. Bit is mirrored in the CFG1 register. PGSIEN 6 Proximity Saturation Interrupt Enable. When asserted permits proximity saturation interrupts to be generated. Bit is mirrored in the CFG1 register. PIEN 5 Proximity Interrupt Enable. When asserted permits proximity interrupts to be generated, subject to the proximity thresholds and persistence filter. Bit is mirrored in the ENABLE register. AIEN 4 ALS Interrupt Enable. When asserted permits ALS interrupts to be generated, subject to the ALS thresholds and persistence filter. Bit is mirrored in the ENABLE register. Reserved 3 Reserved. GIEN 2 Gesture Interrupt Enable. When asserted permits all gesture-related interrupts to occur. The first gesture interrupt is subject to GFIFOTHR. Bit is mirrored in the GST_CTRL register. CIEN 1 Calibration Interrupt Enable. When asserted permits calibration interrupts to be generated. Reserved 0 Reserved.
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Register Description Interrupt Clear Register (INTCLEAR 0xDE) Figure 69: Interrupt Clear Register 7654 3 2 1 0 INTCLEAR_ ASAT INTCLEAR_ PGSAT INTCLEAR_ PINT INTCLEAR_ AINT Reserved INTCLEAR_ GINT INTCLEAR_ CINT Reserved Field Bits Description INTCLEAR_ASAT 7 Clear Interrupt: Analog Saturation. Clears the analog saturation interrupt. INTCLEAR_PGSAT 6 Clear Interrupt: Proximity Saturation. Clears the proximity saturation interrupt. INTCLEAR_PINT 5 Clear Interrupt: Proximity. Clears the proximity interrupt. INTCLEAR_AINT 4 Clear Interrupt: ALS. Clears the ALS interrupt. Reserved 3 Reserved. INTCLEAR_GINT 2 Clear Interrupt: Gesture. Must be used to clear the gesture interrupt after device exits GMODE and GVALID is asserted. If there is a gesture interrupt because the gesture FIFO level (GFIFO_LVL) is above the gesture FIFO threshold (GFIFOTHR), INTCLEAR_GINT will not clear the interrupt. To clear the gesture interrupt in this case, the data in the FIFO must be read. INTCLEAR_CINT 1 Clear Interrupt: Calibration. Clears the calibration interrupt. Reserved 0 Reserved.
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Register Description Gesture FIFO Access Registers (0xF8 − 0xFF) Gesture data is stored in a 256 byte FIFO buffer containing 32 eight byte datasets. Each dataset contains one sample each of North, South, West, & East gesture data. If the FIFO overflows (i.e. 33 datasets before host/system reads data from the FIFO buffer), an overflow flag will be set and new data will be lost. Host/Systems acquire gesture data by reading addresses: 0xF8 – 0xFF, which directly correspond to North, South, West, and East data points. The regist er address pointer automatically wraps from 0xFF to 0xF8. Data can be read one byte at a time (eight consecutive I²C transactions) or in blocks (there is no block-read length limit). When reading single bytes, the internal FIFO read pointer and the Gesture FIFO Buffer Level, GFIFO_LVL, are updated each time register 0xFF is read. For block-reads, the internal FIFO read pointer and the Gesture FIFO Buffer Level, GFIFO_LVL update for each eight byte dataset. If the FIFO continues to be acce ssed after GFIFO_LVL = 0, the device will return 0 for all data. Gesture interrupts and the gestur e valid (GVALID) flag indicate when there is valid data in the FIFO buffer. When the Gesture FIFO Buffer Level exceeds the Gesture Entry Threshold (GFIFO_LVL > GTHR_IN), a gesture interrupt is generated, and the GVALID flag is raised. Reading any data will clear the gesture interrupt, but GVALID will remain raised. A second interrupt is generated when the gesture is complete (GTHR_OUT conditions are met). The GVALID flag will remain raised until all data has been read, clearing th e FIFO buffer. Once the FIFO buffer is empty, GVALID will be cleared to indicate that the gesture is complete and all data is read. The amount of unread data is indicated by the GFIFO_LVL.
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Register Description Figure 70: Gesture FIFO Access Registers Field Register Bits Description GFIFO_N 0xF8 7:0 Gesture North FIFO low byte 0xF9 15:8 Gesture North FIFO high byte GFIFO_S 0xFA 7:0 Gesture South FIFO low byte 0xFB 15:8 Gesture South FIFO high byte GFIFO_W 0xFC 7:0 Gesture West FIFO low byte 0xFD 15:8 Gesture West FIFO high byte GFIFO_E 0xFE 7:0 Gesture East FIFO low byte 0xFF 15:8 Gesture East FIFO high byte
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Application Information The typical application hardware circuit of this device is shown below. Figure 71: TMG49037 Typical Application Circuit
Application Information
/g100/g68/g39/g1008/g1013/g454/g454 /g1005 /g1006 /g1007 /g1008 /g1009 VDD GND LEDA INT SCL SDA /g1011 /g1012 LDR4.7µF 1µF >4.7µF 22/g525 VDDVBUS /g1010GPIO VDD VLED VLED
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Application Information Figure 72: TMG49037 Recommended Circuit Layout
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Package Drawings & Markings Figure 73: TMG49037 Module Dimensions Note(s): 1. Package type: oLGA8 2. All linear dimensions are in millimeters. 3. Dimension tolerances are ±0.05mm unless otherwise noted. 4. Contacts are copper with NiPdAu plating. 5. This package contains no lead (Pb). 6. This drawing is subject to change without notice. 7. Measurement guarantee by lot a cceptance testing using 20 units. Package Drawings & Markings Green RoHS '(7(&725 /(' 7239,(: 3,1 6,'(9,(: ; ; %277209,(:
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − PCB Pad Layout Suggested PCB pad layout guidelines for the surface mount module are shown. Flash Gold is recommended as a surface finish for the landing pads. Figure 74: Recommended PCB Pad Layout Note(s): 1. All linear dimensions are in millimeters. 2. Dimension tolerances are ±0 .05mm unless otherwise noted. 3. This drawing is subject to change without notice. PCB Pad Layout
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Mechanical Data Figure 75: Tape and Reel Mechanical Drawing Note(s): 1. All linear dimensions are in millimeters. Dime nsion tolerance is ± 0.10 mm unless otherwise noted. 2. The dimensions on this drawing are for illustrative purpos es only. Dimensions of an actual carrier may vary slightly. 3. Symbols on drawing Ao, Bo, and Ko are defined in ANSI EIA Standard 481−B 2001. 4. Each reel is 330 millimeters in diameter and contains 5000 parts. 5. ams packaging tape and reel conform to th e requirements of EIA Standard 481−B. 6. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape. 7. This drawing is subject to change without notice. Mechanical Data
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Soldering and Storage Information Storage Information Moisture Sensitivity Optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previous ly absorbed into the package. To ensure the package contains the smallest amount of absorbed moisture possible, each device is baked prior to being dry packed for shipping. Devices are dry packed in a sealed aluminized envelope called a moisture-barrier bag with silica gel to protect them from ambient moisture during shipping, handling, and storage before use. Shelf Life The calculated shelf life of the device in an unopened moisture barrier bag is 12 months from the date code on the bag when stored under the following conditions:
- Shelf Life: 12 months
- Ambient Temperature: <40°C
- Relative Humidity: <90% Rebaking of the devices will be required if the devices exceed the 12 month shelf life or the Humidity Indicator Card shows that the devices were exposed to conditions beyond the allowable moisture region. Floor Life The module has been assigned a moisture sensitivity level of MSL 3. As a result, the floor life of devices removed from the moisture barrier bag is 168 hours from the time the bag was opened, provided that the devices are stored under the following conditions:
- Floor Life: 168 hours
- Ambient Temperature: <30°C
- Relative Humidity: <60% If the floor life or the temperature/humidity conditions have been exceeded, the devices must be rebaked prior to solder reflow or dry packing. Rebaking Instructions When the shelf life or floor life limits have been exceeded, rebake at 50°C for 12 hours.
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Ordering & Contact Information Figure 78:
Ordering Information
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8141 Premstaetten
Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com Ordering Code Address Interface Delivery Form TMG49037 0x29 I²C bus = 1.8V Interface Tape & Reel Ordering & Contact Information
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − RoHS Compliant & ams Green Statement RoHS: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specif ied lead-free processes. ams Green (RoHS compliant and no Sb/Br): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are unde rway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to prov ide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. RoHS Compliant & ams Green Statement
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Copyrights & Disclaimer Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used with out the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appe aring in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding th e information set forth herein. ams AG reserves the right to ch ange specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applic ations requiring extended temperature range, unusual environmental requirements, or high reliability applications , such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied wa rranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any th ird party shall arise or flow out of ams AG rendering of technical or other services. Copyrights & Disclaimer
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Document Status Document Status Product Status Definition Product Preview Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Datasheet Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade Datasheet (discontinued) Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Document Status
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Revision Information Note(s): 1. Page and figure numbers for the previous version may diff er from page and figure numbers in the current revision. 2. Correction of typographical er rors is not explicitly mentioned. Changes from 1-00 (2019-Aug-15) to current revision 1-01 (2019-Aug-20) Page Updated figure 26 21 Updated Revision ID Register 35 Revision Information
[v1-01] 2019-Aug-20 Document Feedback TMG49037 − Content Guide
1 General Description
2 Key Benefits & Features
2 Applications
3 Block Diagram
4 Pin Assignment
4 Pin Description
5A b s o l u t e M a x i m u m R a t i n g s
6 Electrical Characteristics
11 Timing Characteristics
11 Timing Diagram
12 Typical Operating Characteristics
17 I²C Protocol
17 I²C Write Transaction
17 I²C Read Transaction
20 Detailed Description
20 Sleep After Interrupt Operation
21 Register Description
24 Enable Register (ENABLE 0x80)
25 ALS Integration Time Register (ATIME 0x81)
26 Proximity Sample Time Register (PTIME 0x82)
27 Wait Time Register (WTIME 0x83)
28 ALS Interrupt Threshold Registers (0x84 – 0x87)
29 Proximity Interrupt Threshold Registers
(0x88 – 0x8B)
30 Interrupt Persistence Register (PERS 0x8C)
31 Configuration Register Zero (CFG0 0x8D)
32 Proximity/Gesture Configuration Register Zero (PG-
CFG0 0x8E)
33 Proximity/Gesture Configura tion Register One (PGCFG1
0x8F)
34 Configuration Register One (CFG1 0x90)
35 ID Register (ID 0x92)
36 Status Register (STATUS 0x93)
37 CRGB Data Registers (0x94 − 0x9B)
38 Proximity Data Registers (0x9C – 0x9D)
39 Status Register Two (STATUS2 0x9E)
40 Configuration Register Two (CFG2 0x9F)
41 Configuration Register Three (CFG3 0xAB)
42 Configuration Register Four (CFG4 0xAC)
43 Configuration Register Five (CFG5 0xAD)
44 Gesture Configuration Register Zero
(GCFG0 0xB0)
45 Gesture Configuration Register One
(GCFG1 0xB1)
46 Gesture Configuration Register Two
(GCFG2 0xB2) Content Guide
Document Feedback [v1-01] 2019-Aug-20 TMG49037 − Content Guide
47 Status Register Three (STATUS3 0xB3)
47 Gesture Sample Time Register (GTIME 0xB4)
48 Gesture Control Register (GST_CTRL 0xB5)
48 Gesture Threshold Re gisters (0xB6 – 0xB9)
49 Gesture FIFO Buffer Level Register
(GFIFO_LVL 0xBA)
49 Gesture Status Register (GSTATUS 0xBB)
50 Control Register (CONTROL 0xBC)
50 Auxiliary ID Register (AUXID 0xBD)
51 Proximity/Gesture Offset Registers
(0xC0 − 0xC7)
52 Proximity/Gesture Baseline Registers
(0xD0 − 0xD3)
53 Autozero Configuration Register
(AZ_CONFIG 0xD6)
54 Calibration Register (CALIB 0xD7)
55 Calibration Configuration Register Zero
(CALIBCFG0 0xD8)
57 Calibration Configuration Register One
(CALIBCFG1 0xD9)
58 Calibration Configuration Register Two
(CALIBCFG2 0xDA)
59 Calibration Configuration Register Three
(CALIBCFG3 0xDB)