TMF8801 OSRAM
Document overview
- Manufacturer or author: Provided By www.digicamel.com(free datasheet download site)
- PDF pages: 73
Technical content
v10-00 • 2022-Dec-20 Abstract The TMF8801 is a dToF (direct time of flight) optical distance sensor module achieving up to 2500mm target detection distance.
Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 2 Content Guide
6 Typical Operating
8.2 APPREV_MAJOR Register (Address
12 Soldering & Storage Information 67
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1 General Description
The TMF8801 is a time-of-flight (TOF) sensor in a single modular package with associated VCSEL. The TOF device is based on SPAD, TDC and histogram technology. The device achieves 2500 mm detection range.
1.1 Key Benefits & Features
The benefits and features of TMF8801, Time-of-Flight Sensor, are listed below: Figure 1: Added Value of Using TMF8801 Benefits Features Small footprint fits in the mobile phone bezel Modular package - 2.2 mm x 3.6 mm x 1.0 mm Detecting central closest objects 21ºFOI Within 5 % of measurement (accuracy); no multipath and no multiple object problems as for iToF Time-to-Digital Converter (TDC) Direct Time-of-Flight Measurement Better accuracy detects reliably closest object Minimum distance 20 mm Maximum distance 2500 mm Single Photon Avalanche Photodiode (SPAD) Histogram based architecture No complex calibration Dynamic cover glass calibration Compensates for dirt on glass Reliable Operation under demanding use cases Improved accuracy over temperature and life Reference SPAD Make better decisions Distance and signal quality reported Class 1 Eye Safe Fast VCSEL driver with protection Longer battery life 27 mA power consumption at 30 Hz operation 0.23 mA power consumption at 1 Hz 0.17 mA power consumption at 0.5 Hz 0.26 µA power-down current consumption (EN=0)
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1.2 Applications
The device is ideal for use in the mobile phone market with applications including:
- Distance measurement for camera autofocus (Laser Detect Autofocus - LDAF)
- Supporting low-power system operation by enabling high-power components (i.e. 3D camera) only when an object is in the detection range
- Presence detection - Object detection
- Collision avoidance
1.3 Block Diagram
The functional blocks of this device are shown below: Figure 2: Functional Blocks of TMF8801 TMF8801 VCSEL Optical Filter Reflective Surface Background Light Internal Reflection Optics SPAD, TDC and Histogram Driver Control Data Process Cortex M0 TOF SensorEN GPIO1 GPIO0INT SDA SCL VDDC GNDC VDD GND Host
Ordering Information
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2 Ordering Information
Ordering Code Package Marking Delivery Form Delivery Quantity TMF8801-1BM Optical Module 5-digit tracecode (coded) Tape & Reel (7’ reels) 500 pcs/reel TMF8801-1B Optical Module 5-digit tracecode (coded) Tape & Reel (13’ reels) 5000 pcs/reel
TMF8801 Module Description Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 6
3 TMF8801 Module Description
3.1 Pin Diagram
Figure 3: Pin Locations Top Through View (not to scale)
3.2 Pin Description
Figure 4: Pin Description of TMF8801 Pin Number Pin Name Signal Type Description
1 VDDC Supply Charge pump supply voltage (3 V); add a
capacitor GRM155R70J104KA01 (0402 X7R 0.1 µF 6.3 V) to GND
2 GNDC Ground Charge pump ground; connect all ground pins
3 GPIO0 I/O General purpose input/output; default output
low; leave open if not used VDDC GNDC GPIO0 INT SCL SDA VDDV GNDV GPIO1 EN GND VDD TMF8701 1 12
TMF8801 Module Description Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 7 Pin Number Pin Name Signal Type Description 4 INT Output Interrupt. Open-drain output; connect to GND if not used
5 SCL Input I²C Serial Clock
6 SDA I/O I²C Serial Data
7 VDD Supply Chip Supply voltage (3 V); add a capacitor
GRM155R70J104KA01 (0402 X7R 0.1 µF
6.3 V) to GND
8 GND Ground Chip Ground; connect all ground pins
9 EN Input Enable input active high; setting to low forces
the device into shutdown and all memory content is lost; connected to TMF8801 VDD if not connected to a host GPIO
10 GPIO1 I/O General purpose input/output; default output
low; leave open if not used
11 GNDV Ground VCSEL Ground; connect all ground pins
12 VDDV Supply VCSEL Supply voltage (3 V); add a capacitor
GRM155R70J104KA01 (0402 X7R 0.1 µF (1) SDA, SCL, INT and EN have no diode to any VDD supply. Therefore even with VDD=0 V they do not block the interrupt line or I²C bus. (2) GPIO0 and GPIO1 are push/pull output and have a diode to VDD; therefore if VDD is not powered, GPIO0 and GPIO1 should not be driven from outside.
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4 Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 5 Symbol Parameter Min Max Unit Comments Electrical Parameters VDDC, VDDV, VDD 3 V Supply voltage -0.3 3.6 V Connect pins VDDC, VDDV, VDD on PCB with very short connections GNDV, GNDC, GND Ground 0.0 0.0 V Connect all GND pins on PCB with very short connections GPIO0, GPIO1 Digital I/O terminal voltage -0.3 VDD + 0.3 V max. 3.6 V V Protection diode to VDD INT, SCL, SDA, EN Digital I/O terminal voltage -0.3 3.6 V No protection diodes to any positive supply only to ground I_SCR Latch up immunity ± 100 mA JEDEC JESD78D Nov 2011 Electrostatic Discharge ESDHBM Electrostatic Discharge HBM ± 2000 V JS-001-2014 ESDCDM Electrostatic Discharge CDM ± 500 V JEDEC JESD22-C101F Oct 2013 Temperature Ranges and Storage Conditions TSTRG Storage Temperature Range -40 85 °C RHNC Relative Humidity (non- condensing) 85 % MSL Moisture Sensitivity Level 3 Represents a maximum floor life time of 168h with TAMB < 30 °C and < 60 % r.h. (1) The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.”
Electrical Characteristics
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5 Electrical Characteristics
All limits are guaranteed. The parameters with Min and Max values are guaranteed with production tests or SQC (Statistical Quality Control) methods.
5.1 Recommended Operating Conditions
Device parameters are guaranteed at nominal conditions unless otherwise noted. While the device is operational across the temperature range, functionality will vary with temperature. Figure 6: Recommended Operating Conditions of TMF8801 Symbol Parameter Min Typ Max Unit Comment VDDV, VDDC, VDD 3 V supply voltage 2.7 3 3.3 V Temperature Range Free-air temperature -30 25 70 °C Operational
Typical Operating Characteristics Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 10
6 Typical Operating Characteristics
Following operating characteristics are measured with calibrated devices with full optical stack including glass and IR ink with >90 % transmissivity. The airgap is set to 0.38 mm. The ambient light is measured on the 1 m x 1 m target. A very diffuse scotch magic tape 810 is used for measurement with smudge. Figure 7:
350 Lux Fluorescent Light and 18% Grey Card
Figure 8:
350 Lux Fluorescent Light, 18% Grey Card and Smudge on Glass
350Lux Fluorescent Light, Grey Card Measured Distance vs. Target Distance [mm] 500 1000 1500 2000 2500 0 500 1000 1500 2000 2500 350Lux Fluorescent Light, Smudge on glass (1 layer scotch magic tape 810), Grey Card, Measured Distance vs. Target Distance [mm]
Typical Operating Characteristics Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 12 Figure 11: Field of Illumination of VCSEL (FOI), X-Axis: ±10.4°, Y-Axis: ±10.31°, 1/e2
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7 Functional Description
7.1 I²C Protocol
The TMF8801 is controlled by an I²C bus, one interrupt pin and two GPIO pins. The device uses I²C serial communication protocol for communication. The device supports 7-bit chip addressing and standard, fast mode and fast mode plus modes. Read and Write transactions comply with the standard set by Philips (now NXP). For a complete description of the I²C protocol, please review the NXP I²C design specification. Internal to the device, an 8-bit buffer stores the register address location of the byte to read or write. This buffer auto-increments upon each byte transfer and is retained between transaction events (i.e. valid even after the master issues a STOP and the I²C bus is released). During consecutive Read transactions, the future/repeated I²C Read transaction may omit the memory address byte normally following the chip address byte; the buffer retains the last register address +1. A Write transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESSWRITE, DATA BYTE(S), and STOP. Following each byte (9TH clock pulse) the slave places an ACKNOWLEDGE/NOT- ACKNOWLEDGE (ACK/NACK) on the bus. If NACK is transmitted by the slave, the master may issue a STOP. A Read transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS, RESTART, CHIP-ADDRESSREAD, DATA BYTE(S), and STOP. Following all but the final byte the master places an ACK on the bus (9TH clock pulse). Termination of the Read transaction is indicated by a NACK being placed on the bus by the master, followed by STOP. The default I²C address is 0x41. The address can be changed after power-up. Use the enable pin to enable only one device at a time to provide unique device addresses.
7.2 System Parameters
The on-chip microprocessor is a Cortex M0 µP.
Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 14 Figure 12: ARM M0 Parameters Parameter Min Nom Max Units Comment µP Operating Frequency 5.37 86 MHz The CPU can operate with the RC oscillator directly or with a 16x PLL; frequency tuning adjusts the default frequency to 4.7 MHz RAM 32 kB ROM 32 kB Max PLL Frequency 172 MHz for 5.37 MHz RC clock
7.3 I/O
Figure 13: Typical I/O Level Specification Symbol Parameter Condition Min Typ Max Units ILEAK SDA, SCL, GPIO0/1, EN, INT -5 5 µA VIH(1) SDA, SCL, GPIO0/1, EN 1.26 V VIL_I2C(1) SDA, SCL 2.7 V<VDD<2.9 V, <400 kHz I²C speed 0.3 V VDD >2.9 V, <400 kHz I²C speed 0.54 2.8 V<VDD<3.0 V, <1 MHz I²C speed 0.3 VDD>3.0 V, <1 MHz I²C speed 0.54 VIL GPIO0/1, EN 0.54 V VOL SDA, GPIO0/1, INT 2 mA sink 0 0.36 V 4 mA sink 0 0.6 V IDRIVE_H GPIO0/1 1 V applied on GPIO 3.6 mA IDRIVE_L GPIO0/1 1 V applied on GPIO 3.9 mA (1) The input high level VIH and low level VIL is defined to support a pull-up supply of 1.8 V ±5 %.
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7.4 Power Consumption
All current consumption values include silicon process variation. Temperature and voltages are at nominal conditions (23 ºC and 2.8 V). Figure 14: Power Consumption Parameter Condition Min Nom Max Units Comment I_VDD Powerdown Enable Pin Low I²C Off 0.02 0.26 1 µA State: Powerdown I_VDD Standby CPU Off, RAM On OSC Off, pon=0 I²C Wakeup Only 85 µA State: Standby I_VDD Wait CPU Off, RAM On, OSC On
5 MHz I²C On, Timer
140 µA State: Wait I_VDD Ranging Processing CPU Running at 80 MHz No VCSEL, No TDC 2.7 mA State: Histogram processing I_VDD Ranging Active CPU stopped VCSEL_clk_div2=0 (default), TDCs running 32.5 mA State: Ranging active I_VDD Ranging Active CPU stopped VCSEL_clk_div2=1, TDCs running 25.2 mA State: Ranging active I_VDD Ranging Average power consumption
30 Hz,33 ms
settings(1) 27 mA
1 Hz, Ranging
period = 1000 ms 0.23 mA Firmware 3.0.19.0 or higher, 80 k iterations, cmd_data6 = 0x23 (algorithm setting for command 0x02 or 0x03)
0.5 Hz,
period = 2000 ms 0.17 mA Peak VCSEL Current 230 mA Max VCSEL Duty Cycle 2 % (1) Current is reduced to typ. 17.7 mA if iteration is set to 600 k instead of 900 k and output data rate is maintained at 30 Hz by setting repetition_period = 33 [ms].
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7.5 Timing
7.5.1 Ranging Acquisition Timing
Figure 15: Ranging Acquisition Timing Parameter Min Nom Max Units Comment Ranging Time Default Settings 33 ms Varies with operational mode Ranging Init (including electrical calibration) 8 ms Only done on startup and if temperature changed from last calibration Ranging Period 209 ms Programmable by the interface 1000 / 2000 ms Additional modes added with firmware 3.0.19.0 or higher(1) (1) For firmware 3.0.19.0 or higher, set register repetition_period (cmd_data2 for command 0x02 or 0x03) to 0xfe for 1000 ms ranging period and 0xff for 2000 ms ranging period. Figure 16: Ranging Timing Diagram
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7.5.2 Reset Pin and Power-Up Timing
Figure 17: Reset Pin and Power-Up Timing Parameter Min Nom Max Units Comment Power On (Boot Time) 3 ms Does not include RAM download time Enable high to ready for measurement 8 ms Standby to Active Time <<1 ms Active to Standby Time <<1 ms Enable Low to Power Down Time <<1 ms
7.6 Algorithm Performance
As the performance of the algorithm is dependent on the ROM version, following section only applies for devices with order code TMF8801-1B (and TMF8801-1BM), calibrated and in-application oscillator calibration using the reference driver code and patched with the latest software patch from ams OSRAM – contact ams OSRAM to identify latest patch version. To achieve the full distance of 250 cm, the on chip oscillator needs to be tuned to 4.7 MHz. The TMF8801 is embedded in the application using a 0.38 mm airgap and a glass with an IR ink with >90 % transmissivity. The glass thickness is 0.5 mm. An additional mask on the opaque ink is implemented according to TMF8801 optical design guide (external document).
7.6.1 Calibration
To achieve the performance described in the next sections, a calibration of the algorithm needs to be performed (command = 0x0A). The TMF8801 shall be embedded in the final application and the cover glass including the IR ink needs to be assembled. The calibration test shall be done in a housing with minimal ambient light and no target within 40 cm in field of view of the TMF8801. The TMF8801 generates a calibration data set which is permanently stored on the host. On each power-up of the TMF8801 the calibration data set is sent by I²C to the TMF8801 prior to execution of any algorithms (commands=0x02 or 0x0B).
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7.6.2 Algorithm Timings
The TMF8801 can adjust the number of iterations and detection threshold using registers. A default mode is defined having 900 k iterations and threshold=0. Figure 18: Algorithm Timings Parameter Condition Min Nom Max Units Default mode command=0x02 or 0x03 cmd_data6=0xA3, cmd_data3=0x00, cmd_data1=0x03, cmd_data0=0x84 (900 k iterations) 33 ms
7.6.3 Algorithm Performance Parameters
The algorithm reports distance information of the closest object in 1 mm steps. Using the timings described in 7.6.2 following performance is achieved: Figure 19: Object Detection Algorithm Parameters Parameter Condition Min Nom Max Units Reflectivity of object at 940 nm Perpendicular to TMF8801 18 90 % Maximum distance detection, 1.5 m x 1.5 m object 350 lux fluorescent on object, 18% grey card 2500(1) mm 360 lux halogen light on object(2), 88% white card 2500(1) mm 360 lux halogen light on object(2), 18% grey card 1700 mm 1400 lux halogen light on object(3), 88% white card 1500 mm 1400 lux halogen light on object(4), 18% grey card 1250 mm 14000 lux halogen light on object(4), 18% grey card 550 mm Minimum distance detection, 18 % grey card, 20 cm x 26 cm 20 mm
Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 19 Parameter Condition Min Nom Max Units Accuracy Object distance ≥ 200 mm ±5 % 100 mm ≤ object distance < 200 mm ±10 mm 20 mm ≤ object distance < 100 mm ±15 mm Transition short to long distance mode 200 mm (1) To achieve the full distance, the oscillator need to be tuned to 4.7 MHz. Use ams OSRAM reference code to implement clock frequency tuning. Any target reported above 2500 mm should be considered as no object. (2) 360 lux halogen light represents 2.5 k sunlight equivalent; light on object only. (3) 1400 lux halogen light represents 10 k sunlight equivalent; light on object only (4) 14000 lux halogen light represents 100 k sunlight equivalent; light on object only
7.7 VCSEL
Internal protection ensures no single point of failure will cause the VCSEL to violate the Class 1 Laser Safety.
- Laser Safety Class 1
- VCSEL Pulse Rep Rate 23 ns (43 MHz; 37.6 MHz if clock frequency tuned to 4.7MHz) If VCSEL_clk_div=1 the frequency is divided by two.
7.8 Typical Optical Characteristics
- VCSEL Field of Illumination (FOI) 21º full width from 5% of maximum up to maximum 19º 1/e^2
- TOF Sensor Field of View (FOV) 37º FWHM – for short distances 24º FWHM – for long distances The SPAD FoV angular response uses the full TMF8801 SPADs for short distances. The SPAD FoV is reduced when the TMF8801 operates in long distance since the SPAD array is reduced. This helps to improve ambient light tolerance.
Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 20 Figure 20: FOI/FOV of TMF8801
7.8.1 Filter Characteristics:
- FWHM 56 nm
- Passband Center Wavelength 940 nm
- Stopband Wavelengths 350 nm – 912 nm, 968 nm – 1100 nm
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8 Register Description
8.1 APPID Register (Address 0x00)
Figure 21: APPID Register Addr: 0x00 APPID Field Name Rst Type Description 7:0 appid 0 RW Currently running application: 0xC0 App0 – Measurement application running 0x80 bootloader running
8.2 APPREV_MAJOR Register (Address 0x01)
Figure 22: APPREV_MAJOR Register Addr: 0x01 APPREV_MAJOR Field Name Rst Type Description 7:0 apprevMajor 0 RW Application major revision
8.3 APPREQID Register (Address 0x02)
Figure 23: APPREQID Register Addr : 0x02 APPREQID Field Name Rst Type Description 7:0 appReqid 0 RW Application that shall be started, set this to 0x80 … bootloader 0xC0 …. App0 – measurement application and wait until register 0x00 (APPID) shows this as application.
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8.4 ENABLE Register (Address 0xE0)
Figure 24: ENABLE Register Addr: 0xE0 ENABLE Field Name Rst Type Description 7 cpu_reset 0 RW_SC Write a '1' here to reset CPU. This generates global reset, fully resetting CPU and all CPU registers. The bit resets itself, no need to explicitly clear it. 6 cpu_ready 0 RO CPU is ready to handle I²C - if this bit is zero, then only the registers 0xe0 and above are usable, the memory mapped I²C space is not used. Bit gets set only explicitly by software, therefore a functional and running firmware is necessary for this bit to work. 0 pon 1 R_PUSH 1=Activate oscillator 0=Ask cpu to go to standby Activating the oscillator is implemented in hardware. Whenever this register is '0' and a '1' is being written, the oscillator is being started and CPU receives a PON1 interrupt. It is implemented in the bootloader to execute a reset at this point, but the application goes to an IDLE state. De-activating the oscillator is a software assisted process. It is important that the CPU powers down all modules properly before turning off the oscillator, therefore this is implemented in firmware. So writing a '0' to this register will trigger an internal CPU interrupt. The firmware, after powering down everything, sets the device into standby state.
8.5 INT_STATUS Register (Address 0xE1)
Figure 25: INT_STATUS Register Addr: 0xE1 INT_STATUS Field Name Rst Type Description 1 int2 0 R_PUSH1 Raw histogram available interrupt for App0; asserted when a raw histogram can be retrieved from I²C. int2 status. If bis is asserted, and int2_enab is asserted as well, then the INT pin will be pulled low. Writing a '1' here will clear int1 condition.
Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 23 Addr: 0xE1 INT_STATUS Field Name Rst Type Description 0 int1 0 R_PUSH1 Object detection interrupt for App0; asserted when a result from object detection is available int1 status. If bis is asserted, and int1_enab is asserted as well, then the INT pin will be pulled low. Writing a '1' here will clear int1 condition. Note: An interrupt is raised on every result from object detection including no-target unless persistence is set > 0.
8.6 INT_ENAB Register (Address 0xE2)
Figure 26: INT_ENAB Register Addr: 0xE2 INT_ENAB Field Name Rst Type Description 1 int2_enab 0 RW Raw histogram available interrupt for App0; asserted when a raw histogram can be retrieved from I²C. 0=disabled, 1=enabled -> INT output is active if int2 flag is "1" 0 int1_enab 0 RW Object detection interrupt for App0; asserted when a result from object detection is available 0=disabled, 1=enabled -> INT output is active if int1 flag is "1"
8.7 ID Register (Address 0xE3)
Figure 27: ID Register Addr: 0xE3 ID Field Name Rst Type Description 5:0 id 0 RO Chip ID, reads 07h – do not rely on register bits 6 and 7 of this register.
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8.8 REVID Register (Address 0xE4)
Figure 28: REVID Register Addr: 0xE4 REVID Field Name Rst Type Description 2:0 rev_id 0 RO Chip revision ID
8.9 App0 Registers – appid=0xC0
Following registers are only available if appid=0xC0 (App0):
8.9.1 CMD_DATA9 Register (Address 0x06)
Figure 29: CMD_DATA9 Register Addr: 0x06 CMD_DATA9 Field Name Rst Type Description 7:0 cmd_data9 0 W Command data 9 – see COMMAND Register (Address 0x10); for future extension of commands
8.9.2 CMD_DATA8 Register (Address 0x07)
Figure 30: CMD_DATA8 Register Addr: 0x07 CMD_DATA8 Field Name Rst Type Description 7:0 cmd_data8 0 W Command data 8 – see COMMAND Register (Address 0x10); for future extension of commands
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8.9.3 CMD_DATA7 Register (Address 0x08)
Figure 31: CMD_DATA7 Register Addr: 0x08 CMD_DATA7 Field Name Rst Type Description 7:0 cmd_data7 0 W Command data 7 – see COMMAND Register (Address 0x10)
8.9.4 CMD_DATA6 Register (Address 0x09)
Figure 32: CMD_DATA6 Register Addr: 0x09 CMD_DATA6 Field Name Rst Type Description 7:0 cmd_data6 0 W Command data 6 – see COMMAND Register (Address 0x10)
8.9.5 CMD_DATA5 Register (Address 0x0A)
Figure 33: CMD_DATA5 Register Addr: 0x0A CMD_DATA5 Field Name Rst Type Description 7:0 cmd_data5 0 W Command data 5 – see COMMAND Register (Address 0x10)
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8.9.6 CMD_DATA4 Register (Address 0x0B)
Figure 34: CMD_DATA4 Register Addr: 0x0B CMD_DATA4 Field Name Rst Type Description 7:0 cmd_data4 0 W Command data 4 – see COMMAND Register (Address 0x10)
8.9.7 CMD_DATA3 Register (Address 0x0C)
Figure 35: CMD_DATA3 Register Addr: 0x0C CMD_DATA3 Field Name Rst Type Description 7:0 cmd_data3 0 W Command data 3 – see COMMAND Register (Address 0x10)
8.9.8 CMD_DATA2 Register (Address 0x0D)
Figure 36: CMD_DATA2 Register Addr: 0x0D CMD_DATA2 Field Name Rst Type Description 7:0 cmd_data2 0 W Command data 2 – see COMMAND Register (Address 0x10)
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8.9.9 CMD_DATA1 Register (Address 0x0E)
Figure 37: CMD_DATA1 Register Addr: 0x0E CMD_DATA1 Field Name Rst Type Description 7:0 cmd_data1 0 W Command data 1 – see COMMAND Register (Address 0x10)
8.9.10 CMD_DATA0 Register (Address 0x0F)
Figure 38: CMD_DATA0 Register Addr: 0x0F CMD_DATA0 Field Name Rst Type Description 7:0 cmd_data0 0 W Command data 0 – see COMMAND Register (Address 0x10)
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8.9.11 COMMAND Register (Address 0x10)
Figure 39: COMMAND Register Addr: 0x10 COMMAND Field Name Rst Type Description 7:0 command 0 RW Direct the device to control or select contents of the registers from 0x20...0xDF Setting Meaning 0x00 No command 0x02 Set flag to perform target distance measurement with 8 bytes of data containing where including setting of calibration (and algorithm state) configuration. cmd_data7 = Bit mask which calibration/state data was downloaded from the host to TMF8801 prior to setting this command: Bits Definition 0 dataFactoryCal: When 1 data from register 0x20 onward includes factory calibration dataAlgState: If set, also set dataFactoryCal=1. Data from register 0x20 onwards includes factory calibration and algorithm state. cmd_data6… cmd_data0: Identical to command=0x03. 0x03 Set flag to perform target distance measurement with 7 bytes of data containing where cmd_data6 = Bit mask which algorithm is used Bits Definition
0 Set to ‘1’
1 Set to ‘1’
2 VCSEL_clk_div2: If set, operates the VCSEL clock at half
frequency - see section 7.7 - and doubles the ranging active time where the VCSEL is enabled. It is recommended to use together with spread_spectrum_mode=1. 3 Reserved; set to 0b. 4 algImmediateInterrupt – When 1 target distance measurement will immediately report to the host an interrupt of the capturing caused by a GPIO event; when 0, will only report to the host when target distance measurement was finished
5 When 1 combine the capture of the short and long distance
histogram for maximum speed 6 Reserved; set to 0.
7 When 1 do not go to standby between measurements (faster
measurement times but higher current consumption)
Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 29 cmd_data5 = Bits for GPIO control Bits Definition 3:0 GPIO0 settings 0 – Input 1 - Input: active low disables collection, immediately abandoning current measurement. Returning to high restarts new measurement 2 - Input: active high disables collection, immediately abandoning current measurement. Returning to low restarts new measurement 3 - Output: VCSEL pulse output – see cmd_data4 4 - Output low (default after startup) 5 - Output high 6:15 – Reserved, do not use 7:4 GPIO1 settings 0 - Input 1 - Input: active low disables collection, immediately abandoning current measurement. Returning to high restarts new measurement 2 - Input: active high disables collection, immediately abandoning current measurement. Returning to low restarts new measurement 3 - Output: VCSEL pulse output – see cmd_data4 4 - Output low (default after startup) 5 - Output high 6:15 – Reserved, do not use cmd_data4 = If cmd_data5 enables VCSEL pulse output for GPIO0 and/or GPIO1, cmd_data4 sets its timings as follows: Value Meaning
0 No signal
1 GPIOx, rises 0 µs time before VCSEL pulse starts
2 GPIOx rises 100 µs before VCSEL pulse
3 GPIOx rises 200 µs before VCSEL pulse and so on
The falling edge of GPIOx happens at the same time the VCSEL stops emitting light. cmd_data3 = Object detection threshold and spread spectrum mode Bits Definition 5:0 Object detection threshold – use 0 as default value spread_spectrum_mode: If set, avoids aliasing of objects into measurement range. Use together with VCSEL_clk_div2=1 otherwise maximum distance is reduced and false objects at far distance can occur.
7 Set to ‘0’
cmd_data2 = repetition_period in mSec, use 0 for single measurement; if the repetition period is set lower than the ranging time for this mode, the TMF8801 runs at it maximum possible speed (best effort approach). cmd_data1 = Number of iterations, low byte; 1 LSB=1 k cmd_data0 = Number of iterations, high byte; 1 LSB=1 k*256 Once a measurement is finished, the interrupt is asserted if it is enabled by int1_enab. Additionally the transaction ID tid is updated 0x08 Write additional configuration for application – only available for firmware version 3.0.22 or higher cmd_data4 = Persistence 8-bit value for interrupt suppression
Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 30 Addr: 0x10 COMMAND Field Name Rst Type Description Value Definition
0 Any result (detect and no-detect) will trigger an interrupt
1-255 An interrupt will only be triggered if the detected distance is >= low_threshold and distance <= high_threshold and the detection happened at least <persistence> consecutive times cmd_data3 = low_threshold 8-bit LSB value cmd_data2 = low_threshold 8-bit MSB value cmd_data1 = high_threshold 8-bit LSB value cmd_data0 = high_threshold 8-bit MSB value 0x09 Read additional configuration for application – only available for firmware version 3.0.22 or higher. After the command is executed, the persistence, low_threshold and high_threshold are stored in registers 0x20 to 0x24 – see section 8.9.22 - Interrupt Suppression Registers – Result of Command = 0x09 0x0A Perform factory calibration in the final customer application including cover glass, no ambient light and no target. The result from the factory calibration is stored from register 0x20 onwards (14 bytes). 0x0B Set flag to download calibration (and algorithm state) configuration to TMF8801 cmd_data0 = Bit mask which calibration/state data was downloaded from the host to TMF8801 prior to setting this command: Bits Definition 0 dataFactoryCal: when 1 data from register 0x20 onward includes factory calibration 1 dataAlgState: if set, also set dataFactoryCal=1. Data from register 0x20 onwards includes factory calibration and algorithm state. 0x0F Set gpio control setting without actually performing a measurement as commands 0x02 or 0x03 would do: cmd_data0 = Bits for GPIO control Bits Definition 3:0 GPIO0 settings 0 - Input 1 - Input: active low disables collection, immediately abandoning current measurement. Returning to high restarts new measurement 2 - Input: active high disables collection, immediately abandoning current measurement. Returning to low restarts new measurement 3 - Output: VCSEL pulse output 4 - Output low 5 - Output high 6:15 - Reserved, do not use
Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 31 Addr: 0x10 COMMAND Field Name Rst Type Description 7:4 GPIO1 settings 0 - Input 1 - Input: active low disables collection, immediately abandoning current measurement. Returning to high restarts new measurement 2 - Input: active high disables collection, immediately abandoning current measurement. Returning to low restarts new measurement 3 - Output: VCSEL pulse output 4 - Output low 5 - Output high 6:15 – Reserved, do not use 0x30 Enable histogram readout; the internal state machine will stop when a histogram (e.g. calibration) is available and wait for readout by the host. If the selected histogram is readout, the host shall continue the state machine by sending command 0x32 cmd_data3 = Bitmask for the histograms to be readout: Bit Definition
0 Always set to ‘0’
1 Set to get electrical calibration histograms
2 Set to get optical calibration histogram
3 Always set to ‘0’
4 Set to get short distance histograms
6:5 Always set to ‘00’ Set to get distance measurement histograms. Bin 127 respectively bin 255 is used as scaling factor for this type of histograms. The scaling factor is 0 for no scaling, 1 for 2x, 2 for 4x and so on. cmd_data2 = Set to 0x00 cmd_data1 = = Bitmask for pileup correct histograms readout: Bit Definition
0 Set to get pileup corrected distance measurement histograms
1 Set to get pileup corrected sum histogram
2 Set bit 2 to get pileup corrected short distance histogram
7:3 Always set to 0 cmd_data0 = set to 0x00 Once above bitmask is set, the device is programmed to stop when the histogram is available. Set command=0x04 to actually perform the measurement. 0x32 After the host has readout the histogram, continue with internal processing. 0x47 Read out serial number – results see section 0 Serial Number Readout 0x49 Change the I²C address of TMF8801 cmd_data0 = Condition if I²C address is changed; program the GPIOs input/output accordingly before using this feature (commands 0x02, 0x03 or 0x0F):
Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 32 Addr: 0x10 COMMAND Field Name Rst Type Description Bit Definition 0 mask_gpio0 1 mask_goio1 2 value_gpio0 3 value_gpio1 7:4 always set to 0 The I²C address change is executed only if (mask_gpio1 & GPIO1) << 1 + (mask_gpio0 & GPIO0) == value_gpio1 << 1 + value_gpio0 where GPIO1 and GPIO0 is the current status on pin GPIO1 and pin GPIO0. If this conditional programming is not used, set cmd_data0 to 0x00. cmd_data1 = New I²C address Bit Definition
0 Set to ‘0’
7:1 New I²C address to be used 0x80.. 0x93 Read 1 quarter of one histogram - copy histogram bits[4:2] to select TDC0…TDC4, quarter bits[1:0] into 0x20..0x9f NOTE: At the end of the transaction of read a quarter, the contents of the registers from 0x20-0x9F will be automatically updated, and the contents of registers REGISTER_CONTENTS and TID will be updated NOTE: At the end of a TDC, the TDC number will also auto increment. 0xFF Stop whatever you are doing as soon as possible and reenter the idle state. The current state will not be interrupted and will require leaving the current state processing to take effect. This command will stop continuous measurement.
8.9.12 PREVIOUS Register (Address 0x11)
Figure 40: PREVIOUS Register Addr: 0x11 PREVIOUS Field Name Rst Type Description 7:0 previousCommand 0 RO Previous command that was executed (or current if continues mode is selected)
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8.9.13 APPREV_MINOR Register (Address 0x12)
Figure 41: APPREV_MINOR Register Addr: 0x12 APPREV_MINOR Field Name Rst Type Description 7:0 appRevMinor 0 RO Application minor revision
8.9.14 APPREV_PATCH Register (Address 0x13)
Figure 42: APPREV_PATCH Register Addr: 0x13 APPREV_PATCH Field Name Rst Type Description 7:0 appRevPatch 0 RO Application patch number
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8.9.15 STATUS Register (Address 0x1D)
Figure 43: STATUS Register Addr: 0x1D STATUS Field Name Rst Type Description 7:0 status 0 RO Current status or current general operation Reading Meaning 00h-0Fh OK 10h-FFh Error
8.9.16 REGISTER_CONTENTS Register (Address 0x1E)
Figure 44: REGISTER_CONTENTS Register Addr: 0x1E REGISTER_CONTENTS Field Name Rst Type Description 7:0 register_contents 0 RO Current contents of the I²C RAM from 0x20 to 0xEF ; the coding is as follows: Reading Meaning 0Ah Calibration data 47h Serial number 55h Results for commands 0x02/0x03 and 0x04 80h-93h Raw histogram data where 80h = TDC0, bin 0…63 81h = TDC0, bin 64…127 82h = TDC0, bin 128..195 83h = TDC0, bin 196..255 84h = TDC1, bin 0…63 93h = TDC4, bin 196…255
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8.9.17 TID Register (Address 0x1F)
Figure 45: TID Register Addr: 0x1F TID Field Name Rst Type Description 7:0 tid 0 RO Unique transaction ID, changes with every update of register map by TOF
8.9.18 Object Detection Results – If Register register_contents = 0x55 (commands
0x02, 0x03 or 0x04) RESULT_NUMBER Register (Address 0x20) Figure 46: RESULT_NUMBER Register Addr: 0x20 RESULT_NUMBER Field Name Rst Type Description 7:0 result_num 0 RO Result number, incremented every time there is a unique answer RESULT_INFO Register (Address 0x21) Figure 47: RESULT_INFO Register Addr: 0x21 RESULT_INFO Field Name Rst Type Description 5:0 reliability 0 RO Reliability of object - valid range 0..63 where 63 is best 7:6 measStatus 0 RO When algImmediateInterrupt == 1 Will indicate the status of the measurement: Reading Meaning
0 Short distance capture interrupted, using
previous short distance only result
1 Short distance capture interrupted, using
previous short and long distance result
Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 36 Addr: 0x21 RESULT_INFO Field Name Rst Type Description
2 Long distance capture interrupted, result
is from short distance algorithm only
3 Complete result (short and long distance
algorithm) When algImmediateInterrupt == 0 Will indicate the status of the measurement: Reading Meaning
0 Measurement was not interrupted
1 Reserved
2 Measurement was interrupted (delay) by
3 Reserved
DISTANCE_PEAK_0 Register (Address 0x22) Figure 48: DISTANCE_PEAK_0 Register Addr: 0x22 DISTANCE_PEAK_0 Field Name Rst Type Description 7:0 distance_peak[7:0] 0 RO Distance to the peak in [mm] of the object, least significant byte DISTANCE_PEAK_1 Register (Address 0x23) Figure 49: DISTANCE_PEAK_1 Addr: 0x23 DISTANCE_PEAK_1 Field Name Rst Type Description 7:0 distance_peak[15:8] 0 RO Distance to the peak in [mm] of the object, most significant byte The sys clock registers is a running timer information – this value is counting up (and wraps around to 0 again) as long as the internal clock is running. As it is derived from the internal RC oscillator and
Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 44 OBJECT_HITS_3 Register (Address 0x3A) Figure 72: OBJECT_HITS_3 Register Addr: 0x3A OBJECT_HITS_3 Field Name Rst Type Description 7:0 object_hits[31:24] 0 RO Sum of the object SPADs hits during the distance measurement; zero if no object is detected or distance algorithm is no used
8.9.19 Calibration and Algorithm State Data Exchange
These registers shall be pre-loaded by the host before command=0x02 or 0x0B is executed FACTORY_CALIB_0 Register (Address 0x20) Figure 73: FACTORY_CALIB_0 Register Addr: 0x20 FACTORY_CALIB_0 Field Name Rst Type Description 7:0 factory_calib_0 0 RW Factory calibration data Bits [3:0] are format revision Bits [7:4] are bits [3:0] of crosstalk measurement; this is a summed value – for crosstalk specification according to ODG use xtalk_msb and xtalk_lsb. FACTORY_CALIB_1 Register (Address 0x21) Figure 74: FACTORY_CALIB_1 Register Addr: 0x21 FACTORY_CALIB_1 Field Name Rst Type Description 7:0 factory_calib_1 0 RW Factory calibration data
Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 51 STATE_DATA_WR_10 Register (Address 0x38) Figure 97: STATE_DATA_WR_10 Register Addr: 0x38 STATE_DATA_WR_10 Field Name Rst Type Description 7:0 state_data_wr_10 0 RW Algorithm state data
8.9.20 Raw Histogram Output – If Register register_contents=0x80…0x93
HISTOGRAM_START Register (Address 0x20) Figure 98: HISTOGRAM_START Register Addr: 0x20 HISTOGRAM_START Field Name Rst Type Description 7:0 hist_start 0 RW Quarter of histogram first byte …all bytes until… HISTOGRAM_END Register (Address 0x9F) Figure 99: HISTOGRAM_END Register Addr: 0x9F HISTOGRAM_END Field Name Rst Type Description 7:0 hist_end 0 RW Quarter of histogram last byte
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8.9.21 Serial Number Readout – If Register register_contents=0x47
SERIAL_NUMBER_0 Register (Address 0x28) Figure 100: SERIAL_NUMBER_0 Register Addr: 0x28 SERIAL_NUMBER_0 Field Name Rst Type Description 7:0 serial_number_0 0 RW Serial number byte 0 SERIAL_NUMBER_1 Register (Address 0x29) Figure 101: SERIAL_NUMBER_1 Register Addr: 0x29 SERIAL_NUMBER_1 Field Name Rst Type Description 7:0 serial_number_1 0 RW Serial number byte 1 IDENTIFICATION_NUMBER_0 (Address 0x2A) Figure 102: IDENTIFICATION_NUMBER_0 Register Addr: 0x2A IDENTIFICATION_NUMBER_0 Field Name Rst Type Description 7:0 identification_number_0 0 RW Identification number byte 0
Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 53 IDENTIFICATION_NUMBER_1 (Address 0x2B) Figure 103: IDENTIFICATION_NUMBER_1 Register Addr: 0x2B IDENTIFICATION_NUMBER_1 Field Name Rst Type Description 7:0 identification_number_1 0 RW Identification number byte 1 The binary concatenated number of serial_number_0: serial_number_1: identification_number_0: identification_number_1 registers result in a unique number.
8.9.22 Interrupt Suppression Registers – Result of Command = 0x09
These registers are only available for firmware version 3.0.22 or higher. PERSISTANCE Register (Address 0x20) Figure 104: PERSISTANCE Register Addr: 0x20 PERSISTANCE Field Name Rst Type Description 7:0 persistence 0 RW Persistence 8-bit value for interrupt suppression Value Definition 1-255 An interrupt will only be triggered if the detected distance is >= low_threshold and distance <= high_threshold and the detection happened at least <persistence> consecutive times LOW_THRESHOLD_LSB Register (Address 0x21) Figure 105: LOW_THRESHOLD_LSB Register Addr: 0x21 LOW_THRESHOLD_LSB Field Name Rst Type Description 7:0 low_threshold_lsb 0 RW Interrupt suppression low_threshold LSB Byte – see persistence register
Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 55 Addr: 0x24 HIGH_THRESHOLD_MSB Field Name Rst Type Description high_threshold = high_threshold_LSB + 256 * high_threshold_MSB
8.10 Bootloader Registers – appid=0x80
Following registers are only available if appid=0x80 (Bootloader):
8.10.1 BL_CMD_STAT (Address 0x08)
Figure 109: BL_CMD_STAT Register Addr: 0x08 BL_CMD_STAT Field Name Rst Type Description 7:0 bl_cmd_stat 0 RW Write: Bootloader Command – see section Bootloader Commands Read: Bootloader Status – anything else than 0x00 means an error
8.10.2 BL_SIZE (Address 0x09)
Figure 110: BL_SIZE Register Addr: 0x09 BL_SIZE Field Name Rst Type Description 6:0 bl_size 0 RW Data size in bytes
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8.10.3 BL_DATA (Address 0x0A-0x8A)
Figure 111: BL_DATA Register Addr: 0x0A-0x8A BL_DATA Field Name Rst Type Description 7:0 bl_data0 … bl_data127 0 RW Up to 128 data bytes for bootloader commands
8.10.4 BL_CSUM (Address 0x8B)
Figure 112: BL_CSUM Register Addr: 0x8B BL_CSUM Field Name Rst Type Description 7:0 bl_csum 0 RW Checksum for Sum(Command + Data Size + Data itself) XOR 0xFF
8.10.5 Bootloader Commands
The following commands (bl_cmd_stat) are supported by the bootloader: Command Value Meaning RAMREMAP_RESET 0x11 Remap RAM to Address 0 and Reset DOWNLOAD_INIT 0x14 Initialize for RAM download from host to TMF8801 W_RAM 0x41 Write RAM Region (Plain = not encoded into e.g. Intel Hex Records) ADDR_RAM 0x43 Set the read/write RAM pointer to a given address RAMREMAP_RESET = Execute Program Downloaded to RAM This command remaps the RAM to address 0 and performs a System reset (see also command RESET). Command is performed immediately without any delay.
Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 58 Address Value Meaning BL_DATA127 0..0xFF 128th byte to be written (only if size was 0x80) BL_CSUM 0..0xFF The CSUM comes immediately after the data. ADDR_RAM This command is to specify the RAM pointer location for the next R_RAM or W_RAM command. Figure 116: ADDR_RAM Address Value Meaning BL_CMD_STAT 0x43 Specify the address of the next RAM read or write. BL_SIZE 2 BL_DATA0 0..0xFF LSB of address in RAM BL_DATA1 0..0xFF MSB of address in RAM BL_CSUM 0..0xFF
Application Information
Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 59
9 Application Information
9.1 SPAD Options
9.1.1 Signal SPADs
Firmware can enable/disable SPADs in the array as needed. Figure 117: Signal SPADs Min Nom Max Comment 1x SPADS 72 10x Attenuated SPADs 16 100x Attenuated SPADs 16 Physically there are 4x32=128 signal SPADs, but SPADs with too high dark count rate are disabled during production test. There are four TDCs (TDC1…TDC4) connected to the output of the SPADs. Each of the TDCs is connected to an array of 32 SPADs (SPADs with too high dark count rate are disabled). In distance mode the number of SPADs are reduced to typ. 40 SPADs to limit the FOV of the TMF8801.
9.1.2 Reference SPADs
Figure 118: Reference SPADs Min Nom Max Comment 100x Attenuated SPADs 9 Due to the high light intensity form the VCSEL which is located very close to the reference SPADs and has no optical barrier like the signal SPADs only highly attenuated SPADs are used. Physically there are 12 reference SPADs, but SPADs with too high dark count rate are disabled during production test. There is one TDC (TDC0) connected to the output of the SPADs.
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9.2 Reference SPAD, TDC and Histogram
There is an internal reference SPAD with associated TDC and histogram. This is used to determine the start time of each pulse. The reference SPAD is processed during calibration. The reference channel processing occurs internal to the device with no user interaction required. All histograms can be processed inside the TMF8801 and/or readout through the I²C interface. As the readout is constrained by the I²C speed and the I²C bus utilization (TMF8801 can support I²C speed up to 1 MHz), it is recommended to readout the histograms only for debugging purposes. Figure 119 shows a histogram obtained from TMF8801. The x-axis is scaled in bins, where the nominal bin size is 200 ps per bin and each TDC channel has 128 bins. Each TDC has two channels: The first channel is shown in bins 0…127, the second channel is shown in bins 128…255. The y-axis is scaled in counts represented by 16-bit values. The green line shows the reference histogram from TDC0 and its peak marks the reference or zero distance. The other four lines (blue, cyan, red and violet) are the histograms obtained from TDC1 to TDC4. A target at 20 cm is used to generate the peak around bin 20 respectively bin 148. Figure 119: Histogram
Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 61
9.3 Schematic
The TMF8801 needs only 3 small 0402 external capacitors for operation: Figure 120: The SYNC signal connected to GPIO1 can be used to immediately interrupt the TMF8801 VCSEL operation if the high power illuminator is operating. It needs to be ensured that SYNC does not exceed the VDD supply of TMF8801 as otherwise an internal protection diode will start conducting. The VCSEL operation is controlled by setting cmd_data5 of command=0x02 or 0x03 according (see App0 registers). On SYNC assertion, the VCSEL is immediately switched off (typically after 10 µs), on SYNC de-assertion the VCSEL operation is resumed within >100 µs. GPIO0 can be used as a general GPIO output signal. The signals INT/SDA/SCL need an external pullup resistor to the VIO supply (typically 1.8 V). TMF8801 VCSEL Optical Filter Reflective Surface Background Light Internal Reflection Optics SPAD, TDC and Histogram Driver Control Data Process EN GPIO1 GPIO0 INT SDA SCL VDDCGNDC VDDVGNDV VDD GND Host VDD0.1µF/6V3 VDD 2x 0.1µF/6V3 High Power Illuminator VIO SYNC
Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 62
9.3.1 Operating Several TMF8801 on a Single I²C Bus
Several TMF8801 devices can share a single I²C bus if there are dedicated enable (EN) connections to each of these devices. Figure 121: Sharing a Single I²C Bus for Operating Several TMF8801s The procedure to initialize the devices to different I²C addresses is as follows: 1. Set EN1=0, EN2=0, EN3=0 (reset all devices) 2. Set EN1=1 3. Upload firmware patch to first TMF8801 4. Reprogram I²C address for first TMF8801 using command=0x49 where cmd_data0=0 and cmd_data1=I²C address for first TMF8801 5. Set EN2=1 EN1 INT1 SDA SCL Host Cortex M0 GPIO1 GPIO0 TMF8801 VCSEL Optical Filter Reflective Surface Background Light Internal Reflection Optics SPAD, TDC and Histogram Driver Control Data Process TOF Sensor Cortex M0 GPIO1 GPIO0 TMF8801 VCSEL Optical Filter Reflective Surface Background Light Internal Reflection Optics SPAD, TDC and Histogram Driver Control Data Process TOF Sensor Cortex M0 GPIO1 GPIO0 TMF8801 VCSEL Optical Filter Reflective Surface Background Light Internal Reflection Optics SPAD, TDC and Histogram Driver Control Data Process TOF SensorEN2 INT2 SDA SCL EN3 INT3 SDA SCL
Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 63 6. Upload firmware patch to second TMF8801 7. Reprogram I²C address for second TMF8801 using command=0x49 where cmd_data0=0 and cmd_data1=I²C address for second TMF8801 8. Set EN3=1 9. Upload firmware patch to third TMF8801 10. Reprogram I²C address for third TMF8801 using command=0x49 where cmd_data0=0 and cmd_data1=I²C address for third TMF8801 11. If there are further devices, repeat last three steps accordingly.
9.4 PCB Layout
Figure 122: PCB Layout Recommendation Use GRM155R70J104KA01 (0402 X7R 0.1 µF 6.3 V) or capacitors with same or better performance for CVDDC, CVDD and CVDDV. (0402) VDDC GNDC GPIO0 EN GND VDD GPIO1 INT SCL SDA GNDV VDDV GND GND VDD VDD VDD GND GPIO1 EN GPIO0 INT SCL SDA CVDDC (0402) CVDDV (0402)CVDD (0402) GND PLANE
Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 64
9.5 PCB Pad Layout
Figure 123: PCB Pad Layout (1) All linear dimensions are in millimeters. (2) Dimension tolerances are 0.05 mm unless otherwise noted. (3) This drawing is subject to change without notice. Use the PCB pad layout as a recommendation only. The actual pad layout shall be optimized for the customer production line.
Package Drawings & Markings Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 65 Figure 124: Package Drawing (1) All linear dimensions are in millimeters. (2) Contact finish is Au/Ni. (3) This package contains no lead (Pb). (4) This drawing is subject to change without notice. (5) 5-digit tracecode is only on bottom side of the package. RoHS Green
Tape & Reel Information Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 66
11 Tape & Reel Information
Figure 125: Tape and Reel Drawing (1) All linear dimensions are in millimeters. Dimension tolerance is ± 0.10 mm unless otherwise noted. (2) The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly. (3) Symbols on drawing A0, B0, and K0 are defined in ANSI EIA Standard 481-B 2001. (4) There are two reel sizes available (see section Ordering Information) i) 7’’ reels: Each reel is 7 inch in diameter and contains 500 parts. ii) 13’’ reels: Each reel is 13 inch in diameter and contains 5000 parts. (5) ams OSRAM packaging tape and reel conform to the requirements of EIA Standard 481-B. (6) In accordance with EIA standard, device pin 1 is located next to sprocket holes in the tape. (7) This drawing is subject to change without notice.
Soldering & Storage Information Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 67
12 Soldering & Storage Information
12.1 Soldering Information
The package has been tested and has demonstrated an ability to be reflow soldered to a PCB substrate. The solder reflow profile describes the expected maximum heat exposure of components during the solder reflow process of product on a PCB. Temperature is measured on top of component. The components should be limited to a maximum of three passes through this solder reflow profile. Figure 126: Solder Reflow Profile Graph Figure 127: Solder Reflow Profile Parameter Reference Device Average temperature gradient in preheating 2.5 °C/s Soak time tsoak 2 to 3 minutes Time above 217 °C (T1) t1 Max 90 s
Soldering & Storage Information Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 68 Parameter Reference Device Time above 230 °C (T2) t2 Max 50 s Time above Tpeak – 10 °C (T3) t3 Max 10 s Peak temperature in reflow Tpeak 260 °C Temperature gradient in cooling Max −5 °C/s
12.2 Storage Information
12.2.1 Moisture Sensitivity
Optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previously absorbed into the package. To ensure the package contains the smallest amount of absorbed moisture possible, each device is baked prior to being dry packed for shipping. Devices are dry packed in a sealed aluminized envelope called a moisture-barrier bag with silica gel to protect them from ambient moisture during shipping, handling, and storage before use. Shelf Life The calculated shelf life of the device in an unopened moisture barrier bag is 24 months from the date code on the bag when stored under the following conditions:
- Shelf Life: 24 months
- Ambient Temperature: <40 °C
- Relative Humidity: <90 % Rebaking of the devices will be required if the devices exceed the 24 month shelf life or the Humidity Indicator Card shows that the devices were exposed to conditions beyond the allowable moisture region. Floor Life The module has been assigned a moisture sensitivity level of MSL 3. As a result, the floor life of devices removed from the moisture barrier bag is 168 hours from the time the bag was opened, provided that the devices are stored under the following conditions:
- Floor Life: 168 hours
- Ambient Temperature: <30 °C
- Relative Humidity: <60 % If the floor life or the temperature/humidity conditions have been exceeded, the devices must be rebaked prior to solder reflow or dry packing.
Soldering & Storage Information Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 69 Rebaking Instructions When the shelf life or floor life limits have been exceeded, rebake at 50 °C for 12 hours.
Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 70
13 Laser Eye Safety
The TMF8801 is designed to meet the Class 1 laser safety limits including single faults in compliance with IEC / EN 60825-1:2014. This applies to the stand-alone device and the included software supplied by ams OSRAM. In an end application system environment, the system may need to be tested to ensure it remains compliant. The system must not include any additional lens to concentrate the laser light or parameters set outside of the recommended operating conditions. Use outside of the recommended condition or any physical modification to the module during development could result in hazardous levels of radiation exposure.
Datasheet • PUBLIC DS000648 • v10-00 • 2022-Dec-20 72 │ 71 Document Status Product Status Definition Product Preview Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Datasheet Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams-OSRAM AG standard warranty as given in the General Terms of Trade Datasheet (discontinued) Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams-OSRAM AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Changes from previous version to current revision v10-00 Page Added commands 0x08 and 0x09 for interrupt suppression which are available for firmware version 3.0.22 or higher Added interrupt suppression registers which are available for firmware version 3.0.22 or higher 53-55 Increased shelf life to 24 months 68
- Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
- Correction of typographical errors is not explicitly mentioned.
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15 Legal Information
Copyrights & Disclaimer Copyright ams-OSRAM AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ams-OSRAM AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of Trade. ams-OSRAM AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams-OSRAM AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams-OSRAM AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams-OSRAM AG for each application. This product is provided by ams-OSRAM AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams-OSRAM AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams-OSRAM AG rendering of technical or other services. RoHS Compliant & ams Green Statement RoHS Compliant: The term RoHS compliant means that ams-OSRAM AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories plus additional 4 substance categories (per amendment EU 2015/863), including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead -free processes. ams Green (RoHS compliant and no Sb/Br/Cl): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) and do not contain Chlorine (Cl not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams-OSRAM AG knowledge and belief as of the date that it is provided. ams-OSRAM AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams-OSRAM AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams-OSRAM AG and ams-OSRAM AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Headquarters ams-OSRAM AG Tobelbader Strasse 30
8141 Premstaetten
Austria, Europe Tel: +43 (0) 3136 500 0 Please visit our website at www.ams.com Buy our products or get free samples online at www.ams.com/Products Technical Support is available at www.ams.com/Technical-Support Provide feedback about this document at www.ams.com/Document-Feedback For sales offices, distributors and representatives go to www.ams.com/Contact For further information and requests, e-mail us at ams_sales@ams.com