TMD2712 OSRAM
Document overview
- Manufacturer or author: Provided By www.digicamel.com(free datasheet download site)
- PDF pages: 54
Technical content
Datasheet, Public Page 1 [v4-00] 2023-Jan-02 Document Feedback TMD2712 ALS + Proximity Sensor Module The TMD2712 features proximity detection and digital ambient light sensing (ALS). The extremely tiny 1mm x 2mm module incorporates an IR VCSEL and fa ctory calibrated VCSEL driver. The proximity detection feature provides object detection (e.g. mobile device screen to user’s ear) by photodiode detection of reflected IR energy (sourced by the integrated VCSEL). Detect/release events are interrupt driven, and occur when proximity result crosses upper an d/or lower threshold settings. The proximity engine features a wide range offset adjustment to compensate for unwanted IR energy reflection at the sensor. Proximity results are further improved by automatic ambient light subtraction. The ALS and IR photodiodes have dedicated data converters producing 16-bit data. This architecture allows applications to accurately measure ambient light which enables devices to calculate illuminance to control display backlight. Ordering Information and Content Guide appear at end of datasheet. Key Benefits & Features The benefits and features of TM D2712, ALS + Proximity Sensor Module are listed below: Figure 1: Added Value of Using TMD2712 Benefits Features
- Optimized for narrow bezel mobile phones • Tiny 1mm x 2mm x 0.5mm module
- Reduced power consumption
- 1.8V power supply with 1.8V I²C bus
- Sleep mode (0.7μA)
- VCSEL IR emitter
- Enabled superior proximity detection
- Integrated factory calibrated 940nm IR VCSEL
- Crosstalk and ambient light cancellation
- Wide configuration range
- Accurate ambient light sensing
- High sensitivity
- 2 channels (photopic ALS + IR)
- Programmable gain and integration time
- Industrial design flexibility • Offset emitter/detector package design General Description
Page 2 Datasheet, Public Document Feedback [v4-00] 2023-Jan-02 TMD2712 − General Description
Applications
The TMD2712 applications include:
- Mobile phone di splay management
- Mobile phone and wearable user proximity detection
- Wearable ambient light measurement Block Diagram The functional blocks of this device are shown below: Figure 2: Functional Blocks of TMD2712 SCL SDA INT VDD CH1 ADC CH1 DataPhotopic IR Proximity Integration Proximity Control Prox Data Prox Thresholds Lower Upper Prox ADC ALS Thresholds Lower Upper I2C Interface Interrupt Open Drain Output Open Drain Current Sink GND 940nm IR VCSEL ALS Control CH0 ADC CH0 Data IR VDD3
Datasheet, Public Page 3 [v4-00] 2023-Jan-02 Document Feedback TMD2712 − Pin Assignments Figure 3: Pin Diagram (Top View) Figure 4: Pin Description of TMD2712 Pin Number Pin Name Description 1I N T Interrupt. Open drain output (active low). If INT is not used, tie to GND for enhanced ESD protection. 2 GND Ground. All voltages are referenced to GND. 3 VDD3 Supply voltage for IR emitter (3.0/3.3V)
4 SDA I²C serial data I/O terminal
5 SCL I²C serial clock input terminal
Supply voltage for sensor (1.8V). To enable the device to recover from a high voltage ESD strike, it is recommended to connect VDD to a host GPIO pin for independent power control. Pin Assignments ,17 *1' 9'' 6'$ 9'' 6&/
Page 4 Datasheet, Public Document Feedback [v4-00] 2023-Jan-02 TMD2712 − Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 5: Absolute Maximum Ratings Symbol Parameter Min Max Units Comments Electrical Parameters VDD Supply Voltage to GND -0.3 1.98 V VDD3 IR Emitter Voltage to GND -0.3 3.6 V VIO Digital I/O Terminal Voltage -0.3 3.6 V IIO Digital Output Terminal Current -1 20 mA Electrostatic Discharge ISCR Input Current (latch-up immunity) ± 100 mA Class II JEDEC JESD78E ESDHBM HBM Electrostatic Discharge ± 2000 V JEDEC/ESDA JS-001-2017 ESDCDM CDM Electrostatic Discharge ± 500 V JEDEC JS-002-2014 Temperature Ranges and Storage Conditions TSTRG Storage Temperature Range -40 85 °C IPC/JEDEC J-STD-020 The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Non-hermetic Solid State Surface Mount Devices.” RH NC Relative Humidity (non-condensing) 85 % PDISS Power Dissipation 50 mW Average power dissipation over a 1 second period MSL Moisture Sensitivity Level 3 Maximum floor life time of 168h Absolute Maximum Ratings
Page 6 Datasheet, Public Document Feedback [v4-00] 2023-Jan-02 TMD2712 − Electrical Characteristics Figure 8: ALS Optical Characteristics (VDD = 1.8V, T A = 25°C unless otherwise noted) Note(s): 1. Representative result by characterization. Parameter Conditions Min Typ Max Unit CH0 ALS sensitivity Warm White LED @ 8μW/cm2 AGAIN = 128x ATIME = 100ms -15% 1113 +15% counts CH1 ALS sensitivity 940nm LED @ 21.1μW/cm2 AGAIN = 128x ATIME = 100ms -20% 375 +20% counts ALS integration step size 2.68 2.78 2.90 ms ALS CH0 / CH1 dark count 0μW/cm AGAIN = 1024x ATIME = 50ms 0 1 2 counts ALS 16x gain scaling Relative to 128x 0.125 x ALS 1024x gain scaling Relative to 128x 8.2 x ALS noise (1) AGAIN = 128x ATIME = 100ms 0.05 % (σ)
Datasheet, Public Page 7 [v4-00] 2023-Jan-02 Document Feedback TMD2712 − Electrical Characteristics Figure 9: Proximity Optical Characteristics (VDD = 1.8V, VDD3 = 3.0V, T A = 25°C unless otherwise noted) Note(s): 1. Representative result by characterization. 2. Response with no target varies with power supply characteristics and system noise. 3. At factory final test. Parameter Conditions Min Typ Max Unit Response: absolute (1) PGAIN1 = 1x; PGAIN2 = 10x PLDRIVE = 8mA PPULSE = 4 pulses PPULSE_LEN = 34μs HW Averaging = 8 BINSRCH_TARGET = 15 APC = disabled Post Calibration Target material: 18% reflective surface No glass above module Target Size: 100mm x 100mm Target Distance: 30mm 120 counts Part to Part Variation (3) Same as Response: absolute except target is 51mm diameter diffusor ±25 % Response: no target (2) Same as Response: absolute except no target 4 14 30 counts
Page 10 Datasheet, Public Document Feedback [v4-00] 2023-Jan-02 TMD2712 − Detailed Description Proximity Proximity results are affected by three fundamental factors: the integrated IR VCSEL emission, IR reception, and environmental factors, including target distance and surface reflectivity. The IR reception signal path begins with IR detection from a photodiode and ends with the 14 -bit proximity result in PDATA register. Signal from the photodiode is amplified, and offset adjusted to optimize performance. Offset correction or cross-talk compensation is accomplished by adjustment to the POFFSET register. The analog circuitry of the device applies the offset value as a subtraction to the signal accumulation; therefore a positive offset value has the effect of decreasing the results. Ambient Light Sensing, ALS The ALS reception signal path begins as photodiodes receive filtered light and ends with 16-bit results. Channel 0 contains a photopic filter and channel 1 contains an infrared (IR) filter which is used both for the pr oximity function and also to accurately measure ambient light levels. Signals from both photodiodes are simultaneously accumulated for a period of time set by the value in ATIME before the results are available. Gain is adjustable by either 128x or 1024x to facilitate operation over a wide range of lighting conditions under dark glass with low transmissivity. Based on the op tical glass used on top of the device, custom equations are empirically derived to calculate the amount of ambient light using the ALS results. Detailed Description
Datasheet, Public Page 11 [v4-00] 2023-Jan-02 Document Feedback TMD2712 − Detailed Description Operational State Diagram Figure 14: Operational State Diagram Note(s): 1. ALS active time = ALS integration time (ATIME) 2. Proximity active time = (7 x PULSE_LEN) + PPULSE x (2x PULSE_LEN + 22μs) + 78.75μs. SLEEP (PON = 0) IDLE (PON = 1) PEN = 1 Hardware Averaging Loop 2 to 16 Times Proximity ACTIVE2 Complete PRATE PROX_AVG (if enabled) PWTIME (if enabled) Update PDATA SAI (if enabled) Wait Time Y Y Idle Sleep Active IDD Supply Current ALS ACTIVE1 AWTIME (if enabled) Update CH0/1 DATA SAI (if enabled) Y AEN = 1
Page 12 Datasheet, Public Document Feedback [v4-00] 2023-Jan-02 TMD2712 − Detailed Description I²C Characteristics The device uses I²C serial communication protocol for communication. The device support s 7-bit chip addressing and both standard and fast clock frequency modes with a chip address of 0x39. Read and write transactions comply with the standard set by Ph ilips (now NXP). Internal to the device, an 8-bit buffer stores the register address location of the desired byte to read or write. This buffer auto-increments upon each byte transfer and is retained between transaction events (i.e. valid even after the master issues a STOP command and the I²C bus is released). During consecutive Read transactions, the future/repeated I²C Read transaction may omit the memory address byte normally following the chip address byte; the buffer retains the last register address + 1. I²C Write Transaction A Write transaction consists of a START, CHIP-ADDRESS WRITE , REGISTER-ADDRESS, DATA BYTE(S ), and STOP . Following each byte (9TH clock pulse) the slave places an ACKNOWLEDGE/ NOT-ACKNOWLEDGE (ACK/NACK) on the bus. If NACK is transmitted by the slave, the master may issue a STOP . I²C Read Transaction A Read transaction consists of a START, CHIP-ADDRESS WRITE , REGISTER-ADDRESS, START, CHIP-ADDRESS READ , DATA BYTE(S), and STOP . Following all but the final byte the master places an ACK on the bus (9TH clock pulse). Termination of the Read transaction is indicated by a NA CK being placed on the bus by the master, followed by STOP . Alternately, if the previous I²C transaction was a Read, the internal register address buffer is still valid, allowing the transaction to proceed without “re”-specifying the register address. In this case the transaction consists of a START, CHIP-ADDRESS READ ,DATA BYTE(S), and STOP . Following all but the final byte the master places an ACK on the bus (9TH clock pulse). Termination of the Read transaction is indicated by a NACK being placed on the bus by the master, followed by STOP . The I²C bus protocol was develo ped by Philips (now NXP). For a complete description of the I²C protocol, please review the NXP I²C design specification at: https://www.i2c-bus.org/references/
Datasheet, Public Page 13 [v4-00] 2023-Jan-02 Document Feedback TMD2712 − Detailed Description Timing Diagrams Figure 15: I²C Timing Diagrams
Page 14 Datasheet, Public Document Feedback [v4-00] 2023-Jan-02 TMD2712 − Register Description Figure 16: Register Overview Address Register Name R/W Register Function Reset Value 0x80 ENABLE R/W Enables states and interrupts 0x00 0x81 ATIME R/W ADC integration time 0x00 0x82 PRATE R/W Proximity time 0x1F 0x83 AWTIME R/W ALS wait time 0x00 0x84 AILTL R/W ALS interrupt low threshold low byte 0x00 0x85 AILTH R/W ALS interrupt low threshold high byte 0x00 0x86 AIHTL R/W ALS interrupt high threshold low byte 0x00 0x87 AIHTH R/W ALS interrupt high threshold high byte 0x00 0x88 PILTL R/W Proximity interrupt low threshold low byte 0x00 0x89 PILTH R/W Proximity interrupt low threshold high byte 0x00 0x8A PIHTL R/W Proximity interrupt high threshold low byte 0x00 0x8B PIHTH R/W Proximity interrupt high threshold high byte 0x00 0x8C PERS R/W ALS and proximity interrupt persistence filters 0x00 0x8D CFG0 R/W Configuration zero 0x58 0x8E PCFG0 R/W Proximity configuration zero 0x8F 0x8F PCFG1 R/W Proximity configuration one 0x32 0x90 PCFG2 R/W Proximity configuration two 0x20 0x91 REVID R Revision ID 0x00 0x92 ID R Device ID 0x64 0x93 CFG1 R/W Configuration one 0x68 0x94 STATUS R, SC Device status 0x00 0x95 ALSL R ALS (CH0) low data 0x00 0x96 ALSH R ALS (CH0) high data 0x00 0x97 IRL R IR (CH1) low data 0x00 0x98 IRH R IR (CH1) high data 0x00 0x99 PDATAL R Proximity ADC low data 0x00 0x9A PDATAH R Proximity ADC high data 0x00 Register Description
Datasheet, Public Page 15 [v4-00] 2023-Jan-02 Document Feedback TMD2712 − Register Description Note(s): 1. R = Read Only / W = Write Only / R/W = Read or Write / SC = Self Clearing after access. 0xA6 REVID2 R Revision ID two 0x00 or 0x0F 0xA8 SOFTRST R/W Soft reset 0x00 0xA9 PWTIME R/W Proximity wait time 0x00 0xAA CFG8 R/W Configuration eight (must be set to 0x29) 0x2A 0xAB CFG3 R/W Configuration three 0x01 0xAE CFG6 R/W Configuration six 0x3F 0xC0 POFFSETL R/W Proximity offset low data 0x00 0xC1 POFFSETH R/W Proximity offset high data 0x00 0xD7 CALIB R/W Proximity offset calibration 0x00 0xD8 CALIB_OFFSET R/W Proximity offset extension 0x00 0xD9 CALIBCFG R/W Proximity offset calibration control 0x50 0xDC CALIBSTAT R Proximity offset calibration status 0x00 0xDD INTENAB R/W Interrupt enables 0x00 0xE6 FAC_L R Factory data low 0x00 to 0xFF 0xE7 FAC_H R Factory data high 0x00 to 0xFF 0xF9 TEST9 R/W Test nine (must be set to 0x06) 0x0C Address Register Name R/W Register Function Reset Value
Page 16 Datasheet, Public Document Feedback [v4-00] 2023-Jan-02 TMD2712 − Register Description Detailed Register Description Enable Register (Address 0x80) Figure 17: Enable Register Note(s): 1. When the ALS function is en abled (AEN = 1), this bit must be set to a one (PWEN = 1). Before activating AEN or PEN, preset each applicable operating mode registers and bits. To change register settings, it is necessary to deactivate PON an d set all applicable operating mode registers and bits before activating PON again. Addr: 0x80 Enable Bit Bit Name Default Access Bit Description 7:5 Reserved 0 RW Reserved. Must be set to default value. 4P W E N 0 R W This bit activates the proximity wait feature which is set by the PWTIME register. Active high. (1) 3A W E N 0 R W This bit activates the ALS wait feature which is set by the AWTIME register. Active high. 2 PEN 0 RW This bit activates the proximity detection. Active high. 1 AEN 0 RW This bit actives the ALS function. Active high. 0P O N 0 R W This field activates the internal oscillator and ADC channels. Active high.
Page 22 Datasheet, Public Document Feedback [v4-00] 2023-Jan-02 TMD2712 − Register Description PERS Register (Address 0x8C) Figure 29: PERS Register The frequency of consecutive proximity channel results outside of threshold limits are counted; this count value is compared against the PPERS value. If the counter is equal to the PPERS value an interrupt is asserted . Any time a pr oximity channel result is inside the threshold values the counter is cleared. Addr: 0x8C PERS Bit Bit Name Default Access Bit Description 7:4 PPERS 0 (0000) RW This register sets the proximity persistence filter. Value Interrupt 0 (0000) Every proximity cycle 1 (0001) Any value outside proximity thresholds 2 (0010) 2 consecutive proximity values out of range 3 (0011) 3 consecutive proximity values out of range …… . 15 (1111) 15 consecutive proximity values out of range 3:0 APERS 0 (0000) RW This register sets the ALS persistence filter. 0 (0000) Every ALS cycle 1 (0001) Any value outside ALS thresholds 2 (0010) 2 consecutive ALS values out of range 3 (0011) 3 consecutive ALS values out of range 4 (0100) 5 consecutive ALS values out of range 5 (0101) 10 consecutive ALS values out of range 6 (0110) 15 consecutive ALS values out of range 7 (0111) 20 consecutive ALS values out of range 13 (1101) 50 consecutive ALS values out of range 14 (1110) 55 consecutive ALS values out of range 15 (1111) 60 consecutive ALS values out of range
Datasheet, Public Page 23 [v4-00] 2023-Jan-02 Document Feedback TMD2712 − Register Description The frequency of consecutive ALS (CH0) channel results outside of threshold limits are counted; this count value is compared against the APERS value. If the counter is equal to the APERS setting an interrupt is asserted . Any time an ALS (CH0) channel result is inside the threshold values the counter is cleared. CFG0 Register (Address 0x8D) Figure 30: CFG0 Register Addr: 0x8D CFG0 Bit Bit Name Default Access Bit Description 7:4 Reserved 0101 RW Reserved. Must be set to default value.
3 POFFSET_
SCALE 1R W If set to 0, the range of POFFSET and LSB step size is increased by a factor of ~2x 2P W L O N G 0 R W When PWLONG (PROX Wait Long) is asserted the wait period as set by PWTIME is increased by a factor of 12. 1A W L O N G 0 R W When AWLONG (ALS Wait Long) is asserted the wait period as set by AWTIME is increased by a factor of 12. 0 Reserved 0 RW Reserved. Must be set to default value.
Page 24 Datasheet, Public Document Feedback [v4-00] 2023-Jan-02 TMD2712 − Register Description PCFG0 Register (Address 0x8E) Figure 31: PCFG0 Register The PPULSE field sets the maximum number of IR VCSEL pulses that may occur in a proximity cycle. The proximity engine will automatically continue to add IR VCSEL pulses, up to the value set in PPULSE or if a near-s aturation condition occurs if Automatic Pulse Control (APC) is enabled. The dynamic range of the sensor is automatically ad justed to detect distant targets as well as prevent saturation from close targets. This operation also reduces power consumption because proximity integration period is automatically shortened when a target is close to the sensor. If Automatic Pulse Control (APC) is disabled by setting bit 6 in CFG6 to 1, then PPULSE always determines the number of proximity pulses to be transmitted. Addr: 0x8E PCFG0 Bit Bit Name Default Access Bit Description 7:6 PGAIN1 2 (10) RW This field along with the PGAIN2 bits in the CFG1 register, sets the gain of the proximity IR sensor. Value Stage 1 Gain 0 (00) 1x 1 (01) 2x 2 (10) 4x 3 (11) 8x 5:0 PPULSE 15 (001111) RW Maximum number of pulses in a single proximity cycle. Value Maximum Number of Pulses 0 (000000) 1 1 (000001) 2 2 (000010) 3 63 (111111) 64
Datasheet, Public Page 27 [v4-00] 2023-Jan-02 Document Feedback TMD2712 − Register Description CFG1 Register (Address 0x93) Figure 36: CFG1 Register Addr: 0x93 CFG1 Bit Bit Name Default Access Bit Description 7 Reserved 0 RW Reserved. Must be set to default value. 6:5 PGAIN2 3 (11) RW This field along with the PGAIN1 bits in the PCFG0 register, sets the gain of the proximity IR sensor. For optimal noise performance, PGAIN2 = 5x is recommended. Value Stage 2 Gain 0 (00) 2.5x 1 (01) 5x 2 (10) Reserved 3 (11) 10x 4:0 AGAIN 8 (01000) RW This field sets the gain of the ALS sensor. Value ALS Gain 5 (00101) 16x 8 (01000) 128x 11 (01011) 1024x All other values Reserved
Page 28 Datasheet, Public Document Feedback [v4-00] 2023-Jan-02 TMD2712 − Register Description STATUS Register (Address 0x94) Figure 37: STATUS Register All flags in this register can be cleared by setting the bit high. Alternatively, if the INT_READ_CLE AR in the CFG3 register bit is set, then simply reading this register automatically clears all eight flags. ALSL Register (Address 0x95) Figure 38: ALSL Register Addr: 0x94 STATUS Register Bit Bit Name Default Access Bit Description
7 ASAT 0 R, SC Analog saturation flag signals that the ALS results may
be unreliable due to saturation of the AFE. 6P S A T 0 R , S C Proximity saturation flag indicates that an ambient- or reflective-saturation event occurred during a previous proximity cycle. 5P I N T 0 R , S C Proximity interrupt flag indicates that proximity results have exceeded thresholds and persistence settings. 4A I N T 0 R , S C ALS interrupt flag indicates that ALS results (CH0) have exceeded thresholds and persistence settings. 3C I N T 0 R , S C Calibration interrupt flag indicates that calibration has completed. 2Z I N T 0 R , S C Zero detection interrupt flag indicates that a zero value in PDATA has caused the proximity offset to be decremented (if AUTO_OFFSET_ADJ = 1).
1 PSAT_REFLECTIVE 0 R, SC
The Reflective Proximity Saturation Interrupt flag signals that the AFE has saturated during the IR VCSEL active portion of proximity integration.
0 PSAT_AMBIENT 0 R, SC
The Ambient Proximity Saturation Interrupt flag signals that the AFE has saturated during the IR VCSEL inactive portion of proximity integration. Addr: 0x95 ALSL Bit Bit Name Default Access Bit Description 7:0 ALSL 0x00 RO This register contains the low byte of the 16-bit ALS channel (CH0) data.
Datasheet, Public Page 31 [v4-00] 2023-Jan-02 Document Feedback TMD2712 − Register Description SOFTRST Register (Address 0xA8) Figure 45: SOFTRST Register PWTIME Register (Address 0xA9) Figure 46: PWTIME Register The wait timer is implemented using a down counter. Wait time = Increment x 2.78ms. If PWLONG is enabled then Wait time = Increment x 2.78ms x 12. Addr: 0xA8 SOFTRST Bit Bit Name Default Access Bit Description 7:2 Reserved 0 RW Reserved. Must be set to default value.
1 P O R 0 R W
Writing a 1 to this bit will cause a power on reset. This will immediately terminate all device operation and pu t the device into the sleep state. 0S O F T R S T 0 R W Writing a 1 to this bit will cause all registers to be reset to their default state. This will immediately terminate all device operation and put the device into the sleep state. Addr: 0xA9 PWTIME Bit Bit Name Default Access Bit Description 7:0 PWTIME 0x00 RW Value that specifies the wait time in 2.78ms increments. Value Increments Wait Time 0x00 1 2.78ms (33.4ms) 0x01 2 5.56ms (66.7ms) 0x11 18 50.0ms (600ms) 0x23 36 100ms (1.20s) 0x3F 64 178ms (2.14s) 0xFF 256 712ms (8.54s)
Page 32 Datasheet, Public Document Feedback [v4-00] 2023-Jan-02 TMD2712 − Register Description CFG8 Register (Address 0xAA) Figure 47: CFG8 Register CFG3 Register (Address 0xAB) Figure 48: CFG3 Register The SAI bit sets the device operational mode following the completion of an ALS or proximity cycle. If AINT and AIEN are both set or if PINT and PIEN ar e both set, causing an interrupt on the INT pin, and the SAI bit is set, then the oscillator will deactivate. The device will appear as if PON = 0, however, PON will read as 1. The device can only be reactivated (oscillator enabled) by clearing the interrupts in the STATUS register. Addr: 0xAA CFG8 Bit Bit Name Default Access Bit Description 7:0 Reserved 0x2A RW Reserved. Must be set to 0x29. Addr: 0xAB CFG3 Bit Bit Name Default Access Bit Description
7 INT_READ_CLEAR 0 RW If set, then flag bits in the STATUS register will be
reset whenever the STATUS register is read over I²C. 6:5 Reserved 0 RW Reserved. Must be set to default value. 4S A I 0 R W The Sleep After Interrupt bit is used to place the device into a low power mode upon an interrupt pin assertion. PON SAI INT Oscillator 0X X O F F
10 X O N
3:0 Reserved 0001 RW Reserved. Must be set to default value.
Datasheet, Public Page 33 [v4-00] 2023-Jan-02 Document Feedback TMD2712 − Register Description CFG6 Register (Address 0xAE) Figure 49: CFG6 Register POFFSETL Register (Address 0xC0) Figure 50: POFFSETL Register POFFSETH Register (Address 0xC1) Figure 51: POFFSETH Register Typically, optical and/or electrical crosstalk negatively influence proximity operation and results. The POFFSETL/POFFSETH registers provide a mechanism to remove system crosstalk from the proximity data. POFFSETL and POFFSETH contains the magnitud e and sign of a value which adjusts PDATA is generated in the AFE. An offset value in the range of ± 255 is possible. Addr: 0xAE CFG6 Bit Bit Name Default Access Bit Description 7 Reserved 0 RW Reserved. Must be set to default value.
6 APC_
Proximity Automatic Pulse Control (APC) disable. 0 = APC enable 1 = APC disable 5:0 Reserved 111111 RW Reserved. Must be set to default value.Addr: 0xC0 POFFSETL Bit Bit Name Default Access Bit Description 7:0 POFFSETL 0x00 RW This register contains the magnitude portion of proximity offset adjust value. Addr: 0xC1 POFFSETH Bit Bit Name Default Access Bit Description 7:1 Reserved 0 RW Reserved. Must be set to default value. 0P O F F S E T H 0 R W This register contains the sign portion of proximity offset adjust value.
Page 34 Datasheet, Public Document Feedback [v4-00] 2023-Jan-02 TMD2712 − Register Description CALIB Register (Address 0xD7) Figure 52: CALIB Register Proximity response in systems with electrical and optical crosstalk may be improved by using the calibration feature. Optical crosstalk is caused when the photodiode receives a portion of the VCSEL IR which wa s unintentionally reflected by a surface other than the target. Electrical offset is caused by electrical disturbance in the sensor AFE, and also influences the proximity result. The calibratio n routine adjusts the value in POFFSETL/H until the proximity resu lt is as close to the binary search target as possible. Optical and electrical calibration function identically, except that during an electrical calibration the proximity photodiode is disconnected from the AFE. An electrical calibration can be initiated anytime by setting the ELECTRICAL_CALIBRATION and START_OFFSET_CAL bits. To perform an optical (and electrical) calibration do not set the ELECTRICAL_CALIBRATION bi t when setting the START_ OFFSET_CALIB. The CINT flag will assert after calibration has finished. Upon completion proximity offset registers are automatically loaded with calibration result. Addr: 0xD7 CALIB Bit Bit Name Default Access Bit Description 7C A L A V G 0 R W Enables proximity hardware averaging as selected with PROX_AVG during calibration. 0 = No hardware averaging 1 = Hardware averaging enabled 6 Reserved 0 RW Reserved. Must be set to default value.
5 ELECTRICAL_
Selects proximity calibration type. 0 = Electrical and optical crosstalk. 1 = Electrical crosstalk only. 4C A L P R A T E 0 R W Enables PRATE during calibration. Useful when averaging is enabled. 0 = PRATE ignored 1 = PRATE applied between averaging samples 3:1 Reserved 0 RW Reserved. Must be set to default value. 0 START_OFFSET_CAL 0 RW Set to 1 to start a calibration sequence.
Datasheet, Public Page 35 [v4-00] 2023-Jan-02 Document Feedback TMD2712 − Register Description CALIB_OFFSET Register (Address 0xD8) Figure 53: CALIB_OFFSET Register For applications with high optical proximity crosstalk (the emitted IR optical signal appears at the IR sensor), the offset range can be extended in discrete steps. To determine the best range extension step for the appl ication, a proximity calibration cycle is initiated and the resulting proximity offset is captured in the POFFSETL/H registers. Addr: 0xD8 CALIB_OFFSET Bit Bit Name Default Access Bit Description 7:6 Reserved 0 RW Reserved. Must be set to default value.
5 EN_RANGE_
Setting this bit to a 1 enables the proximity offset range extension functionality. See the OFFSET_RANGE_ EXTENSION bits. If this bit is set to 0, the offset range extension is disabled. 4:0 OFFSET_ RANGE_ EXTENSION (00000) RW Offset range extension selection. Value Selection 0 (00000) Nominal 1 (00001) Nominal + 1 Step 2 (00010) Nominal + 2 Steps 3 (00011) Nominal + 3 Steps Nominal + (Value) Steps 31 (11111) Nominal + 31 Steps
Page 36 Datasheet, Public Document Feedback [v4-00] 2023-Jan-02 TMD2712 − Register Description CALIBCFG Register (Address 0xD9) Figure 54: CALIBCFG Register The binary search target field is used by the calibration feature to set the baseline value for PDATA when no target is present. For example, calibration of a device in open air, with no target, and BINSEARCH_TARGET setting of 2 causes the PDATA value to be approximately 15 counts. This feature is useful because it forces PDATA result to always be above zero. Addr: 0xD9 CALIBCFG Bit Bit Name Default Access Bit Description 7:5 BINSRCH_ TARGET (010) RW Proximity offset calibration result target. Value PDATA Target 0 (000) 3 1 (001) 7 2 (010) 15 3 (011) 31 4 (100) 63 5 (101) 127 6 (110) 255 7 (111) 511 4 Reserved 1 RW Reserved. Must be set to default value.
3 AUTO_OFFSET_
ADJ 0R W If set, this bit causes the value in POFFSETL register to be decremented if PDATA ever becomes zero. 2:0 PROX_AVG 0 (000) RW PROX_AVG defines the number of ADC samples collected and hardware averaged during a proximity cycle. Value Sample Size 0 (000) Disable 1 (001) 2 2 (010) 4 3 (011) 8 4 (100) 16 All other values Reserved
Datasheet, Public Page 37 [v4-00] 2023-Jan-02 Document Feedback TMD2712 − Register Description The PROX_AVG field sets the number of ADC samples that are averaged. Each ADC sample causes the programmed number of proximity pulses to be transmitted. Once all samples have been completed and the average is calculated, the proximity state machine will then pass this value directly to PDATA. CALIBSTAT Register (Address 0xDC) Figure 55: CALIBSTAT Register INTENAB Register (Address 0xDD) Figure 56: INTENAB Register Addr: 0xDC CALIBSTAT Bit Bit Name Default Access Bit Description 7:3 Reserved 0 R Reserved. Must be set to default value.
2 OFFSET_
Bit is set when the proximity offset has been automatically decremented if AUTO_OFFSET_ ADJ = 1 (see CALIBCFG register). This bit can be cleared by writing 1 to it or setting AUTO_ OFFSET_ADJ to 0. 1 Reserved 0 R Reserved. Must be set to default value.
0 CALIB_FINISHED 0 R
This flag indicates that calibration has finished. This bit is a copy of the CINT bit in the STATUS register. It will be cleared when the CINT bit is cleared. Addr: 0xDD INTENAB Bit Bit Name Default Access Bit Description 7 ASIEN 0 RW ALS Saturation Interrupt Enable. 6 PSIEN 0 RW Proximity Saturation Interrupt Enable. 5 PIEN 0 RW Proximity Interrupt Enable. 4 AIEN 0 RW ALS Interrupt Enable. 3 CIEN 0 RW Calibration Interrupt Enable. 2 ZIEN 0 RW Zero Detect Interrupt Enable. 1:0 Reserved 0 RW Reserved. Must be set to default value.
Datasheet, Public Page 39 [v4-00] 2023-Jan-02 Document Feedback TMD2712 − Application Information Schematic Figure 60: Typical Applications Circuit Note(s): 1. Place the 2.2μF VDD (C1) and 2.2μF VDD3 (C2) capacitors within 5mm of the module. 2. The value of the I²C pull up resistors (R PU) should be based on the 1.8V bus voltag e, system bus speed and trace capacitance. 3. C1 and C2 are critical comp onents to protect the device during high voltage ESD strikes. 4. In systems subjected to high voltage ESD strikes, it is reco mmended to connect VDD to a host GPIO pin to allow the device to be independently power cycled.
Application Information
2.2µF VDD VDD3 GND 22ȍ1.8V 3.0V RPU RPU 10Kȍ 2.2µF
Page 40 Datasheet, Public Document Feedback [v4-00] 2023-Jan-02 TMD2712 − Application Information Recommended Circuit Layout Figure 61: With INT Pin Operational Note(s): 1. The dominant factor governing device performance is the comp onent placement, not necessarily component value. The placement of the decoupling capacitor, C1, is the most critical. Place the component on the same side of PCB as device as shown in the fi gure above. Make connection as close as possible to minimize series inductance and resi stance. This is critical. With INT pin operational With INT pin tied to GND
Datasheet, Public Page 41 [v4-00] 2023-Jan-02 Document Feedback TMD2712 − Package Drawings & Markings Figure 62: Package Drawings Note(s): 1. All linear dimensions are in millimeters. 2. Dimension tolerances are 0.05mm unless otherwise noted. 3. Contact finish is Au. 4. This package contains no lead (Pb). 5. This drawing is subject to change without notice. Package Drawings & Markings GreenRoHS 3$57&/ 72$/6,5&/ 3$57&/ 72352;&/ 3$57('*(72352;&/ 3$57&/ 72352;&/ 3$57&/ 72$/6&/ 3$57&/ 72,5&/ 352;,0,7< $/6,5 (0,77(5&(17(5 6'$ 6&/ 9'' 9'' *1' ,17 '(9,&(3,1287 %277209,(: 0 & $% 0 & $%
Page 42 Datasheet, Public Document Feedback [v4-00] 2023-Jan-02 TMD2712 − Package Drawings & Markings Recommended PCB Pad Layout Suggested PCB pad layout guidelines for the surface mount module are shown. Flash Gold is recommended as a surface finish for the landing pads. Figure 63: Recommended PCB Pad Layout Note(s): 1. All linear dimensions are in millimeters. 2. Dimension tolerances are 0.05mm unless otherwise noted. 3. Contact finish is Au. 4. This drawing is subject to change without notice.
Datasheet, Public Page 43 [v4-00] 2023-Jan-02 Document Feedback TMD2712 − Tape & Reel Information Figure 64: Tape and Reel Information Note(s): 1. All linear dimensions are in millimeters. Di mension tolerance is ±0.1 0mm unless otherwise noted. 2. The dimensions on this drawing are for illustrative purpos es only. Dimensions of an actual carrier may vary slightly. 3. Symbols on drawing Ao, Bo, and Ko are defined in ANSI EIA Standard 481-B 2001. 4. ams OSRAM packaging tape and reel conform to the requirements of EIA Standard 481-B. 5. In accordance with EIA standard device pin 1 is located next to the sprocket holes in the tape. 6. This drawing is subject to change without notice. Tape & Reel Information
Page 44 Datasheet, Public Document Feedback [v4-00] 2023-Jan-02 TMD2712 − Soldering & Storage Information The module has been tested an d has demonstrated an ability to be reflow soldered to a PCB substrate. The solder reflow profile describes the expected maximum heat exposure of components during the solder reflow process of product on a PCB. Temperature is measured on top of component. The components should be limited to a maximum of three passes through this solder reflow profile. Figure 65: Solder Reflow Profile Note(s): 1. Tolerance for peak profile temperature (TP) is defined as a supplier minimum and a user maximum. Profile Feature Preheat/ Soak Sn-Pb Eutectic Assembly Pb-Free Assembly Temperature Min ( Tsmin) 100 °C 150 °C Temperature Max ( Tsmax) 150 °C 200 °C Time (ts) from (Tsmin to Tsmax) 60-120 seconds 60-120 seconds Ramp-up rate (TL to TP) 3 °C/second max. 3 °C/second max. Liquidous temperature (TL) Time (tL) maintained above TL 183 °C 60-150 seconds 217 °C 60-150 seconds Peak package body temperature (TP) For users TP must not exceed the classification temp. of 235 °C. For suppliers TP must equal or exceed the classification temp. of 235 °C For users TP must not exceed the classification temp. of 260 °C. For suppliers TP must equal or exceed the classification temp. of 260 °C Time (tP) (1) within 5 °C of the specified classification temperature (Tc) 20 (1)seconds 30 (1)seconds Ramp-down rate (TP to TL) 6 °C/second max. 6 °C/second max. Time 25 °C to peak temperature 6 minutes max. 8 minutes max. Soldering & Storage Information
Datasheet, Public Page 45 [v4-00] 2023-Jan-02 Document Feedback TMD2712 − Soldering & Storage Information Figure 66: Solder Reflow Profile Graph Storage Information Moisture Sensitivity Optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previously absorbed into the package. To ensure the package contains the smallest amount of absorbed mois ture possible, each device is baked prior to being dry packed for shipping. Devices are dry packed in a sealed aluminized envelope called a moisture-barrier bag with sili ca gel to protect them from ambient moisture during shipping, handling, and storage before use. Shelf Life The calculated shelf life of the device in an unopened moisture barrier bag is 24 months from the date code on the bag when stored under the following conditions:
- Shelf Life: 24 months
- Ambient Temperature: <40°C
- Relative Humidity: <90% Rebaking of the devices will be required if the devices exceed the 24 months shelf life or the Humidity Indicator Card shows that the devices were exposed to conditions beyond the allowable moisture region. Not to Scale – For Reference Only TP Temperature (°C) Time (seconds) tL TL TC - 5°C tP Tsmin Tsmax Preheat Area Max Ramp Up Rate = 3°C/s Max Ramp Down Rate = 6°C/s
Page 46 Datasheet, Public Document Feedback [v4-00] 2023-Jan-02 TMD2712 − Soldering & Storage Information Floor Life The module has been assigned a moisture sensitivity level of MSL 3. As a result, the floor life of devices removed from the moisture barrier bag is 168 hours from the time the bag was opened, provided that the devices are stored under the following conditions:
- Floor Life: 168 hours
- Ambient Temperature: <30°C
- Relative Humidity: <60% If the floor life or the temperature/humidity conditions have been exceeded, the devices must be rebaked prior to solder reflow or dry packing. Rebaking Instructions When the shelf life or floor life limits have been exceeded, rebake at 50°C for 12 hours. Laser Eye Safety The TMD2712 is designed to meet the Class 1 laser safety limits including single faults in compliance with IEC/EN 60825-1:2014. In an end application system environment, the system may need to be tested to ensure it remains compliant. The system must not include any additional lens to concentrate the laser light or parameters set outsid e of the recommended operating conditions or any physical modification to the module during development could result in hazardous levels of radiation exposure.
Datasheet, Public Page 47 [v4-00] 2023-Jan-02 Document Feedback TMD2712 − Ordering & Contact Information Figure 67:
Ordering Information
Buy our products or get free samples online at: www.ams.com/Products Technical Support is available at: www.ams.com/Technical-Support Provide feedback about this document at: www.ams.com/Document-Feedback For further information and requests, e-mail us at: ams_sales@ams.com For sales offices, distributors and representatives, please visit: www.ams.com/Contact Headquarters ams-OSRAM AG Tobelbader Strasse 30
8141 Premstaetten
Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com Ordering Code I²C Bus I²C Address Delivery Form Delivery Quantity TMD27123 1.8V 0x39 Tape & Reel (13”) 10000 pcs/reel TMD27123M Tape & Reel (7”) 1000 pcs/reel Ordering & Contact Information
Page 48 Datasheet, Public Document Feedback [v4-00] 2023-Jan-02 TMD2712 − RoHS Compliant & ams Green Statement RoHS: The term RoHS compliant means that ams-OSRAM AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories plus additional 4 substance categories (per amendment EU 2015/863), including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes. ams Green (RoHS compliant and no Sb/Br/Cl): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) and do not contain Chlorine (Cl not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams-OSRAM AG knowledge and belief as of the date that it is provided. ams-OSRAM AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams-OSRAM AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams-OSRAM AG and ams-OSRAM AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. RoHS Compliant & ams Green Statement
Datasheet, Public Page 49 [v4-00] 2023-Jan-02 Document Feedback TMD2712 − Copyrights & Disclaimer Copyright ams-OSRAM AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ams-OSRAM AG are covered by the warranty and patent indemnification provis ions appearing in its General Terms of Trade. ams-OSRAM AG makes no warranty, express, statutory, implied, or by desc ription regarding the information set forth herein. ams-OSRAM AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams-OSRAM AG for current information. This product is intended for use in commercial applications. Applications re quiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams-OSRAM AG for each application. This product is provided by ams-OSRAM AG “AS IS” and any express or implied wa rranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams-OSRAM AG shall not be liable to recipient or any third party for any damages, including but no t limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams-OSRAM AG rendering of technical or other services. Copyrights & Disclaimer
Page 50 Datasheet, Public Document Feedback [v4-00] 2023-Jan-02 TMD2712 − Document Status Document Status Product Status Definition Product Preview Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Datasheet Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams-OSRAM AG standard warranty as given in the General Terms of Trade Datasheet (discontinued) Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams-OSRAM AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Document Status
Datasheet, Public Page 51 [v4-00] 2023-Jan-02 Document Feedback TMD2712 − Revision Information Note(s): 1. Page and figure numbers for the previous version may diff er from page and figure numbers in the current revision. 2. Correction of typographical er rors is not explicitly mentioned. Changes from 3-00 (2022-Jul-07) to current revision 4-00 (2023-Jan-02) Page Updated “Shelf Life” to 24 months 45 Revision Information
Page 52 Datasheet, Public Document Feedback [v4-00] 2023-Jan-02 TMD2712 − Content Guide
1 General Description
1 Key Benefits & Features
2 Applications
2 Block Diagram
3 Pin Assignments
4A b s o l u t e M a x i m u m R a t i n g s
5 Electrical Characteristics
8 Typical Operating Characteristics
10 Detailed Description
10 Proximity
10 Ambient Light Sensing, ALS
11 Operational State Diagram
12 I²C Characteristics
12 I²C Write Transaction
12 I²C Read Transaction
13 Timing Diagrams
14 Register Description
16 Detailed Register Description
16 Enable Register (Address 0x80)
17 ATIME Register (Address 0x81)
17 PRATE Register (Address 0x82)
18 AWTIME Register (Address 0x83)
18 AILTL Register (Address 0x84)
18 AILTH Register (Address 0x85)
19 AIHTL Register (Address 0x86)
19 AIHTH Register (Address 0x87)
20 PILTL Register (Address 0x88)
20 PILTH Register (Address 0x89)
21 PIHTL Register (Address 0x8A)
21 PIHTH Register (Address 0x8B)
22 PERS Register (Address 0x8C)
23 CFG0 Register (Address 0x8D)
24 PCFG0 Register (Address 0x8E)
25 PCFG1 Register (Address 0x8F)
25 PCFG2 Register (Address 0x90)
26 REVID Register (Address 0x91)
26 ID Register (Address 0x92)
27 CFG1 Register (Address 0x93)
28 STATUS Register (Address 0x94)
28 ALSL Register (Address 0x95)
29 ALSH Register (Address 0x96)
29 IRL Register (Address 0x97)
29 IRH Register (Address 0x98)
29 PDATAL Register (Address 0x99)
30 PDATAH Register (Address 0x9A)
30 REVID2 Register (Address 0xA6)
31 SOFTRST Register (Address 0xA8)
31 PWTIME Register (Address 0xA9)
32 CFG8 Register (Address 0xAA)
32 CFG3 Register (Address 0xAB)
33 CFG6 Register (Address 0xAE)
Datasheet, Public Page 53 [v4-00] 2023-Jan-02 Document Feedback TMD2712 − Content Guide