TLV8x3 3-Pin Voltage Supervisors with Active-Low, Open-Drain Reset datasheet (Rev. E)
Document overview
- Manufacturer or author: Texas Instruments, Incorporated [SBVS157,E]
- PDF pages: 25
Technical content
TLV8x3 3-Pin Voltage Supervisors with Active-Low, Open-Drain Reset
1 Features
- 3-Pin SOT23 Package
- Supply Current: 9 µA (Typical)
- Precision Supply Voltage Monitor: 2.5 V, 3 V, 3.3 V, 5 V
- Power-On Reset Generator with Fixed Delay Time of 200 ms
- Pin-for-Pin Compatible with MAX803
- Temperature Range: –40°C to +125°C
- Open-Drain, RESET Output
2 Applications
- Factory Automation
- Portable and Battery-Powered Equipment
- Set-Top Boxes
- Servers
- Appliances
- Electricity Meters
- Building Automation
3 Description
The TLV8x3 family of supervisory circuits provides circuit initialization and timing supervision, primarily for DSPs and processor-based systems. The TLV803, TLV853, and TLV863 are functionally equivalent. The TLV853 and TLV863 provide an alternate pinout of the TLV803. The newer TLV803E device is a pin-to-pin alternative to all of these 3. During power on, RESET asserts when the supply voltage (V DD) exceeds 1.1 V. Thereafter, the supervisory circuit monitors V DD and keeps RESET active as long as V DD remains below the threshold voltage VIT. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time (t d(typ) = 200 ms) starts after V DD exceeds the threshold voltage, V IT. When the supply voltage drops below the V IT threshold voltage, the output is active (low) again. All the devices in this family have a fixed sense-threshold voltage (VIT) set by an internal voltage divider. The product spectrum is designed for supply voltages of 2.5 V, 3 V, 3.3 V, and 5 V. These devices are available in a 3-pin SOT-23 package. The TLV803 devices are characterized for operation over a temperature range of –40°C to +125°C. Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) TLV8x3 SOT-23 (3) 2.92 mm × 1.30 mm (1) For all available packages, see the package option addendum at the end of the data sheet. 3.3□V TL V803S DSP/FPGA/ASIC GND GND RESET RESET VDD 3.3-V□LDO GND OUTIN5□V VDD Typical Application www.ti.com TLV803, TLV853, TLV863 SBVS157E – APRIL 2011 – REVISED DECEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 1 Product Folder Links: TLV803 TLV853 TLV863 TLV803, TLV853, TLV863 SBVS157E – APRIL 2011 – REVISED DECEMBER 2020 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
13 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (November 2020) to Revision E (December 2020) Page Changes from Revision C (September 2015) to Revision D (November 2020) Page Changes from Revision B (August 2011) to Revision C (September 2015) Page
- Changed device part numbers shown on page header to show single TLV803 device instead of lettered-
- Added Detailed Description, Application and Implementation, Power-Supply Recommendations, Layout,
- Changed "free-air temperature" to "junction temperature" in Absolute Maximum Ratings condition statement ..
- Changed "free-air temperature" to "junction temperature" in Electrical Characteristics condition statement .... 6 TLV803, TLV853, TLV863 SBVS157E – APRIL 2011 – REVISED DECEMBER 2020 www.ti.com
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Changes from Revision A (June 2011) to Revision B (August 2011) Page www.ti.com TLV803, TLV853, TLV863 SBVS157E – APRIL 2011 – REVISED DECEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TLV803 TLV853 TLV863
5 Device Comparison
Table 5-1. Device Threshold Options DEVICE THRESHOLD VOLTAGE TLV803Z 2.25 V TLV803R 2.64 V TLV803S 2.93 V TLV803M 4.38 V TLV853M 4.38 V TLV863M 4.38 V Table 5-2. Device Family Comparison DEVICE FUNCTION TLV803 Open-Drain, RESET Output TLV809 Push-Pull, RESET Output TLV810 Push-Pull, RESET Output
6 Pin Configuration and Functions
Figure 6-1. TLV803: DBZ Package 3-Pin SOT-23 Top View VDD GND RESET Figure 6-2. TLV853: DBZ Package 3-Pin SOT-23 Top View VDD GND RESET Figure 6-3. TLV863: DBZ Package 3-Pin SOT-23 Top View Pin Functions PIN I/O DESCRIPTION NAME TLV803 TLV853 TLV863 GND 1 2 3 — Ground pin. RESET 2 1 1 O RESET is an open-drain output that is driven to a low impedance state when RESET is asserted. RESET remains low (asserted) for the delay time (td) after VDD exceeds VIT–. Use a 10-kΩ to 1-MΩ pullup resistor on this pin. The pullup voltage is not limited by VDD. VDD 3 3 2 I Supply voltage pin. It is good analog design practice to place a 0.1-µF ceramic capacitor close to this pin. TLV803, TLV853, TLV863 SBVS157E – APRIL 2011 – REVISED DECEMBER 2020 www.ti.com
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating junction temperature range (unless otherwise noted) MIN MAX UNIT Voltage VDD(2) 0 6.5 V All other pins(2) –0.3 +6.5 Current Maximum low output current, IOL 5 mA Maximum high output current, IOH –5 Input clamp current, IIK (VI < 0 or VI > VDD) ±20 Output clamp current, IOK (VO < 0 or VO > VDD) ±20 Temperature Operating junction temperature range, TJ –40 125 Storage temperature range, Tstg –65 150 (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to GND. For reliable operation the device should not be operated at 6.5 V for more than t = 1000h continuously
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Thermal Information
THERMAL METRIC(1) TLV8x3 UNITSDBZ (SOT-23)
3 PINS
RθJA Junction-to-ambient thermal resistance 328.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 135.4 °C/W RθJB Junction-to-board thermal resistance 58.3 °C/W ψJT Junction-to-top characterization parameter 5.2 °C/W ψJB Junction-to-board characterization parameter 59.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.4 Recommended Operating Conditions
at specified temperature range (unless otherwise noted) MIN MAX UNIT VDD Supply voltage 1.1 6 V TJ Operating junction temperature –40 125 °C www.ti.com TLV803, TLV853, TLV863 SBVS157E – APRIL 2011 – REVISED DECEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TLV803 TLV853 TLV863
7.5 Electrical Characteristics
over recommended operating junction temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOL Low-level output voltage VDD = 2 V to 6 V, IOL = 500 µA 0.3 VVDD = 3.3 V, IOL = 2 mA 0.4 VDD = 6 V, IOL = 4 mA 0.4 Power-up reset voltage(1) IOL = 50 µA, VOL < 0.2 V 1.1 V VIT– Negative-going input threshold voltage(2) TLV803Z TJ = – 40°C to +125°C 2.20 2.25 2.30 V TLV803R 2.58 2.64 2.70 TLV803S 2.87 2.93 2.99 TLV8x3M 4.28 4.38 4.48 Vhys Hysteresis TLV803Z TJ = 25°C, IOL = 50 µA mV TLV803R 35 TLV803S 40 TLV8x3M 60 IDD Supply current VDD = 2 V, output unconnected 9 15 µA VDD = 6 V, output unconnected 20 30 IOH Output leakage current VDD = 6 V 350 nA (1) The lowest supply voltage at which RESET becomes valid. tr,VDD ≤ 66.7 V/ms. (2) To ensure best stability of the threshold voltage, place a bypass capacitor (0.1-µF ceramic) near the supply terminals.
7.6 Switching Characteristics
over operating temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tw Pulse duration at VDD VDD = 1.08 VIT– to 0.92 VIT– 10 µs td Delay time VDD ≥ VIT– + 0.2 V; see Timing Diagram 120 200 280 ms td td t 0 t RESET DD RESET 1.1□V VDD VIT/c45 Figure 7-1. Timing Diagram TLV803, TLV853, TLV863 SBVS157E – APRIL 2011 – REVISED DECEMBER 2020 www.ti.com
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7.7 Typical Characteristics
at TJ = 25°C, VIT– = 4.38 V, and VDD = 5.0 V (unless otherwise noted) 1.2 0.8 0.6 0.4 0.2 V (V) OL 0 1 2 3 4 I (mA)OL +125 C/c176 +85 C/c176 +25 C/c176
0 C/c176
/c45 /c176 40 C V =□2.5□VDD Figure 7-2. Low-Level Output Voltage vs Low-Level Output Current I ( A /c109 DD 0 1 2 3 5 V (V)DD +125 C/c176 +85 C/c176 +25 C/c176 /c45 /c176 40 C Figure 7-3. Supply Current vs Supply Voltage 1.001 0.999 0.998 0.997 0.996 0.995 0.994 Normalized□V (V) IT /c45 /c45 40 /c45 25 /c45 10 5 20 35 50 65 80 95 110 T emperature□( C)/c176 125 Figure 7-4. Normalized to 25°C Negative-Going Input Threshold Voltage vs Temperature 220 210 200 190 180 170 160 t (ms)d /c45 40 /c45 25 /c45 10 5 20 35 50 65 80 95 110 T emperature□( C)/c176 125 TL V803M TL V803Z Figure 7-5. Delay Time vs Temperature 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 V (V) OL 0 0.25 0.5 0.75 1.25 V (V)DD 1.51 +125 C/c176 +85 C/c176 +25 C/c176 /c45 /c176 40 C RESET Pulled□Up□to□V with□22.1-k Resistor DD /c87 Figure 7-6. Power-Up Low-Level Output Voltage vs Supply Voltage www.ti.com TLV803, TLV853, TLV863 SBVS157E – APRIL 2011 – REVISED DECEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TLV803 TLV853 TLV863
8 Detailed Description
8.1 Overview
The TLV803 family of supervisory circuits provides circuit initialization and timing supervision. The TLV853 and TLV863 are both functionally equivalent to the TLV803. These devices output a logic low whenever V DD drops below the negative-going threshold voltage (V IT–). The output, RESET, remains low for approximately 200 ms after the VDD voltage exceeds the positive-going threshold voltage (V IT– + Vhys). These devices are designed to ignore fast transients on the VDD pin.
8.2 Functional Block Diagram
of 1.137 V Reset Logic Timer
8.3 Feature Description
8.3.1 VDD Transient Rejection
The TLV803 has built-in rejection of fast transients on the V DD pin. The rejection of transients depends on both the duration and the amplitude of the transient. The amplitude of the transient is measured from the bottom of the transient to the negative threshold voltage of the TLV803, as shown in Figure 8-1. VDD T ransient Amplitude Duration VIT/c45 tw Figure 8-1. Voltage Transient Measurement The TLV803 does not respond to transients that are fast duration/low amplitude or long duration/small amplitude. Transients meeting or longer than the tw specified in the switching characteristics section triggers a reset. TLV803, TLV853, TLV863 SBVS157E – APRIL 2011 – REVISED DECEMBER 2020 www.ti.com
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8.3.2 Reset During Power Up and Power Down
The TLV803 output is valid when V DD is greater than 1.1 V. When V DD is less than 1.1 V, the output transistor turns off and becomes high impedance. The voltage on the RESET pin rises to the voltage level connected to the pull-up resistor. Figure 8-2 shows a typical waveform for power-up, assuming the RESET pin has a pull-up resistor connected to the VDD pin. RESET VDD td V +□VIT HYS/c45 1.1□V Valid□Output Figure 8-2. Power-Up Response
8.3.3 Bidirectional Reset Pins
Some microcontrollers have bidirectional reset pins that act as both inputs and outputs. In a situation where the TLV803 is pulling the RESET line low while the microcontroller is trying the force the RESET line high, a series resistor should be placed between the output of the TLV803 and the RESET pin of the microcontroller to protect against excessive current flow. Figure 8-3 shows the connection of the TLV803 to a microcontroller using a series resistor to drive a bidirectional RESET line. 100□k/c87 TL V803S VDD 3.3□V RESET GND 47□k/c87 RST Microprocessor VCC Figure 8-3. Connection To Bidirectional Reset Pin
8.4 Device Functional Modes
8.4.1 Normal Operation (VDD > Power-Up Reset Voltage)
When the voltage on VDD is greater than 1.1 V, the RESET signal asserts when V DD is less than V IT– and deasserts when VDD is greater thanVIT–.
8.4.2 Power On Reset (VDD < Power-Up Reset Voltage)
When the voltage on VDD is lower than the required voltage to internally pull the asserted output to GND (power-up reset voltage), both outputs are in a high-impedance state. www.ti.com TLV803, TLV853, TLV863 SBVS157E – APRIL 2011 – REVISED DECEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TLV803 TLV853 TLV863
9 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Monitoring Multiple Supplies
Because the TLV803 has an open-drain output, multiple TLV803 outputs can be directly tied together to form a logical OR-ing function for the RESET line. Only one pull-up resistor is required for this configuration. Figure 9-1 shows two TLV803s connected together to provide monitoring of a 3.3-V power rail and a 5.0-V power rail. A reset is generated if either power rail falls below the threshold voltage of its corresponding TLV803. GND VDD RESET RST TL V803M Microprocessor 100□k/c87 0.1 /c109F 5.0□V GND VDD RESET TL V803S 0.1 /c109F 3.3□V VIO VCORE 3.3□V Figure 9-1. Multiple Voltage Rail Monitoring
9.1.2 Output Level Shifting
The RESET output of the TLV803 can be pulled to a maximum voltage of 6 V and can be pulled higher in voltage than VDD. It is useful to provide level shifting of the output for cases where the monitored voltage is less than the useful logic levels of the load. Figure 9-2 shows the TLV803Z used to monitor a 2.5-V power rail, with a logic RESET input to a microprocessor that is connected to 5.0 V and has 5.0-V logic levels. TLV803, TLV853, TLV863 SBVS157E – APRIL 2011 – REVISED DECEMBER 2020 www.ti.com
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10□k/c87 0.1 /c109F 2.5□V 5.0□V Figure 9-2. Output Voltage Level Shifting
9.2 Typical Application
Figure 9-3 shows TLV803S being used to monitor the supply rail for a DSP, FPGA, or ASIC. 3.3□V TL V803S DSP/FPGA/ASIC GND GND RESET RESET VDD 3.3-V□LDO GND OUTIN5□V VDD Figure 9-3. Typical Application
9.2.1 Design Requirements
This design calls for a 3.3-V rail to be monitored. The design resets if the supply rail falls below 2.93 V. The output must satisfy 3.3-V CMOS logic.
9.2.2 Detailed Design Procedure
Select the TLV803S to satisfy the voltage threshold requirement. Place a pullup resistor on RESET to VDD in order to satisfy the output logic requirement. www.ti.com TLV803, TLV853, TLV863 SBVS157E – APRIL 2011 – REVISED DECEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TLV803 TLV853 TLV863
9.2.3 Application Curves
1.2 0.8 0.6 0.4 0.2 V (V) OL 0 1 2 3 4 I (mA)OL +125 C/c176 +85 C/c176 +25 C/c176 /c45 /c176 40 C V =□2.5□VDD Figure 9-4. Low-Level Output Voltage vs Low-Level Output Current
10 Power Supply Recommendations
These devices are designed to operate from an input voltage supply range between 1.1 V and 6 V. TLV803, TLV853, TLV863 SBVS157E – APRIL 2011 – REVISED DECEMBER 2020 www.ti.com
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11 Layout
11.1 Layout Guidelines
Place the CIN decoupling capacitor close to the device.
11.2 Layout Example
Figure 11-1. Layout Example (DBZ Package) www.ti.com TLV803, TLV853, TLV863 SBVS157E – APRIL 2011 – REVISED DECEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TLV803 TLV853 TLV863
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TLV803. The TLV803SEVM-019 evaluation module (and related user guide ) can be requested at the Texas Instruments website through the product folders or purchased directly from the TI eStore.
12.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. SPICE models for the TLV803, TLV853, and TLV863 are available through the respective device product folders under Tools & Software.
12.2 Documentation Support
12.2.1 Related Documentation
- TLV803SEVM-019 User's Guide. Literature number SLVU461.
12.3 Related Links
Table 12-1 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 12-1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY TLV803 Click here Click here Click here Click here Click here TLV853 Click here Click here Click here Click here Click here TLV863 Click here Click here Click here Click here Click here
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TLV803, TLV853, TLV863 SBVS157E – APRIL 2011 – REVISED DECEMBER 2020 www.ti.com
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12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TLV803, TLV853, TLV863 SBVS157E – APRIL 2011 – REVISED DECEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TLV803 TLV853 TLV863
www.ti.com 15-Jul-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TLV803MDBZR Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAU | SN | NIPDAUAG Level-1-260C-UNLIM -40 to 125 VOUQ TLV803MDBZR.A Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 VOUQ TLV803MDBZT Active Production SOT-23 (DBZ) | 3 250 | SMALL T&R Yes NIPDAU | SN | NIPDAUAG Level-1-260C-UNLIM -40 to 125 VOUQ TLV803MDBZT.A Active Production SOT-23 (DBZ) | 3 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 VOUQ TLV803RDBZR Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAU | SN | NIPDAUAG Level-1-260C-UNLIM -40 to 125 VOSQ TLV803RDBZR.A Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 VOSQ TLV803RDBZRG4 Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 VOSQ TLV803RDBZRG4.A Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 VOSQ TLV803RDBZT Active Production SOT-23 (DBZ) | 3 250 | SMALL T&R Yes NIPDAU | SN | NIPDAUAG Level-1-260C-UNLIM -40 to 125 VOSQ TLV803RDBZT.A Active Production SOT-23 (DBZ) | 3 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 VOSQ TLV803SDBZR Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAU | SN | NIPDAUAG Level-1-260C-UNLIM -40 to 125 VOTQ TLV803SDBZR.A Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 VOTQ TLV803SDBZRG4 Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 VOTQ TLV803SDBZRG4.A Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 VOTQ TLV803SDBZT Active Production SOT-23 (DBZ) | 3 250 | SMALL T&R Yes NIPDAU | SN | NIPDAUAG Level-1-260C-UNLIM -40 to 125 VOTQ TLV803SDBZT.A Active Production SOT-23 (DBZ) | 3 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 VOTQ TLV803ZDBZR Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAU | SN | NIPDAUAG Level-1-260C-UNLIM -40 to 125 VORQ TLV803ZDBZR.A Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 VORQ TLV803ZDBZT Active Production SOT-23 (DBZ) | 3 250 | SMALL T&R Yes NIPDAU | SN | NIPDAUAG Level-1-260C-UNLIM -40 to 125 VORQ TLV803ZDBZT.A Active Production SOT-23 (DBZ) | 3 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 VORQ TLV853MDBZR Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 ZGM4 TLV853MDBZR.A Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 ZGM4 TLV853MDBZT Active Production SOT-23 (DBZ) | 3 250 | SMALL T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 ZGM4 Addendum-Page 1
www.ti.com 15-Jul-2026 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TLV853MDBZT.A Active Production SOT-23 (DBZ) | 3 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 ZGM4 TLV863MDBZR Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAU | SN | NIPDAUAG Level-1-260C-UNLIM -40 to 125 VTWM TLV863MDBZR.A Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 VTWM TLV863MDBZT Active Production SOT-23 (DBZ) | 3 250 | SMALL T&R Yes NIPDAU | SN | NIPDAUAG Level-1-260C-UNLIM -40 to 125 VTWM TLV863MDBZT.A Active Production SOT-23 (DBZ) | 3 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 VTWM (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 20-May-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 20-May-2026 Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 20-May-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV803MDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0 TLV803MDBZR SOT-23 DBZ 3 3000 210.0 185.0 35.0 TLV803MDBZT SOT-23 DBZ 3 250 210.0 185.0 35.0 TLV803MDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0 TLV803RDBZR SOT-23 DBZ 3 3000 210.0 185.0 35.0 TLV803RDBZRG4 SOT-23 DBZ 3 3000 210.0 185.0 35.0 TLV803RDBZT SOT-23 DBZ 3 250 210.0 185.0 35.0 TLV803RDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0 TLV803SDBZR SOT-23 DBZ 3 3000 210.0 185.0 35.0 TLV803SDBZRG4 SOT-23 DBZ 3 3000 210.0 185.0 35.0 TLV803SDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0 TLV803ZDBZR SOT-23 DBZ 3 3000 210.0 185.0 35.0 TLV803ZDBZT SOT-23 DBZ 3 250 210.0 185.0 35.0 TLV803ZDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0 TLV853MDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0 TLV853MDBZR SOT-23 DBZ 3 3000 210.0 185.0 35.0 TLV853MDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0 TLV853MDBZT SOT-23 DBZ 3 250 210.0 185.0 35.0 Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION www.ti.com 20-May-2026 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV863MDBZR SOT-23 DBZ 3 3000 210.0 185.0 35.0 TLV863MDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0 TLV863MDBZT SOT-23 DBZ 3 250 210.0 185.0 35.0 TLV863MDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0 Pack Materials-Page 4
www.ti.com PACKAGE OUTLINE C 0.20
0.08 TYP
0.25 2.64 2.10
1.12 MAX
0.10
0.01 TYP
3X 0.5 0.3 0.6
0.2 TYP
1.9 0.95 0 -8 TYP 4X 0 -15 4X 4 -15 A 3.04 2.80 B1.4 1.2 (0.95) (0.15) (0.125) SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR 4214838/F 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration TO-236, except minimum foot length. 4. Support pin may differ or may not be present. 5. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25mm per side
0.2 C A B
0.1 C SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
3X (1.3) 3X (0.6) (2.1) 2X (0.95) (R0.05) TYP 4214838/F 08/2024 SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE SCALE:15X PKG SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS
www.ti.com EXAMPLE STENCIL DESIGN (2.1) 2X(0.95) 3X (1.3) 3X (0.6) (R0.05) TYP SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR 4214838/F 08/2024 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:15X SYMM PKG
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