TL750L

TL750L, TL751L Low-Dropout Voltage Regulators datasheet (Rev. U)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SLVS017,U]
• PDF pages: 28

Technical content

TL750L . . . LP PACKAGE (TO-92, TO-226AA) (TOP VIEW) INPUT COMMON OUTPUT OUTPUT NC NC NC INPUT NC COMMON ENABLE TL751L . . .P PACKAGE (TOP VIEW) OUTPUT COMMON COMMON NC INPUT COMMON COMMON ENABLE TL751L . . . D PACKAGE (TOP VIEW) OUTPUT COMMON COMMON NC INPUT COMMON COMMON NC TL750L . . . D PACKAGE (TOP VIEW) TL750L . . . KC PACKAGE (TOP VIEW) COMMON OUTPUT INPUT COMMON TL750L . . . KCS PACKAGE (TOP VIEW) COMMON OUTPUT INPUT COMMON TL750L . . . KTE PACKAGE (TOP VIEW) OUTPUT COMMON INPUT COMMON OUTPUT COMMON INPUT COMMON TL750L . . . KVU PACKAGE (TOP VIEW) TL750L . . . KTT PACKAGE (TOP VIEW) OUTPUT COMMON INPUTCOMMON NC – No internal connection NC – No internal connection NC – No internal connection TL750L TL751L LOW-DROPOUTVOLTAGEREGULATORS 1FEATURES

• Very Low Dropout Voltage,Less Than 0.6V at • Reverse TransientProtectionDown to–50 V 150 mA • InternalThermal-OverloadProtection
• Very Low QuiescentCurrent • OvervoltageProtection
• TTL- and CMOS-Compatible Enable on TL751L • InternalOvercurrent-LimitingCircuitry Series • Less Than 500-μA Disable(TL751L Series)
• 60-V Load-Dump Protection DESCRIPTION/ORDERING INFORMATION The TL750L and TL751L seriesof fixed-outputvoltageregulatorsoffer5-V,8-V,10-V,and 12-V options.The TL751L seriesalsohas an enable(ENABLE) input.When ENABLE ishigh,theregulatoroutputisplacedinthe high-impedancestate.This givesthe designercompletecontrolover power up, power down, or emergency shutdown. The TL750L and TL751L series are low-dropoutpositive-voltageregulatorsspecificallydesigned for battery-poweredsystems.These devicesincorporateovervoltageand current-limitingprotectioncircuitry,along withinternalreverse-batteryprotectioncircuitryto protectthe devicesand the regulatedsystem.The seriesis fullyprotectedagainst60-V load-dump and reverse-batteryconditions.Extremelylow quiescentcurrentduring full-loadconditionsmakes thesedevicesidealforstandbypower systems. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 1987–2009,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

ORDERING INFORMATION (1) VO TYPTJ PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKINGAT 25°C PowerFLEX ™ – KTE Reelof2000 TL750L05CKTER TL750L05C Tube of75 TL750L05CD 50L05C Reelof2500 TL750L05CDR SOIC – D Tube of75 TL751L05CD 51L05C Reelof2500 TL751L05CDR

5 V Bulkof1000 TL750L05CLP

TO-226/TO-92– LP 750L05C Reelof2000 TL750L05CLPR TO-220 – KC Tube of50 TL750L05CKC TL750L05C TO-220 – KCS Tube of50 TL750L05CKCS TL750L05C TO-252 – KVU Reelof2500 TL750L05CKVUR 750L05C TO-263 – KTT Reelof500 TL750L05CKTTR 750L05C Tube of75 TL750L08CD SOIC – D 50L08C

8 V Reelof2500 TL750L08CDR

0°C to125°C TO-226/TO-92– LP Bulkof1000 TL750L08CLP 750L08C PDIP – P Tube of50 TL751L10CP TL751L10C Tube of75 TL750L10CD 50L10C Reelof2500 TL750L10CDR SOIC – D

10 V Tube of75 TL751L10CD

TO-226/TO-92– LP 750L10C Reelof2000 TL750L10CLPR Tube of75 TL750L12CD 50L12C Reelof2500 TL750L12CDR SOIC – D

12 V Tube of75 TL751L12CD

TO-226/TO-92– LP Bulkof1000 TL750L12CLP 750L12C (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orsee theTI web siteatwww.ti.com. (2) Package drawings,thermaldata,and symbolizationareavailableatwww.ti.com/packaging. DEVICE COMPONENT COUNT Transistors 20 JFETs 2 Diodes 5 Resistors 16

2 SubmitDocumentationFeedback Copyright© 1987–2009,Texas InstrumentsIncorporated

AbsoluteMaximum Ratings(1) overoperatingjunctiontemperaturerange(unlessotherwisenoted) MIN MAX UNIT Continuousinputvoltage 26 V Transientinputvoltage(2) TA = 25°C 60 V Continuousreverseinputvoltage –15 V Transientreverseinputvoltage t≤ 100 ms –50 V TJ Operatingvirtualjunctiontemperature 150 °C Lead temperature 1,6mm (1/16in)for10 s 260 °C Tstg Storagetemperaturerange –65 150 °C (1) Stressesbeyond thoselistedunder"absolutemaximum ratings"may cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder"recommended operating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) The transientinputvoltageratingappliestothewaveform shown inFigure1. Package Thermal Data(1) PACKAGE BOARD θJC θJA PDIP (P) HighK,JESD 51-7 57°C/W 85°C/W PowerFLEX ™ (KTE) HighK,JESD 51-5 3°C/W 23°C/W SOIC (D) HighK,JESD 51-7 39°C/W 97°C/W TO-226/TO-92(LP) HighK,JESD 51-7 55°C/W 140°C/W TO-220 (KC) HighK,JESD 51-5 3°C/W 19°C/W TO-220 (KCS) HighK,JESD 51-5 3°C/W 19°C/W TO-252 (KVU) HighK,JESD 51-5 – 30.3°C/W TO-263 (KTT) HighK,JESD 51-5 18°C/W 25.3°C/W (1) Maximum power dissipationisa functionofTJ(max),θJA,and TA.The maximum allowablepower dissipationatany allowableambient temperatureisPD = (TJ(max)– TA)/θJA.Operatingattheabsolutemaximum TJ of150°C can affectreliability. Recommended OperatingConditions overrecommended operatingjunctiontemperaturerange(unlessotherwisenoted) MIN MAX UNIT TL75xL05 6 26 TL75xL08 9 26 VI Inputvoltage V TL75xL10 11 26 TL75xL12 13 26 VIH High-levelENABLE inputvoltage TL75xLxx 2 15 V TJ = 25°C TL75xLxx –0.3 0.8 VIL (1) Low-levelENABLE inputvoltage V TJ = 0°C to125°C TL75xLxx –0.15 0.8 IO Outputcurrent TL75xLxx 0 150 mA TJ Operatingvirtualjunctiontemperature TL75xLxxC 0 125 °C (1) The algebraicconvention,inwhichtheleastpositive(mostnegative)valueisdesignatedminimum, isused inthisdatasheetfor ENABLE voltagelevelsand temperatureonly. Copyright© 1987–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3

TL75xL05 ElectricalCharacteristics(1) VI = 14 V,IO = 10 mA, TJ = 25°C (unlessotherwisenoted) TL750L05 TL751L05PARAMETER TEST CONDITIONS UNIT MIN TYP MAX TJ = 25°C 4.8 5 5.2 Outputvoltage VI= 6 V to26 V,IO = 0 to150 mA V TJ = 0°C to125°C 4.75 5.25 VI= 9 V to16 V 5 10 Inputregulationvoltage mV VI= 6 V to26 V 6 30 Ripplerejection VI= 8 V to18 V,f= 120 Hz 60 65 dB Outputregulationvoltage IO = 5 mA to150 mA 20 50 mV IO = 10 mA 0.2 Dropoutvoltage V IO = 150 mA 0.6 Outputnoisevoltage f= 10 Hz to100 kHz 500 μV IO = 150 mA 10 12 Quiescentcurrent VI= 6 V to26 V,IO = 10 mA, TJ = 0°C to125°C 1 2 mA ENABLE ≥ 2 V 0.5 (1) Pulse-testingtechniquesareused tomaintainthejunctiontemperatureas closetotheambienttemperatureas possible.Thermaleffects must be takenintoaccountseparately.Allcharacteristicsaremeasured witha 0.1-μF capacitoracrosstheinputand a 10-μF capacitor, withequivalentseriesresistanceoflessthan0.4Ω,acrosstheoutput. TL75xL08 ElectricalCharacteristics(1) VI = 14 V,IO = 10 mA, TJ = 25°C (unlessotherwisenoted) TL750L08 TL751L08PARAMETER TEST CONDITIONS UNIT MIN TYP MAX TJ = 25°C 7.68 8 8.32 Outputvoltage VI= 9 V to26 V,IO = 0 to150 mA V TJ = 0°C to125°C 7.6 8.4 VI= 10 V to17 V 10 20 Inputregulationvoltage mV VI= 9 V to26 V 25 50 Ripplerejection VI= 11 V to21 V,f= 120 Hz 60 65 dB Outputregulationvoltage IO = 5 mA to150 mA 40 80 mV IO = 10 mA 0.2 Dropoutvoltage V IO = 150 mA 0.6 Outputnoisevoltage f= 10 Hz to100 kHz 500 μV IO = 150 mA 10 12 Quiescentcurrent VI= 9 V to26 V,IO = 10 mA, TJ = 0°C to125°C 1 2 mA ENABLE ≥ 2 V 0.5 (1) Pulse-testingtechniquesareused tomaintainthejunctiontemperatureas closetotheambienttemperatureas possible.Thermaleffects must be takenintoaccountseparately.Allcharacteristicsaremeasured witha 0.1-μF capacitoracrosstheinputand a 10-μF capacitor, withequivalentseriesresistanceoflessthan0.4Ω,acrosstheoutput.

4 SubmitDocumentationFeedback Copyright© 1987–2009,Texas InstrumentsIncorporated

TL75xL10 ElectricalCharacteristics(1) VI = 14 V,IO = 10 mA, TJ = 25°C (unlessotherwisenoted) TL750L10 TL751L10PARAMETER TEST CONDITIONS UNIT MIN TYP MAX TJ = 25°C 9.6 10 10.4 Outputvoltage VI= 11 V to26 V,IO = 0 to150 mA V TJ = 0°C to125°C 9.5 10.5 VI= 12 V to19 V 10 25 Inputregulationvoltage mV VI= 11 V to26 V 30 60 Ripplerejection VI= 12 V to22 V,f= 120 Hz 60 65 dB Outputregulationvoltage IO = 5 mA to150 mA 50 100 mV IO = 10 mA 0.2 Dropoutvoltage V IO = 150 mA 0.6 Outputnoisevoltage f= 10 Hz to100 kHz 700 μV IO = 150 mA 10 12 Quiescentcurrent VI= 11 V to26 V,IO = 10 mA, TJ = 0°C to125°C 1 2 mA ENABLE ≥ 2 V 0.5 (1) Pulse-testingtechniquesareused tomaintainthejunctiontemperatureas closetotheambienttemperatureas possible.Thermaleffects must be takenintoaccountseparately.Allcharacteristicsaremeasured witha 0.1-μF capacitoracrosstheinputand a 10-μF capacitor, withequivalentseriesresistanceoflessthan0.4Ω,acrosstheoutput. TL75xL12 ElectricalCharacteristics(1) VI = 14 V,IO = 10 mA, TJ = 25°C (unlessotherwisenoted) TL750L12 TL751L12PARAMETER TEST CONDITIONS UNIT MIN TYP MAX TJ = 25°C 11.52 12 12.48 Outputvoltage VI= 13 V to26 V,IO = 0 to150 mA V TJ = 0°C to125°C 11.4 12.6 VI= 14 V to19 V 15 30 Inputregulationvoltage mV VI= 13 V to26 V 20 40 Ripplerejection VI= 13 V to23 V,f= 120 Hz 50 55 dB Outputregulationvoltage IO = 5 mA to150 mA 50 120 mV IO = 10 mA 0.2 Dropoutvoltage V IO = 150 mA 0.6 Outputnoisevoltage f= 10 Hz to100 kHz 700 μV IO = 150 mA 10 12 Quiescentcurrent VI= 13 V to26 V,IO = 10 mA, TJ = 0°C to125°C 1 2 mA ENABLE ≥ 2 V 0.5 (1) Pulse-testingtechniquesareused tomaintainthejunctiontemperatureas closetotheambienttemperatureas possible.Thermaleffects must be takenintoaccountseparately.Allcharacteristicsaremeasured witha 0.1-μF capacitoracrosstheinputand a 10-μF capacitor, withequivalentseriesresistanceoflessthan0.4Ω,acrosstheoutput. PARAMETER MEASUREMENT INFORMATION The TL750L,TL751L seriesarelow-dropoutregulators.Thismeans thatcapacitanceloadingisimportanttothe performanceoftheregulatorbecause itisa vitalpartofthecontrolloop.The capacitorvalueand itsequivalent seriesresistance(ESR) both affectthe controlloopand must be definedforthe loadrange and temperature range.Figure1 shows therecommended rangeofESR fora givenloadwitha 10-μF capacitoron theoutput. Copyright© 1987–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5

iV − Transient Input Voltage − V ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ tr = 1 ms TA = 25°C for t ≥/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr5 ms t − Time − ms IL − Load Current − mA 0.2 0.1 0 0 10 ESR − Equivalent Series Resistance − 0.3 0.4 0.5 0.024 0.6 0.7 0.8 0.9 1.0 Region of Best Stability 80 120 150 Potential Instability Region C L = 10-mF Tantalum Capacitor TA = −40°C to 125°C Potential Instability Region W 0 2 4 6 8 12 1410 VI − Input Voltage − V − Input Current − mAII 0 1 2 3 − Input Current − mA 4 5 6 II VI − Input Voltage − V TL750L TL751L TYPICAL CHARACTERISTICS TL750L05 EQUIVALENT SERIES RESISTANCE TRANSIENT INPUT VOLTAGE vs vs LOAD CURRENT TIME Figure1. Figure2. TL750L05 TL750L12 INPUT CURRENT INPUT CURRENT vs vs INPUT VOLTAGE INPUT VOLTAGE Figure3. Figure4.

6 SubmitDocumentationFeedback Copyright© 1987–2009,Texas InstrumentsIncorporated

www.ti.com 15-Jul-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TL750L05CD Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 125 50L05C TL750L05CD.A Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 125 50L05C TL750L05CDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 125 50L05C TL750L05CDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 125 50L05C TL750L05CKCS Active Production TO-220 (KCS) | 3 50 | TUBE Yes SN N/A for Pkg Type 0 to 125 TL750L05C TL750L05CKCS.A Active Production TO-220 (KCS) | 3 50 | TUBE Yes SN N/A for Pkg Type 0 to 125 TL750L05C TL750L05CKCSE3 Active Production TO-220 (KCS) | 3 50 | TUBE Yes SN N/A for Pkg Type 0 to 125 TL750L05C TL750L05CKTTR Active Production DDPAK/ TO-263 (KTT) | 3 500 | LARGE T&R Yes SN Level-3-245C-168 HR 0 to 125 TL750L05C TL750L05CKTTR.A Active Production DDPAK/ TO-263 (KTT) | 3 500 | LARGE T&R Yes SN Level-3-245C-168 HR 0 to 125 TL750L05C TL750L05CKTTRG3 Active Production DDPAK/ TO-263 (KTT) | 3 500 | LARGE T&R Yes SN Level-3-245C-168 HR 0 to 125 TL750L05C TL750L05CKVURG3 Active Production TO-252 (KVU) | 3 2500 | LARGE T&R Yes SN Level-3-260C-168 HR 0 to 125 750L05C TL750L05CKVURG3.A Active Production TO-252 (KVU) | 3 2500 | LARGE T&R Yes SN Level-3-260C-168 HR 0 to 125 750L05C TL750L05CLP Active Production TO-92 (LP) | 3 1000 | BULK Yes SN N/A for Pkg Type 0 to 125 750L05C TL750L05CLP.A Active Production TO-92 (LP) | 3 1000 | BULK Yes SN N/A for Pkg Type 0 to 125 750L05C TL750L05CLPE3 Active Production TO-92 (LP) | 3 1000 | BULK Yes SN N/A for Pkg Type 0 to 125 750L05C TL750L05CLPR Active Production TO-92 (LP) | 3 2000 | LARGE T&R Yes SN N/A for Pkg Type 0 to 125 750L05C TL750L05CLPR.A Active Production TO-92 (LP) | 3 2000 | LARGE T&R Yes SN N/A for Pkg Type 0 to 125 750L05C TL750L05CLPRE3 Active Production TO-92 (LP) | 3 2000 | LARGE T&R Yes SN N/A for Pkg Type 0 to 125 750L05C TL750L08CD Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-2-260C-1 YEAR 0 to 125 50L08C TL750L08CD.A Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-2-260C-1 YEAR 0 to 125 50L08C TL750L08CDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR 0 to 125 50L08C TL750L08CDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR 0 to 125 50L08C TL750L08CLP Active Production TO-92 (LP) | 3 1000 | BULK Yes SN N/A for Pkg Type 0 to 125 750L08C TL750L08CLP.A Active Production TO-92 (LP) | 3 1000 | BULK Yes SN N/A for Pkg Type 0 to 125 750L08C TL750L08CLPE3 Active Production TO-92 (LP) | 3 1000 | BULK Yes SN N/A for Pkg Type 0 to 125 750L08C TL750L10CD Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 125 50L10C TL750L10CD.A Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 125 50L10C Addendum-Page 1

www.ti.com 15-Jul-2026 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TL750L10CDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 125 50L10C TL750L10CDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 125 50L10C TL750L10CLP Active Production TO-92 (LP) | 3 1000 | BULK Yes SN N/A for Pkg Type 0 to 125 750L10C TL750L10CLP.A Active Production TO-92 (LP) | 3 1000 | BULK Yes SN N/A for Pkg Type 0 to 125 750L10C TL750L10CLPR Active Production TO-92 (LP) | 3 2000 | LARGE T&R Yes SN N/A for Pkg Type 0 to 125 750L10C TL750L10CLPR.A Active Production TO-92 (LP) | 3 2000 | LARGE T&R Yes SN N/A for Pkg Type 0 to 125 750L10C TL750L12CD Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 125 50L12C TL750L12CD.A Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 125 50L12C TL750L12CDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 125 50L12C TL750L12CDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 125 50L12C TL750L12CLP Active Production TO-92 (LP) | 3 1000 | BULK Yes SN N/A for Pkg Type 0 to 125 750L12C TL750L12CLP.A Active Production TO-92 (LP) | 3 1000 | BULK Yes SN N/A for Pkg Type 0 to 125 750L12C TL751L05CD Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 125 51L05C TL751L05CD.A Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 125 51L05C TL751L05CDE4 Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 125 51L05C TL751L05CDG4 Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 125 51L05C TL751L05CDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 125 51L05C TL751L05CDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 125 51L05C TL751L10CD Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 125 51L10C TL751L10CD.A Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 125 51L10C TL751L10CDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 125 51L10C TL751L10CDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 125 51L10C TL751L10CP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 125 TL751L10C TL751L10CP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 125 TL751L10C TL751L12CD Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 125 51L12C TL751L12CD.A Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 125 51L12C TL751L12CDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 125 51L12C TL751L12CDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 125 51L12C TL751L12CDRG4 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 125 51L12C (1) Status: For more details on status, see our product life cycle. Addendum-Page 2

www.ti.com 15-Jul-2026 (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TL750L05CKTTR DDPAK/ TO-263 Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL750L05CDR SOIC D 8 2500 353.0 353.0 32.0 TL750L05CKTTR DDPAK/TO-263 KTT 3 500 340.0 340.0 38.0 TL750L05CKVURG3 TO-252 KVU 3 2500 340.0 340.0 38.0 TL750L08CDR SOIC D 8 2500 340.5 338.1 25.0 TL750L10CDR SOIC D 8 2500 340.5 338.1 20.6 TL750L12CDR SOIC D 8 2500 353.0 353.0 32.0 TL751L05CDR SOIC D 8 2500 340.5 338.1 20.6 TL751L10CDR SOIC D 8 2500 340.5 338.1 20.6 TL751L12CDR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TL750L05CD D SOIC 8 75 507 8 3940 4.32 TL750L05CD.A D SOIC 8 75 507 8 3940 4.32 TL750L05CKCS KCS TO-220 3 50 532 34.1 700 9.6 TL750L05CKCS.A KCS TO-220 3 50 532 34.1 700 9.6 TL750L05CKCSE3 KCS TO-220 3 50 532 34.1 700 9.6 TL750L08CD D SOIC 8 75 507 8 3940 4.32 TL750L08CD.A D SOIC 8 75 507 8 3940 4.32 TL750L10CD D SOIC 8 75 507 8 3940 4.32 TL750L10CD.A D SOIC 8 75 507 8 3940 4.32 TL750L12CD D SOIC 8 75 507 8 3940 4.32 TL750L12CD.A D SOIC 8 75 507 8 3940 4.32 TL751L05CD D SOIC 8 75 507 8 3940 4.32 TL751L05CD.A D SOIC 8 75 507 8 3940 4.32 TL751L05CDE4 D SOIC 8 75 507 8 3940 4.32 TL751L05CDG4 D SOIC 8 75 507 8 3940 4.32 TL751L10CD D SOIC 8 75 507 8 3940 4.32 TL751L10CD.A D SOIC 8 75 507 8 3940 4.32 TL751L10CP P PDIP 8 50 506 13.97 11230 4.32 TL751L10CP.A P PDIP 8 50 506 13.97 11230 4.32 TL751L12CD D SOIC 8 75 507 8 3940 4.32 TL751L12CD.A D SOIC 8 75 507 8 3940 4.32 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 5.460 4.953 10.41 9.40 2.29 4.58 3X 0.890 0.635 1.02 0.61 1.27 0.89

2.52 MAX

0.61 0.46 4.32 MIN

5.21 MIN

-80 0.13 0.00 1.78 1.40 0.61 0.46 A 6.70 6.35 B 6.22 5.97 0.51 GAGE PLANE TO-252 - 2.52 mm max heightKVU0003A TO-252 4218915/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Shape may vary per different assembly sites. 4. Reference JEDEC registration TO-252.

0.25 C A B

SCALE 1.500 SEE DETAIL A EXPOSED THERMAL PAD NOTE 3 A 7.000 DETAIL A TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

ALL AROUND 0.07 MIN ALL AROUND (6.15) (5.55)(4.58) 2X (1) 2X (2.75) TO-252 - 2.52 mm max heightKVU0003A TO-252 4218915/A 02/2017 LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:6X PKG SYMM NOTES: (continued) 5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers 6. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL EXPOSED METAL SOLDER MASK DETAILS NOT TO SCALE NON SOLDER MASK DEFINED METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (R0.05) 2X (2.75) 2X (1) (4.58) (1.33) TYP (1.18) TYP (0.14) (4.2) TO-252 - 2.52 mm max heightKVU0003A TO-252 4218915/A 02/2017 PKG NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 65% PRINTED SOLDER COVERAGE BY AREA SCALE:8X SYMM

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

www.ti.com PACKAGE OUTLINE 3X 2.67 2.03 5.21 4.44 5.34 4.32

12.7 MIN

2X 1.27 0.13 3X 0.55 0.38 4.19 3.17

3.43 MIN

3X 0.43 0.35 (2.54) NOTE 3 2X 2.9 2.4

4 MAX

0.076 MAX

(0.51) TYP (1.5) TYP TO-92 - 5.34 mm max heightLP0003A TO-92 4215214/C 04/2025 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Lead dimensions are not controlled within this area. 4. Reference JEDEC TO-226, variation AA. 5. Shipping method: a. Straight lead option available in bulk pack only. b. Formed lead option available in tape and reel or ammo pack. c. Specific products can be offered in limited combinations of shipping medium and lead options. d. Consult product folder for more information on available options. EJECTOR PIN OPTIONAL PLANE SEATING STRAIGHT LEAD OPTION 3 2 1 SCALE 1.200 FORMED LEAD OPTION OTHER DIMENSIONS IDENTICAL TO STRAIGHT LEAD OPTION SCALE 1.200

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

(1.07) (1.5) 2X (1.5) 2X (1.07) (1.27) (2.54) FULL R TYP ( 1.4)0.05 MAX ALL AROUND TYP (2.6) (5.2) (R0.05) TYP 3X ( 0.9) HOLE 2X ( 1.4) METAL 3X ( 0.85) HOLE (R0.05) TYP 4215214/C 04/2025 TO-92 - 5.34 mm max heightLP0003A TO-92 LAND PATTERN EXAMPLE FORMED LEAD OPTION NON-SOLDER MASK DEFINED SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING 1 2 3 LAND PATTERN EXAMPLE STRAIGHT LEAD OPTION NON-SOLDER MASK DEFINED SCALE:15X METAL TYP SOLDER MASK OPENING SOLDER MASK OPENING METAL 1 2 3

www.ti.com TAPE SPECIFICATIONS 19.0 17.5 13.7 11.7 11.0 8.5

0.5 MIN

3.7-4.3 TYP 9.75 8.50 2.9

2.4 TYP

6.75 5.95 13.0 12.4 (2.5) TYP 16.5 15.5 4215214/C 04/2025 TO-92 - 5.34 mm max heightLP0003A TO-92 FOR FORMED LEAD OPTION PACKAGE

www.ti.com PACKAGE OUTLINE 9.25 9.05 6.5 6.1 2.9 2.6 10.36 9.96 13.12 12.70

3.9 MAX

3X 1.36 1.23 3X 0.90 0.77 ( 3.84) 5.08 2X 2.54 8.55 8.15 12.5 12.1 (6.3)

19.65 MAX

4.7 4.4 1.32 1.22 2.79 2.59 0.47 0.34 4222214/B 08/2018 TO-220 - 19.65 mm max heightKCS0003B TO-220 NOTES: 1. Dimensions are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration TO-220. 1 3 SCALE 0.850

www.ti.com EXAMPLE BOARD LAYOUT (1.7) 3X (1.2) (2.54) (5.08) R (0.05) 2X (1.7) METAL 2X SOLDER MASK OPENING 4222214/B 08/2018 TO-220 - 19.65 mm max heightKCS0003B TO-220 LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE:15X 1 2 3 OPENING SOLDER MASK

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you fully indemnify TI and its representatives against any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale, TI’s General Quality Guidelines, or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Unless TI explicitly designates a product as custom or customer-specified, TI products are standard, catalog, general purpose devices. TI objects to and rejects any additional or different terms you may propose. IMPORTANT NOTICE Copyright © 2026, Texas Instruments Incorporated Last updated 10/2025