TL594 Pulse-Width-Modulation Control Circuit datasheet (Rev. I)
Document overview
- Manufacturer or author: Texas Instruments, Incorporated [SLVS052,I]
- PDF pages: 35
Technical content
í Error Amplifier 1 0.1 V DTC Comparator Oscillator OUTPUT CTRL (see Function T able) 0.7 mA í Undervoltage Lockout Control IN+ INí IN+ INí Copyright © 2016, Texas Instruments Incorporated Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TL594 SLVS052I –APRIL 1988–REVISED SEPTEMBER 2016 TL594Pulse-Width-ModulationControlCircuit
1 Features
1• Complete PWM Power-Control Circuitry
- Uncommitted Outputs for 200-mA Sink or Source Current
- Output Control Selects Single-Ended or Push-Pull Operation
- Internal Circuitry Prohibits Double Pulse at Either Output
- Variable Dead Time Provides Control Over Total Range
- Internal Regulator Provides a Stable 5-V Reference Supply Trimmed to 1%
- Circuit Architecture Allows Easy Synchronization
- Undervoltage Lockout (UVLO) for Low-VCC Conditions
2 Applications
- White Goods
- Power Supplies: AC/DC, Isolated, With PFC, > 90 W
- Server PSUs
- Solar Micro-Inverters
- Power Supplies: AC/DC, Isolated, No PFC, < 90 W
- Power: Telecom/Server AC/DC Supplies
- Solar Power Inverters
3 Description
The TL594 device incorporates all the functions required in the construction of a pulse-width- modulation (PWM) control circuit on a single chip. Designed primarily for power-supply control, this device offers the systems engineer the flexibility to tailor the power-supply control circuitry to a specific application. The TL594 device contains two error amplifiers, an on-chip adjustable oscillator, a dead-time control (DTC) comparator, a pulse-steering control flip-flop, a 5-V regulator with a precision of 1%, an undervoltage lockout control circuit, and output control circuitry. The uncommitted output transistors provide either common-emitter or emitter-follower output capability. Each device provides for push-pull or single-ended output operation, with selection by means of the output-control function. The architecture of these devices prohibits the possibility of either output being pulsed twice during push-pull operation. The undervoltage lockout control circuit locks the outputs off until the internal circuitry is operational. Device Information PART NUMBER PACKAGE BODY SIZE (NOM) TL594D SOIC (16) 9.90 mm × 3.91 mm TL594N PDIP (16) 19.30 mm × 6.35 mm TL594NS SO (16) 10.30 mm × 5.30 mm TL594PW TSSOP (16) 5.00 mm × 4.40 mm Block Diagram For OUTPUT CTRL function, see Table 1.
SLVS052I –APRIL 1988–REVISED SEPTEMBER 2016 www.ti.com Product Folder Links: TL594 Submit Documentation Feedback Copyright © 1988–2016, Texas Instruments Incorporated Table of Contents
12.2 Receiving Notification of Documentation Updates 21
13 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (January 2014) to Revision I Page
- Added Applications section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
- Changed values in the Thermal Information table from 73 to 73.5 (D), from 67 to 43.5 (N), from 64 to 73.6 (NS), and Changes from Revision G (January 2007) to Revision H Page
21IN± 15 2IN ± 3FEEDBACK 14 REF 4DTC 13 OUTPUT CTRL 5CT 12 VCC 6RT 11 C2 7GND 10 E2 8C1 9 E1 Not to scale TL594 www.ti.com SLVS052I –APRIL 1988–REVISED SEPTEMBER 2016 Product Folder Links: TL594 Submit Documentation FeedbackCopyright © 1988–2016, Texas Instruments Incorporated
5 Pin Configuration and Functions
D, N, NS, or PW Package 16-Pin SOIC, PDIP, SO, or TSSOP Top View Pin Functions PIN I/O DESCRIPTION NO. NAME 1 1IN+ I Noninverting input to error amplifier 1 2 1IN– I Inverting input to error amplifier 1
3 FEEDBACK I Input pin for feedback
4 DTC I Dead-time control comparator input
5 CT — Capacitor terminal used to set oscillator frequency
6 RT — Resistor terminal used to set oscillator frequency
7 GND — Ground
8 C1 O Collector terminal of BJT output 1
9 E1 O Emitter terminal of BJT output 1
10 E2 O Emitter terminal of BJT output 2
11 C2 O Collector terminal of BJT output 2
12 VCC — Positive supply
13 OUTPUT CTRL I Selects single-ended, parallel output, or push-pull operation
14 REF O 5-V reference regulator output
15 2IN– I Inverting input to error amplifier 2 16 2IN+ I Noninverting input to error amplifier 2
SLVS052I –APRIL 1988–REVISED SEPTEMBER 2016 www.ti.com Product Folder Links: TL594 Submit Documentation Feedback Copyright © 1988–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential voltages, are with respect to the network ground terminal.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage, VCC(2) 41 V Amplifier input voltage VCC + 0.3 V Collector output voltage 41 V Collector output current 250 mA Operating junction temperature, TJ 150 °C Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 1000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) 1000
6.3 Recommended Operating Conditions
VI Amplifier input voltage –0.3 VCC – 2 V VO Collector output voltage 40 V Collector output current (each transistor) 200 mA Current into FEEDBACK terminal 0.3 mA CT Timing capacitor 0.47 10000 nF RT Timing resistor 1.8 500 kΩ fosc Oscillator frequency 1 300 kHz TA Operating free-air temperature TL594C 0 70 TL594I –40 85 (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.4 Thermal Information
THERMAL METRIC(1) TL594 UNITD (SOIC) N (PDIP) NS (SO) PW (TSSOP)
16 PINS 16 PINS 16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 73.5 43.5 73.6 101.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 32.8 30.6 30.3 29.4 °C/W RθJB Junction-to-board thermal resistance 30.8 23.5 34.4 47.3 °C/W ψJT Junction-to-top characterization parameter 6.1 15.3 3.4 1.4 °C/W ψJB Junction-to-board characterization parameter 30.6 23.4 34.1 46.6 °C/W
/c61 /c45 /c115 /c61 /c45 /c229 N n n 1 (X X) N 1 TL594 www.ti.com SLVS052I –APRIL 1988–REVISED SEPTEMBER 2016 Product Folder Links: TL594 Submit Documentation FeedbackCopyright © 1988–2016, Texas Instruments Incorporated (1) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. (2) All typical values, except for parameter changes with temperature, are at TA = 25°C. (3) Duration of the short circuit must not exceed one second. (4) Standard deviation is a measure of the statistical distribution about the mean, as derived from the formula: (5) Temperature coefficient of timing capacitor and timing resistor is not taken into account.
6.5 Electrical Characteristics
VCC = 15 V, over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS(1) MIN TYP(2) MAX UNIT REFERENCE Output voltage (REF) IO = 1 mA, TA = 25°C 4.95 5 5.05 V Input regulation VCC = 7 V to 40 V, TA = 25°C 2 25 mV Output regulation IO = 1 mA to 10 mA, TA = 25°C 14 35 mV Output-voltage change with temperature ΔTA = MIN to MAX 2 10 mV/V Short-circuit output current(3) Vref = 0 10 35 50 mA AMPLIFIER (SEE Figure 3) Input offset voltage, error amplifier FEEDBACK = 2.5 V 2 10 mV Input offset current FEEDBACK = 2.5 V 25 250 nA Input bias current FEEDBACK = 2.5 V 0.2 1 µA Common mode input voltage, error amplifier VCC = 7 V to 40 V 0.3 to VCC – 2 V Open-loop voltage amplification, error amplifier ΔVO = 3 V, RL = 2 kΩ, VO = 0.5 V to 3.5 V 70 95 dB Unity-gain bandwidth VO = 0.5 V to 3.5 V, RL = 2 kΩ 800 kHz Common mode rejection ratio, error amplifier VCC = 40 V, TA = 25°C 65 80 dB Output sink current, FEEDBACK VID = –15 mV to –5 V, FEEDBACK = 0.5 V 0.3 0.7 mA Output source current, FEEDBACK VID = 15 mV to 5 V, FEEDBACK = 3.5 V –2 mA OSCILLATOR, CT = 0.01 µF, RT = 12 kΩ (SEE Figure 4) Frequency 10 kHz Standard deviation of frequency(4) All values of VCC, CT, RT, and TA constant 100 Hz/kHz Frequency change with voltage VCC = 7 V to 40 V, TA = 25°C 1 Hz/kHz Frequency change with temperature(5) ΔTA = MIN to MAX 50 Hz/kHz DEAD-TIME CONTROL (SEE Figure 4) Input bias current VI = 0 to 5.25 V –2 –10 µA Maximum duty cycle, each output DTC = 0 V 0.45 Input threshold voltage Zero duty cycle 3 3.3 V Maximum duty cycle 0 OUTPUT Collector off-state current VC = 40 V, VE = 0 V, VCC = 40 V 2 100 µADTC and OUTPUT CTRL = 0 V, VC = 15 V, VE = 0 V, VCC = 1 V to 3 V 4 200 Emitter off-state current VCC = VC = 40 V, VE = 0 –100 µA Collector-emitter saturation voltage Common emitter, VE = 0, IC = 200 mA 1.1 1.3 V Emitter follower, VC = 15 V, IE = –200 mA 1.5 2.5 Output control input current VI = Vref 3.5 mA
(6) Hysteresis is the difference between the positive-going input threshold voltage and the negative-going input threshold voltage.
6.6 Switching Characteristics
6.7 Typical Characteristics
occurs over the full temperature range. Figure 1. Oscillator Frequency and Frequency Variation Figure 2. Amplifier Voltage Amplification
7 Parameter Measurement Information
Figure 3. Amplifier-Characteristics Test Circuit Figure 4. Operational Test Circuit and Waveforms
í Error Amplifier 1 0.1 V DTC Comparator Oscillator OUTPUT CTRL (see Function T able) 0.7 mA í Undervoltage Lockout Control IN+ INí IN+ INí Copyright © 2016, Texas Instruments Incorporated TL594 www.ti.com SLVS052I –APRIL 1988–REVISED SEPTEMBER 2016 Product Folder Links: TL594 Submit Documentation FeedbackCopyright © 1988–2016, Texas Instruments Incorporated
8 Detailed Description
8.1 Overview
The design of the TL594 not only incorporates the primary building blocks required to control a switching power supply, but also addresses many basic problems and reduces the amount of additional circuitry required in the total design. The TL594 is a fixed-frequency pulse-width-modulation (PWM) control circuit. Modulation of output pulses is accomplished by comparing the sawtooth waveform created by the internal oscillator on the timing capacitor (CT) to either of two control signals. The output stage is enabled during the time when the sawtooth voltage is greater than the voltage control signals. As the control signal increases, the time during which the sawtooth input is greater decreases; therefore, the output pulse duration decreases. A pulse-steering flip-flop alternately directs the modulated pulse to each of the two output transistors. The error amplifiers have a common-mode voltage range of –0.3 V to VCC – 2 V. The DTC comparator has a fixed offset that provides approximately 5% dead time. The on-chip oscillator can be bypassed by terminating RT to the reference output and providing a sawtooth input to CT, or it can be used to drive the common circuitry in synchronous multiple-rail power supplies. For more information on the operation of the TL594, see Designing Switching Voltage Regulators With the TL494 (SLVA001).
8.2 Functional Block Diagram
For OUTPUT CTRL function, see Table 1.
T CHARGE
3 V CT I
/c180/c61 CHARGE T
3 VI R/c61
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8.3 Feature Description
8.3.1 5-V Reference Regulator The TL594 internal 5-V reference regulator output is the REF pin. In addition to providing a stable reference, it acts as a preregulator and establishes a stable supply from which the output-control logic, pulse-steering flip-flop, oscillator, dead-time control comparator, and PWM comparator are powered. The regulator employs a band-gap circuit as its primary reference to maintain thermal stability of less than 100-mV variation over the operating free- air temperature range of 0°C to 70°C. Short-circuit protection is provided to protect the internal reference and preregulator; 10 mA of load current is available for additional bias circuits. The reference is internally programmed to an initial accuracy of ±1% and maintains a stability of less than 25-mV variation over an input voltage range of 7 V to 40 V. For input voltages less than 7 V, the regulator saturates within 1 V of the input and tracks it.
8.3.2 Undervoltage Lockout
The TL594 has circuitry to provide an undervoltage-lockout functionality. A minimum recommended VCC voltage of 7 V is recommended for operation, but if the VCC voltage drops below 6 V during operation, then the device shuts off. See Electrical Characteristics for additional information regarding the undervoltage lockout circuitry.
8.3.3 Oscillator
The oscillator provides a positive sawtooth waveform to the dead-time and PWM comparators for comparison to the various control signals. The frequency of the oscillator is programmed by selecting timing components RT and CT. The oscillator charges the external timing capacitor, CT, with a constant current, the value of which is determined by the external timing resistor, RT. This produces a linear-ramp voltage waveform. When the voltage across CT reaches 3 V, the oscillator circuit discharges it, and the charging cycle is reinitiated. The charging current is determined by Equation 1. (1) The period of the sawtooth waveform is Equation 2. (2) The frequency of the oscillator becomes Equation 3. (3) However, the oscillator frequency is equal to the output frequency only for single-ended applications. For push- pull applications, the output frequency is one-half the oscillator frequency. Single-ended applications are calculated with Equation 4. (4) Push-pull applications are calculated with Equation 5. (5)
www.ti.com SLVS052I –APRIL 1988–REVISED SEPTEMBER 2016 Product Folder Links: TL594 Submit Documentation FeedbackCopyright © 1988–2016, Texas Instruments Incorporated Feature Description (continued)
8.3.4 Dead-Time Control
The dead-time control input provides control of the minimum dead time (off time). The output of the comparator inhibits switching transistors Q1 and Q2 when the voltage at the input is greater than the ramp voltage of the oscillator. An internal offset of 110 mV ensures a minimum dead time of approximately 3% with the dead-time control input grounded. Applying a voltage to the dead-time control input can impose additional dead time. This provides a linear control of the dead time from its minimum of 3% to 100% as the input voltage is varied from 0 V to 3.3 V, respectively. With full-range control, the output can be controlled from external sources without disrupting the error amplifiers. The dead-time control input is a relatively high-impedance input (II < 10 µA) and must be used where additional control of the output duty cycle is required. However, for proper control, the input must be terminated. An open circuit is an undefined condition.
8.3.5 Comparator
The comparator is biased from the 5-V reference regulator. This provides isolation from the input supply for improved stability. The input of the comparator does not exhibit hysteresis, so protection against false triggering near the threshold must be provided. The comparator has a response time of 400 ns from either of the control- signal inputs to the output transistors, with only 100 mV of overdrive. This ensures positive control of the output within one-half cycle for operation within the recommended 300-kHz range.
8.3.6 Pulse-Width Modulation (PWM)
The comparator also provides modulation control of the output pulse width. For this, the ramp voltage across timing capacitor CT is compared to the control signal present at the output of the error amplifiers. The timing capacitor input incorporates a series diode that is omitted from the control signal input. This requires the control signal (error amplifier output) to be approximately 0.7 V greater than the voltage across CT to inhibit the output logic, and ensures maximum duty cycle operation without requiring the control voltage to sink to a true ground potential. The output pulse width varies from 97% of the period to 0 as the voltage present at the error amplifier output varies from 0.5 V to 3.5 V, respectively.
8.3.7 Error Amplifiers
Both high-gain error amplifiers receive their bias from the VI supply rail. This permits a common-mode input voltage range from –0.3 V to 2 V less than VI. Both amplifiers behave characteristically of a single-ended single- supply amplifier, in that each output is active high only. This allows each amplifier to pull up independently for a decreasing output pulse-width demand. With both outputs ORed together at the inverting input node of the PWM comparator, the amplifier demanding the minimum pulse out dominates. The amplifier outputs are biased low by a current sink to provide maximum pulse width out when both amplifiers are biased off.
8.3.8 Output-Control Input
The output-control input determines whether the output transistors operate in parallel or push-pull. This input is the supply source for the pulse-steering flip-flop. The output-control input is asynchronous and has direct control over the output, independent of the oscillator or pulse-steering flip-flop. The input condition is intended to be a fixed condition that is defined by the application. For parallel operation, the output-control input must be grounded. This disables the pulse-steering flip-flop and inhibits its outputs. In this mode, the pulses seen at the output of the dead-time control or PWM comparator are transmitted by both output transistors in parallel. For push-pull operation, the output-control input must be connected to the internal 5-V reference regulator. Under this condition, each of the output transistors is enabled, alternately, by the pulse-steering flip-flop.
8.3.9 Output Transistors
Two output transistors are available on the TL594. Both transistors are configured as open collector/open emitter, and each is capable of sinking or sourcing up to 200 mA. The transistors have a saturation voltage of less than 1.3 V in the common-emitter configuration and less than 2.5 V in the emitter-follower configuration. The outputs are protected against excessive power dissipation to prevent damage, but do not employ sufficient current limiting to allow them to be operated as current-source outputs.
8.4 Device Functional Modes
the OUTPUT CTRL pin is tied to VREF, the TL594 is operating in normal push-pull operation (see Table 1). Table 1. Function Table
9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Designing Switching Voltage Regulators With the TL494.
9.2 Typical Application
Switching Voltage Regulators With the TL494. Figure 7. 32-V to 5-V, 10-A Power Supply Application
120 VAC
3 A/50 V
9.2.1 Design Requirements
- VI = 32 V
- VO = 5 V
- IO = 10 A
- fOSC = 20-kHz switching frequency
- VR = 20-mV peak-to-peak (VRIPPLE)
- ΔIL = 1.5-A inductor current change
9.2.2 Detailed Design Procedure
9.2.2.1 Input Power Source
Figure 8. Input Power Source The output voltage and current are determined by Equation 6 and Equation 7.
9.2.2.2 Control Circuits
9.2.2.2.1 Oscillator
oscillator is set to operate at 20 kHz, using the component values calculated by Equation 8 and Equation 9. Choose CT = 0.001 µF and calculate RT with Equation 9.
9.2.2.2.2 Error Amplifier
constant output current (see Figure 9).
Figure 9. Error-Amplifier Section in place of R8 to provide an adjustment. input through RT, reducing the gain to 101.
9.2.2.2.3 Current-Limiting Amplifier
current is calculated as Equation 10. Figure 10 shows the current-limiting circuit. Figure 10. Current-Limiting Circuit Resistors R1 and R2 set the reference of about 1 V on the inverting input of the current-limiting amplifier.
9.2.2.2.4 Soft Start
circuit relatively simple (see Figure 11).
Figure 11. Soft-Start Circuit negative slope waveform to the dead-time control input (pin 4). rate is selected, the soft-start time is calculated as Equation 12. The value of the capacitor then is determined with Equation 13. This helps eliminate any false signals that might be created by the control circuit as power is applied.
9.2.2.2.5 Setting the Dead Time
experience a common on-time. Figure 12 shows the bias circuit for the basic function.
Figure 12. Setting Dead Time
9.2.2.3 Inductor Calculations
Figure 13 shows the switching circuit used. Figure 13. Switching Circuit
9.2.2.4 Output Capacitance Calculations
between the specified peak-to-peak ripple voltage and the peak-to-peak ripple current. objective is calculated according to Equation 15.
9.2.2.5 Transistor Power-Switch Calculations
Figure 14. Power-Switch Section calculated by Equation 16 through Equation 18 to be 144 mA. The value of R10 was calculated by Equation 19. and R12 permit the discharge of carriers in switching transistors when they are turned off.
9.2.3 Application Curve
Figure 15. Reference Voltage vs Input Voltage
10 Power Supply Recommendations
47 µF is a typical choice; however this may vary depending upon the output power being delivered.
11 Layout
11.1 Layout Guidelines
open core. Stick cores usually emit the most unwanted noise.
11.1.1 Feedback Traces
on the side of the PCB opposite of the inductor, ideally with a ground plane separating the two.
11.1.2 Input or Output Capacitors
the effective antenna created by through-hole components.
11.1.3 Compensation Components
placed very close to the inductor either.
11.1.4 Traces and Ground Planes
noise spikes, ringing, and resistive losses that produce voltage errors. feedback and compensation and components are) for improved performance. one plane to the other. Arrange the components so that the switching current loops curl in the same direction. half-cycles and reduces radiated EMI.
11.2 Layout Example
Figure 16. TL594 Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following: Designing Switching Voltage Regulators With the TL494 (SLVA001)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TL594CD Obsolete Production SOIC (D) | 16 - - Call TI Call TI 0 to 70 TL594C TL594CDR Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM 0 to 70 TL594C TL594CDR.A Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL594C TL594CDRG4 Obsolete Production SOIC (D) | 16 - - Call TI Call TI 0 to 70 TL594C TL594CN Active Production PDIP (N) | 16 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL594CN TL594CN.A Active Production PDIP (N) | 16 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL594CN TL594CNE4 Active Production PDIP (N) | 16 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL594CN TL594CNSR Active Production SOP (NS) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL594 TL594CNSR.A Active Production SOP (NS) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL594 TL594CPW Obsolete Production TSSOP (PW) | 16 - - Call TI Call TI 0 to 70 T594 TL594CPWR Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T594 TL594CPWR.A Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T594 TL594CPWRG4 Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T594 TL594ID Obsolete Production SOIC (D) | 16 - - Call TI Call TI -40 to 85 TL594I TL594IDR Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL594I TL594IDR.A Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL594I TL594IDRG4 Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL594I TL594IN Active Production PDIP (N) | 16 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL594IN TL594IN.A Active Production PDIP (N) | 16 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL594IN TL594INSR Active Production SOP (NS) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL594I TL594INSR.A Active Production SOP (NS) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL594I TL594INSRG4 Active Production SOP (NS) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL594I TL594IPWR Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 Z594 TL594IPWR.A Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 Z594 TL594IPWRG4 Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 Z594 (1) Status: For more details on status, see our product life cycle. Addendum-Page 1
www.ti.com 10-Nov-2025 (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL594CDR SOIC D 16 2500 353.0 353.0 32.0 TL594CNSR SOP NS 16 2000 353.0 353.0 32.0 TL594CPWR TSSOP PW 16 2000 353.0 353.0 32.0 TL594IDR SOIC D 16 2500 353.0 353.0 32.0 TL594INSR SOP NS 16 2000 353.0 353.0 32.0 TL594IPWR TSSOP PW 16 2000 353.0 353.0 32.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TL594CN N PDIP 16 25 506 13.97 11230 4.32 TL594CN N PDIP 16 25 506 13.97 11230 4.32 TL594CN.A N PDIP 16 25 506 13.97 11230 4.32 TL594CN.A N PDIP 16 25 506 13.97 11230 4.32 TL594CNE4 N PDIP 16 25 506 13.97 11230 4.32 TL594CNE4 N PDIP 16 25 506 13.97 11230 4.32 TL594IN N PDIP 16 25 506 13.97 11230 4.32 TL594IN.A N PDIP 16 25 506 13.97 11230 4.32 Pack Materials-Page 3
www.ti.com PACKAGE OUTLINE C 8.2
7.4 TYP
14X 1.27 16X 0.51 0.35 8.89
0.15 TYP
0.3 0.1
2.00 MAX
(1.25) 0.25 GAGE PLANE 1.05 0.55 A 10.4 10.0 NOTE 3 B 5.4 5.2 NOTE 4 4220735/A 12/2021 SOP - 2.00 mm max heightNS0016A SOP NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 1 16
0.25 C A B
0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.500
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
14X (1.27) (R0.05) TYP (7) 16X (1.85) 16X (0.6) 4220735/A 12/2021 SOP - 2.00 mm max heightNS0016A SOP NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS OPENING SOLDER MASK METAL SOLDER MASK DEFINED LAND PATTERN EXAMPLE SCALE:7X SYMM 8 9 SEE DETAILS SYMM
www.ti.com EXAMPLE STENCIL DESIGN (7)(R0.05) TYP 16X (1.85) 16X (0.6) 14X (1.27) 4220735/A 12/2021 SOP - 2.00 mm max heightNS0016A SOP NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:7X SYMM SYMM 8 9
www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.30 0.17 6.6
6.2 TYP
1.2 MAX
0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023
0.1 C A B
0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9
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