TL3116, TL3116Y: Ultra-Fast Low-Power Precision Comparators datasheet (Rev. C)
Document overview
- Manufacturer or author: Texas Instruments, Incorporated [SLCS132,C]
- PDF pages: 20
Technical content
/C0084/C0076/C0051/C0049/C0049/C0054/C0044 /C0084/C0076/C0051/C0049/C0049/C0054/C0089 /C0085/C0076/C0084/C0082/C0065/C0262/C0070/C0065/C0083/C0084 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0080/C0082/C0069/C0067/C0073/C0083/C0073/C0079/C0078 /C0067/C0079/C0077/C0080/C0065/C0082/C0065/C0084/C0079/C0082/C0083 /C0261 SLCS132C − MARCH 1997 − REVISED MAY 1997 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Ultra-Fast Operation. . . 10 ns (typ) /C0068Low Positive Supply Current 12.7 mA (Typ) /C0068Operates From a Single 5-V Supply or From a Split ±5-V Supply /C0068Complementary Outputs /C0068Input Common-Mode Voltage Includes Negative Rail /C0068Low Offset Voltage /C0068No Minimum Slew Rate Requirement /C0068Output Latch Capability /C0068Functional Replacement to the LT1116
description
The TL3116 is an ultra-fast comparator designed to interface directly to TTL logic while operating from either a single 5-V power supply or dual ±5-V supplies. The input common-mode voltage extends to the negative rail for ground sensing applications. It features extremely tight offset voltage and high gain for precision applications. It has complementary outputs that can be latched using the LATCH ENABLE terminal. Figure 1 shows the positive supply current of the comparator. The TL3116 only requires 12.7 mA (typical) to achieve a propagation delay of 10 ns. The TL3116 is a pin-for-pin functional replace- ment for the LT1116 comparator, offering high-speed operation but consuming much less power. AVAILABLE OPTIONS PACKAGED DEVICES CHIP TA SMALL OUTLINE † (D) TSSOP (PW) CHIP FORM ‡ (Y) 0°C to 70°C TL3116CD TL3116CPWLE TL3116Y −40°C to 85°C TL3116ID TL3116IPWLE — † The PW packages are available left-ended taped and reeled only. ‡ Chip forms are tested at TA = 25°C only. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D AND PW PACKAGE (TOP VIEW) VCC+ IN+ IN− VCC− Q OUT Q OUT GND LATCH ENABLE symbol (each comparator) IN+ IN− Figure 1 −50 −25 0 25 50 75 100 125 POSITIVE SUPPLY CURRENT vs FREE-AIR TEMPERATURE − Positive Supply Current − mAICC TA − Free-Air Temperature − °C Q OUT Q OUT ÎÎÎÎÎ ÎÎÎÎÎ VCC = ± 5 V /C0261 /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Copyright 1997, Texas Instruments Incorporated
/C0084/C0076/C0051/C0049/C0049/C0054/C0044 /C0084/C0076/C0051/C0049/C0049/C0054/C0089 /C0085/C0076/C0084/C0082/C0065/C0262/C0070/C0065/C0083/C0084 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0080/C0082/C0069/C0067/C0073/C0083/C0073/C0079/C0078 /C0067/C0079/C0077/C0080/C0065/C0082/C0065/C0084/C0079/C0082/C0083 /C0261 SLCS132C − MARCH 1997 − REVISED MAY 1997
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
This chip, when properly assembled, displays characteristics similar to the TL3116C. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS CHIP THICKNESS: 10 MILS TYPICAL BONDING PADS: 4 × 4 MILS MINIMUM TJ max = 150°C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS. TERMINALS 1 AND 6 CAN BE CONNECTED TO MULTIPLE PADS. Q OUT IN− IN+ LATCH ENABLE Q OUT (5) (2) (3) (1) (6) VCC+ GND (7) (8) VCC− (4) (1) (4) (3) (2) (5) (1) (1) (8) (7) (6) (6) (6) COMPONENT COUNT Bipolars 53 MOSFETs 49 Resistors 46 Capacitors 14
/C0084/C0076/C0051/C0049/C0049/C0054/C0044 /C0084/C0076/C0051/C0049/C0049/C0054/C0089 /C0085/C0076/C0084/C0082/C0065/C0262/C0070/C0065/C0083/C0084 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0080/C0082/C0069/C0067/C0073/C0083/C0073/C0079/C0078 /C0067/C0079/C0077/C0080/C0065/C0082/C0065/C0084/C0079/C0082/C0083 /C0261 SLCS132C − MARCH 1997 − REVISED MAY 1997 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to network ground. 2. Differential voltages are at IN+ with respect to IN−. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE T A = 25°C TA = 70°C POWER RATING D 725 mW 5.8 mW/°C 464 mW PW 525 mW 4.2 mW/°C 336 mW
/C0084/C0076/C0051/C0049/C0049/C0054/C0044 /C0084/C0076/C0051/C0049/C0049/C0054/C0089 /C0085/C0076/C0084/C0082/C0065/C0262/C0070/C0065/C0083/C0084 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0080/C0082/C0069/C0067/C0073/C0083/C0073/C0079/C0078 /C0067/C0079/C0077/C0080/C0065/C0082/C0065/C0084/C0079/C0082/C0083 /C0261 SLCS132C − MARCH 1997 − REVISED MAY 1997
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified operating free-air temperature, VDD = ±5 V, VLE = 0 (unless otherwise noted) PARAMETER TEST CONDITIONS † TL3116C TL3116I UNITPARAMETER TEST CONDITIONS † MIN TYP ‡ MAX MIN TYP ‡ MAX UNIT VIO Input offset voltage TA = 25°C 0.5 3 0.5 3 mVVIO Input offset voltage TA = full range 3.5 3.5 mV αVIO Temperature coefficient of input offset voltage −2.5 −2.8 µV/°C IIO Input offset current TA = 25°C 0.1 0.2 0.1 0.2 AIIO Input offset current TA = full range 0.3 0.35 µA IIB Input bias current TA = 25°C 0.7 1.1 0.7 1.1 AIIB Input bias current TA = full range 1.2 1.5 µA VICR Common-mode input VDD = ±5 V −5 2.5 −5 2.5 VVICR Common-mode input voltage range VDD = 5 V 0 2.5 0 2.5 V CMRR Common-mode rejection ratio −5 ≤ VIC ≤ 2.5 V 75 100 75 100 dB kSVR Supply-voltage rejection Positive supply: 4.6 V ≤ +VDD ≤ 5.4 V, TA = 25°C 60 80 60 80 dBkSVR Supply-voltage rejection ratio Negative supply: −7 V ≤ −VDD ≤ −2 V , TA = 25°C 80 100 80 100 dB VOL Low-level output voltage I(sink) = 4 mA, V+ ≤ 4.6 V, TA = 25°C 400 600 400 600 mVVOL Low-level output voltageI(sink) = 10 mA, V+ ≤ 4.6 V, TA = 25°C 750 750 mV VOH High-level output voltage V+ ≤ 4.6 V, I O = 1 mA, TA = 25°C 3.6 3.9 3.6 3.9 VVOH High-level output voltageV+ ≤ 4.6 V, I O = 10 mA, TA = 25°C 3.4 3.8 3.4 3.8 V ICC Positive supply current TA = full range 12.7 14.7 12.7 15 mAICC Negative supply current TA = full range −2.6 −3 mA VIL Low-level input voltage (LATCH ENABLE) 0.8 0.8 V VIH High-level input voltage (LATCH ENABLE) 2 2 V IIL Low-level input current (LATCH ENABLE) VLE = 0 0 1 0 1 µA IIL Low-level input current (LATCH ENABLE) VLE = 2 V 24 39 24 45 µA † Full range for the TL3116C is TA = 0°C to 70°C. Full range for the TL3116I is TA = −40°C to 85°C. ‡ All typical values are measures with TA = 25°C.
/C0084/C0076/C0051/C0049/C0049/C0054/C0044 /C0084/C0076/C0051/C0049/C0049/C0054/C0089 /C0085/C0076/C0084/C0082/C0065/C0262/C0070/C0065/C0083/C0084 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0080/C0082/C0069/C0067/C0073/C0083/C0073/C0079/C0078 /C0067/C0079/C0077/C0080/C0065/C0082/C0065/C0084/C0079/C0082/C0083 /C0261 SLCS132C − MARCH 1997 − REVISED MAY 1997 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics, VDD = ±5 V, VLE = 0 PARAMETER TEST CONDITIONS † TL3116C TL3116I UNITPARAMETER TEST CONDITIONS † MIN TYP MAX MIN TYP MAX UNIT ∆VI = 100 mV, TA = 25°C 9.9 12 9.9 12 tpd1 Propagation delay time‡ ∆VI = 100 mV, VOD = 5 mV TA = full range 9.9 14 9.9 15 nstpd1 Propagation delay time‡ ∆VI = 100 mV, TA = 25°C 8.2 10.3 8.2 10.3 ns ∆VI = 100 mV, VOD = 20 mV TA = full range 8.2 12.7 8.2 13.7 tsk(p) Pulse skew (|tpd+ − tpd−|) ∆VI = 100 mV, TA = 25°C VOD = 5 mV, 0.5 0.5 ns tsu Setup time, LATCH ENABLE 3.4 3.4 ns † Full range for the TL3116C is 0°C to 70°C. Full range for the TL3116I is −40°C to 85°C. ‡ tpd1 cannot be measured in automatic handling equipment with low values of overdrive. The TL3116 is 100% tested with a 1-V step and 500-mV overdrive at TA = 25°C only. Correlation tests have shown that tpd1 limits given can be ensured with this test, if additional dc tests are performed to ensure that all internal bias conditions are correct. For low overdrive conditions, VOS is added to the overdrive. TYPICAL CHARACTERISTICS Table of Graphs FIGURE vs Input voltage 2 ICC Positive supply current vs Frequency 3ICC Positive supply current vs Free-air temperature 4 ICC Negative supply current vs Free-air temperature 5 vs Overdrive voltage 6 vs Supply voltage 7 tpd Propagation delay time vs Input impedance 8tpd Propagation delay time vs Load capacitance 9 vs Free-air temperature 10 VIC Common-mode input voltage vs Free-air temperature 11 VIT Input threshold voltage (LATCH ENABLE)vs Free-air temperature 12 VO Output voltage vs Output source current 13 VO Output voltage vs Output sink current 14 II Input current (LATCH ENABLE) vs Input voltage 15
/C0084/C0076/C0051/C0049/C0049/C0054/C0044 /C0084/C0076/C0051/C0049/C0049/C0054/C0089 /C0085/C0076/C0084/C0082/C0065/C0262/C0070/C0065/C0083/C0084 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0080/C0082/C0069/C0067/C0073/C0083/C0073/C0079/C0078 /C0067/C0079/C0077/C0080/C0065/C0082/C0065/C0084/C0079/C0082/C0083 /C0261 SLCS132C − MARCH 1997 − REVISED MAY 1997
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TA = −40°C TA = 85°C TA = 25°C VI − Input Voltage − V − Positive Supply Current − mAICC ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VCC = ± 5 V TA = 25°C Figure 3 − Positive Supply Current − mA f − Frequency − MHz POSITIVE SUPPLY CURRENT vs FREQUENCY 01 0 1 102 ICC TA = 85°C TA = 25°C TA = −40°C ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ VCC = ± 5 V TA = 25°C Figure 4 −50 −25 0 25 50 75 100 125 POSITIVE SUPPLY CURRENT vs FREE-AIR TEMPERATURE − Positive Supply Current − mAICC TA − Free-Air Temperature − °C ÎÎÎÎÎ VCC = ± 5 V Figure 5 −50 −25 0 25 50 75 100 125 − 1.5 − 2 − 3 − 0.5 NEGATIVE SUPPLY CURRENT vs FREE-AIR TEMPERATURE − 1 − 2.5 − Negative Supply Current − mAICC TA − Free-Air Temperature − °C ÎÎÎÎ ÎÎÎÎ VCC = ± 5 V
/C0084/C0076/C0051/C0049/C0049/C0054/C0044 /C0084/C0076/C0051/C0049/C0049/C0054/C0089 /C0085/C0076/C0084/C0082/C0065/C0262/C0070/C0065/C0083/C0084 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0080/C0082/C0069/C0067/C0073/C0083/C0073/C0079/C0078 /C0067/C0079/C0077/C0080/C0065/C0082/C0065/C0084/C0079/C0082/C0083 /C0261 SLCS132C − MARCH 1997 − REVISED MAY 1997
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TA − Free-Air Temperature − °C Rising Edge Falling Edge10 − 50 − 25 0 25 50 − Propagation Delay Time − ns PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 75 100 125 tpd ÎÎÎÎÎ VCC = ± 5 V Figure 11 − 2 − 4 − 6 − 50 − 25 0 25 50 COMMON-MODE INPUT VOLTAGE vs FREE-AIR TEMPERATURE 75 100 125 − Common-Mode Input Voltage − V TA − Free-Air Temperature − °C VIC ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ VCC = 5 V (Upper Limit) VCC = ± 5 V (Upper Limit) ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ VCC = 5 V (Lower Limit) ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ VCC = ± 5 V (Lower Limit) Figure 12 TA − Free-Air Temperature − °C 0.6 0.4 −50 −25 0 25 50 1.6 1.8 INPUT THRESHOLD VOLTAGE (LATCH ENABLE) vs FREE-AIR TEMPERATURE 75 100 125 150 1.4 1.2 0.8 0.2 ÎÎÎÎ ÎÎÎÎ VCC = ± 5 V − Input Threshold Voltage (LATCH ENABLE) − VVIT Figure 13 3.8 051 0 4.6 4.8 15 20 − Output Voltage − V OUTPUT VOLTAGE vs OUTPUT SOURCE CURRENT VO IO(source) − Output Source Current − mA TA = −40°C TA = 85°C TA = 25°C 4.4 4.2 3.6 3.4 3.2 ÎÎÎÎÎ ÎÎÎÎÎ VCC = ± 5 V TA = 25°C
www.ti.com 5-Mar-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TL3116CD Obsolete Production SOIC (D) | 8 - - Call TI Call TI 0 to 70 3116C TL3116CDR Obsolete Production SOIC (D) | 8 - - Call TI Call TI 0 to 70 3116C TL3116CPW Obsolete Production TSSOP (PW) | 8 - - Call TI Call TI 0 to 70 T3116 TL3116CPWR Obsolete Production TSSOP (PW) | 8 - - Call TI Call TI 0 to 70 T3116 TL3116ID Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 85 3116I TL3116IDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 3116I TL3116IDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 3116I TL3116IPW Obsolete Production TSSOP (PW) | 8 - - Call TI Call TI -40 to 85 Z3116 TL3116IPWR Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 Z3116 TL3116IPWR.A Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 Z3116 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative Addendum-Page 1
www.ti.com 5-Mar-2026 and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL3116IDR SOIC D 8 2500 350.0 350.0 43.0 TL3116IPWR TSSOP PW 8 2000 353.0 353.0 32.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800
www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM
www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5
www.ti.com PACKAGE OUTLINE C TYP6.6 6.2
1.2 MAX
6X 0.65 8X 0.30 0.19 1.95 0.15 0.05 (0.15) TYP 0 - 8 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 3.1 2.9 B NOTE 4 4.5 4.3 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. 1 8
0.1 C A B
0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800
www.ti.com EXAMPLE BOARD LAYOUT (5.8)
0.05 MAX
0.05 MIN
8X (1.5) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 4 5 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN (5.8) 6X (0.65) 8X (0.45) 8X (1.5) (R ) TYP0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X
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