Amplifier

TL061

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LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS

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TL06xx Low-Power JFET-Input Operational Amplifiers datasheet (Rev. N)

Document overview

Manufacturer or author: Texas Instruments, Incorporated [SLOS078,N]
PDF pages: 58

Technical content

TL06xx Low-Power JFET-Input Operational Amplifiers

1 Features

Very low power consumption
Typical supply current: 200 μA (per amplifier)
Wide common-mode and differential voltage ranges
Low input bias and offset currents
Common-mode input voltage range includes VCC+
Output short-circuit protection
High input impedance: JFET-input stage
Internal frequency compensation
Latch-up-free operation
High slew rate: 3.5 V/μs typical
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

2 Applications

Tablets
White goods
Personal electronics
Computers

3 Description

The TL06x (TL061, TL062, and TL064) family of industry-standard operational amplifiers (op amps) mirror the TL07x and TL08x family of op amps with lower power consumption. These devices provide outstanding value for cost-sensitive applications, featuring high input impedance, wide bandwidth, high slew rate, and low input offset and input bias currents. High ESD (1.5 kV, HBM), integrated EMI and RF filters, and wide temperature operation enable the TL06x devices to be used in rugged and environmentally-demanding applications. Device Information PART NUMBER CHANNEL COUNT PACKAGE(1) PACKAGE SIZE(2) TL061x Single D (SOIC, 8) 4.90 mm × 6.00 mm P (PDIP, 8) 9.59 mm × 7.94 mm PS (SO, 8) 6.20 mm × 7.80 mm TL062x Dual D (SOIC, 8) 4.90 mm × 6.00 mm P (PDIP, 8) 9.59 mm × 7.94 mm PS (SO, 8) 6.20 mm × 7.80 mm JG (CDIP, 8) 9.58 mm × 7.62 mm PW (TSSOP, 8) 3.00 mm × 6.40 mm FK (LCCC, 20) 8.89 mm × 8.80 mm TL064x Quad D (SOIC, 14) 8.65 mm × 6.00 mm J (CDIP, 14) 19.4 mm × 7.90 mm N (PDIP, 14) 19.31 mm × 7.94 mm NS (SO, 14) 10.20 mm × 7.80 mm PW (TSSOP, 14) 5.00 mm × 6.40 mm W (CFP, 14) 21.78 mm × 9.21 mm FK (LCCC, 20) 8.89 mm × 8.80 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. RG RF VIN VOUT = 1 + V V OUT IN R R F G 1 + sR C1 1( ( ( ( 2/c112 R C1 1 f =/c45 3 dB Single-Pole, Low-Pass Filter TL061, TL061A, TL061B, TL062, TL062A, TL062B, TL064, TL064A, TL064B SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

6.7 Electrical Characteristics for TL06xC and

11 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision M (June 2023) to Revision N (August 2023) Page Changes from Revision L (May 2015) to Revision M (June 2023) Page

Updated Device Information with package size and channel count, and reordered packages based on
Added table note for input bias current and input offset current on Electrical Characteristics for TL06xC and
Added table note for input bias current and input offset current on Electrical Characteristics for TL06xxC and
Changed name of Electrical Characteristics for TL06xM and TL064M to Electrical Characteristics for TL06xM Changes from Revision K (January 2014) to Revision L (May 2015) Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information TL061, TL061A, TL061B, TL062, TL062A, TL062B, TL064, TL064A, TL064B SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023 www.ti.com

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Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

Changes from Revision J (September 2004) to Revision K (January 2014) Page www.ti.com TL061, TL061A, TL061B, TL062, TL062A, TL062B, TL064, TL064A, TL064B SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

5 Pin Configuration and Functions

2IN– 7 VCC+ 3IN+ 6 OUT 4VCC– 5 NC Not to scale Figure 5-1. TL061x D, P, and PS Package, 8-Pin SOIC, PDIP, and SO (Top View) 11OUT 8 VCC+ 21IN± 7 2OUT 31IN+ 6 2IN ± 4VCC± 5 2IN+ Not to scale Figure 5-2. TL062x D, JG, P, PS, and PW Package, 8-Pin SOIC, CDIP, PDIP, SO, and TSSOP (Top View) 11OUT 14 4OUT 21IN± 13 4IN ± 31IN+ 12 4IN+ 4VCC+ 11 VCC ± 52IN+ 10 3IN+ 62IN± 9 3IN ± 72OUT 8 3OUT Not to scale Figure 5-3. TL064x D, J, N, NS, PW, and W Package, 14-Pin SOIC, CDIP, PDIP, SO, TSSOP and CFP (Top View) 4NC 51IN± 6NC 71IN+ 8NC 9NC 10VCC± 11NC 122IN+ 13NC 14 NC 15 2IN ± 16 NC 17 2OUT 18 NC 19 NC

20 VCC+

Not to scale Figure 5-4. TL062 FK Package, 20-Pin LCCC (Top View) 41IN+ 5NC 6VCC+ 7NC 82IN+ 92IN± 102OUT 11NC 123OUT 133IN± 14 3IN+ 15 NC

16 VCC ±

19 4IN ± 20 4OUT 1 NC 2 1OUT 3 1IN ± Not to scale Figure 5-5. TL064 FK Package, 20-Pin LCCC (Top View) TL061, TL061A, TL061B, TL062, TL062A, TL062B, TL064, TL064A, TL064B SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023 www.ti.com

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Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME TL061 TL062 TL064 D, P, PS D, JG, P, PS, PW FK D, J, N, NS, PW, W FK 1IN– — 2 5 2 3 I Negative input 1IN+ — 3 7 3 4 I Positive input 1OUT — 1 2 1 2 O Output 2IN– — 6 15 6 9 I Negative input 2IN+ — 5 12 5 8 I Positive input 2OUT — 7 17 7 10 O Output 3IN– — — — 9 13 I Negative input 3IN+ — — — 10 14 I Positive input 3OUT — — — 8 12 O Output 4IN– — — — 13 19 I Negative input 4IN+ — — — 12 18 I Positive input 4OUT — — — 14 20 O Output IN– 2 — — — — I Negative input IN+ 3 — — — — I Positive input NC 8 — — Do not connect OFFSET N1 1 — — — — — Input offset adjustment OFFSET N2 5 — — — — — Input offset adjustment OUT 6 — — — — O Output VCC– 4 4 10 11 16 — Power supply VCC+ 7 8 20 4 6 — Power supply (1) I = input, O = output www.ti.com TL061, TL061A, TL061B, TL062, TL062A, TL062B, TL064, TL064A, TL064B SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC+ Supply voltage(2) 18 V VCC– –18 VID Differential input voltage(3) ±30 V VI Input voltage(2) (4) ±15 V Duration of output short circuit(5) Unlimited TJ Operating virtual junction temperature 150 °C Case temperature for 60 seconds FK package 260 °C Lead temperature 1.6 mm (1/16 inch) from case for 60 seconds J, JG, U, or W package 300 °C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds D, N, NS, P, PS, or PW package 260 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC−. (3) Differential voltages are at IN+, with respect to IN−. (4) The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less. (5) The output may be shorted to ground or to either supply. Temperature or supply voltages must be limited so that the dissipation rating is not exceeded.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) 1500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC+ Supply voltage 5 15 V VCC– Supply voltage –5 –15 V VCM Common-mode voltage VCC– + 4 VCC+ – 4 V TA Ambient temperature TL06xM –55 125 TL06xQ –40 125 TL06xI –40 85 TL06xC 0 70 TL061, TL061A, TL061B, TL062, TL062A, TL062B, TL064, TL064A, TL064B SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023 www.ti.com

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6.4 Thermal Information (TL061)

THERMAL METRIC(1) TL061 UNITD (SOIC) P (PDIP)

8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance(2) (3) 97 85 °C/W RθJC(top) Junction-to-case (top) thermal resistance(4) (5) — — °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) Maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/RθJA. Operating at the absolute maximum TJ of 150°C can affect reliability. (3) The package thermal impedance is calculated in accordance with JESD 51-7. (4) Maximum power dissipation is a function of TJ(max), RθJC, and TC. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TC) / RθJC. Operating at the absolute maximum TJ of 150°C can affect reliability. (5) The package thermal impedance is calculated in accordance with MIL-STD-883.

6.5 Thermal Information (TL062)

THERMAL METRIC(1) TL062 UNITD (SOIC) P (PDIP) PS (SO) PW (TSSOP) FK (LCCC) JG (CDIP)

8 PINS 8 PINS 8 PINS 8 PINS 20 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance(2) (3) 97 85 95 149 — — °C/W Rθ JC(top) Junction-to-case (top) thermal resistance(4) (5) — — — — 5.61 14.5 °C/W

6.6 Thermal Information (TL064)

THERMAL METRIC(1) TL064 UNITD (SOIC) N (PDIP) NS (SO) PS (SO) PW (TSSOP) FK (LCCC) J (CDIP) W (CFP)

14 PINS 14 PINS 14 PINS 8 PINS 14 PINS 20 PINS 14 PINS 14 PINS

RθJA Junction-to-ambient thermal resistance(2) (3) 86 80 76 95 113 — — — °C/W Rθ JC(top) Junction-to-case (top) thermal (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) Maximum power dissipation is a function of TJ(max), RθJC, and TC. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TC) / RθJC. Operating at the absolute maximum TJ of 150°C can affect reliability. (3) The package thermal impedance is calculated in accordance with MIL-STD-883. www.ti.com TL061, TL061A, TL061B, TL062, TL062A, TL062B, TL064, TL064A, TL064B SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

6.7 Electrical Characteristics for TL06xC and TL06xxC

VCC± = ±15 V, RL = 10 kΩ to (VCC+ + VCC–) / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS(1) TL061C, TL062C, TL064C TL061AC, TL062AC, TL064AC UNIT MIN TYP MAX MIN TYP MAX VIO Input offset voltage VO = 0, RS = 50 Ω TA = 25°C 3 15 3 6 mV TA = Full range 20 7.5 αVIO Temperature coefficient of input offset voltage VO = 0, RS = 50 Ω, TA = Full range 10 10 μV/°C IIO (3) Input offset current VO = 0 TA = 25°C 5 200 5 100 pA TA = Full range 5 3 nA IIB (3) Input bias current(2) VO = 0 TA = 25°C 30 400 30 200 pA TA = Full range 10 7 nA VICR Common-mode input voltage range TA = 25°C ±11 –12 to ±11 –12 to V VOM Maximum peak output voltage swing RL = 10 kΩ, TA = 25°C ±10 ±13.5 ±10 ±13.5 V RL ≥ 10 kΩ, TA = Full range ±10 ±10 AVD Large-signal differential voltage amplification VO = ±10 V, RL ≥ 2 kΩ TA = 25°C 3 6 4 6 V/mV TA = Full range 3 4 B1 Unity-gain bandwidth RL = 10 kΩ, TA = 25°C 1 1 MHz ri Input resistance TA = 25°C 1012 1012 Ω CMRR Common-mode rejection ratio VIC = VICRmin, VO = 0, RS = 50 Ω, TA = 25°C 70 86 80 86 dB kSVR Supply-voltage rejection ratio (ΔVCC±/ΔVIO) VCC = ±9 V to ±15 V, VO = 0, RS = 50 Ω, TA = 25°C 70 95 80 95 dB PD Total power dissipation (each amplifier) VO = 0, No load, TA = 25°C 6 7.5 6 7.5 mW ICC Supply current (each amplifier) VO = 0, No load, TA = 25°C 200 250 200 250 µA VO1/VO2 Crosstalk attenuation AVD = 100, TA = 25°C 120 120 dB (1) All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified. Full range for TA is 0°C to 70°C for TL06xC, TL06xAC, and TL06xBC and –40°C to 85°C for TL06xI. (2) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 6-12. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as possible. (3) Specified by design and characterization; not production tested. TL061, TL061A, TL061B, TL062, TL062A, TL062B, TL064, TL064A, TL064B SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023 www.ti.com

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6.8 Electrical Characteristics for TL06xxC and TL06xI

VCC± = ±15 V, RL = 10 kΩ to (VCC+ + VCC–) / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS(1) TL061BC, TL062BC, TL064BC TL061I, TL062I, TL064I UNIT MIN TYP MAX MIN TYP MAX VIO Input offset voltage VO = 0, RS = 50 Ω TA = 25°C 2 3 3 6 mV TA = Full range 5 9 αVIO Temperature coefficient of input offset voltage VO = 0, RS = 50 Ω, TA = Full range 10 10 μV/°C IIO (3) Input offset current VO = 0 TA = 25°C 5 100 5 100 pA TA = Full range 3 10 nA IIB (3) Input bias current(2) VO = 0 TA = 25°C 30 200 30 200 pA TA = Full range 7 20 nA VICR Common-mode input voltage range TA = 25°C ±11 –12 to ±11 –12 to V VOM Maximum peak output voltage swing RL = 10 kΩ, TA = 25°C ±10 ±13.5 ±10 ±13.5 V RL ≥ 10 kΩ, TA = Full range ±10 ±10 AVD Large-signal differential voltage amplification VO = ±10 V, RL ≥ 2 kΩ TA = 25°C 4 6 4 6 V/mV TA = Full range 4 4 B1 Unity-gain bandwidth RL = 10 kΩ, TA = 25°C 1 1 MHz ri Input resistance TA = 25°C 1012 1012 Ω CMRR Common-mode rejection ratio VIC = VICRmin, VO = 0, RS = 50 Ω, TA = 25°C 80 86 80 86 dB kSVR Supply-voltage rejection ratio (ΔVCC±/ΔVIO) VCC = ±9 V to ±15 V, VO = 0, RS = 50 Ω, TA = 25°C 80 95 80 95 dB PD Total power dissipation (each amplifier) VO = 0, No load, TA = 25°C 6 7.5 6 7.5 mW ICC Supply current (each amplifier) VO = 0, No load, TA = 25°C 200 250 200 250 µA VO1/VO2 Crosstalk attenuation AVD = 100, TA = 25°C 120 120 dB (1) All characteristics are measured under open-loop conditions with zero common-mode input voltage, unless otherwise specified. Full range for TA is 0°C to 70°C for TL06xC, TL06xAC, and TL06xBC and –40°C to 85°C for TL06xI. (2) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 6-12. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as possible. (3) Assured by design and characterization; not production tested. www.ti.com TL061, TL061A, TL061B, TL062, TL062A, TL062B, TL064, TL064A, TL064B SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

6.9 Electrical Characteristics for TL06xM

VCC± = ±15 V, RL = 10 kΩ to (VCC+ + VCC–) / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS(2) TL061M, TL062M TL064M UNIT MIN TYP MAX MIN TYP MAX VIO Input offset voltage VO = 0, RS = 50 Ω TA = 25°C 3 6 3 9 mVTA = –55°C to 125°C 9 15 αVIO Temperature coefficient of input offset voltage VO = 0, RS = 50 Ω, TA = –55°C to 125°C 10 10 μV/°C IIO (4) Input offset current VO = 0 TA = 25°C 5 100 5 100 pA nA TA = 125°C 20 20 IIB (4) Input bias current(3) VO = 0 TA = 25°C 30 200 30 200 pA nA TA = 125°C 50 50 VICR Common-mode input voltage range TA = 25°C ±11 –12 to ±11 –12 to V VOM Maximum peak output voltage swing RL = 10 kΩ, TA = 25°C ±10 ±13.5 ±10 ±13.5 V RL ≥ 10 kΩ, TA = –55°C to 125°C ±10 ±10 AVD Large-signal differential voltage amplification VO = ±10 V, RL ≥ 2 kΩ TA = 25°C 4 6 4 6 V/mVTA = –55°C to 125°C 4 4 B1 Unity-gain bandwidth RL = 10 kΩ, TA = 25°C 1 1 MHz ri Input resistance TA = 25°C 1012 1012 Ω CMRR Common-mode rejection ratio VIC = VICRmin, VO = 0, RS = 50 Ω, TA = 25°C 80 86 80 86 dB kSVR Supply-voltage rejection ratio (ΔVCC±/ΔVIO) VCC = ±9 V to ±15 V, VO = 0, RS = 50 Ω, TA = 25°C 80 95 80 95 dB PD Total power dissipation (each amplifier) VO = 0, No load, TA = 25°C 6 7.5 6 7.5 mW ICC Supply current (each amplifier) VO = 0, No load, TA = 25°C 200 250 200 250 µA VO1/VO2 Crosstalk attenuation AVD = 100, TA = 25°C 120 120 dB (1) This parameter is not production tested. (2) All characteristics are measured under open-loop conditions, with zero common-mode voltage, unless otherwise specified. (3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 6-12. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as possible. (4) Specified by design and characterization; not production tested.

6.10 Operating Characteristics

VCC± = ±15 V, TA= 25°C, RL = 10 kΩ to (VCC+ + VCC–) / 2 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SR Slew rate at unity gain(1) VI = 10 V, RL = 10 kΩ, CL = 100 pF, see Figure 7-1 1.5 3.5 V/μs tr Rise-time VI = 20 V, RL = 10 kΩ, CL = 100 pF, see Figure 7-1 0.2 μs Overshoot factor 10% Vn Equivalent input noise voltage RS = 20 Ω f = 1 kHz 30 nV/√ Hz (1) Slew rate at –55°C to 125°C is 0.7 V/μs min. TL061, TL061A, TL061B, TL062, TL062A, TL062B, TL064, TL064A, TL064B SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023 www.ti.com

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Typical Characteristics (continued) Data at high and low temperatures are applicable only within the specified operating free-air temperature ranges of the various devices. TA = 25°C No Signal No Load 2 4 6 8 10 12 14 16 100 150 200 250 |VCC±| − Supply Voltage − V ICC − Supply Current − µA ICC Figure 6-7. Supply Current vs Supply Voltage ICC − Supply Current − µA −75 TA − Free-Air Temperature − °C 100 150 200 250 ICC VCC± = ±15 V No Signal No Load Figure 6-8. Supply Current vs Free-Air Temperature −75 TA − Free-Air Temperature − °C −50 −25 0 25 50 75 100 125 VCC± = ±15 V No Signal No Load TL064 TL062 TL061 PD − Total Power Dissipation − mWPD Figure 6-9. Total Power Dissipation vs Free-Air Temperature CMRR − Common-Mode Rejection Ratio − dB 1251007550250−25−50 TA − Free-Air Temperature − °C −75 VCC± = ±15 V RL = 10 kΩ Figure 6-10. All Except TL06_C Common-Mode Rejection Ratio vs Free-Air Temperature 0.7 Normalized Unity-Gain Bandwidth and Slew Rate 1251007550250−25−50 TA − Free-Air Temperature − °C −75 0.8 0.9 1.1 1.2 1.3 1.02 1.01 0.99 0.98 0.97 Normalized Phase Shift 1.03 VCC± = ±15 V RL = 10 kΩ f = B1 for Phase Shift Unity-Gain Bandwidth (left scale) Phase Shift (right scale) Slew Rate (left scale) Figure 6-11. Normalized Unity-Gain Bandwidth, Slew Rate, and Phase Shift vs Free-Air Temperature 1251007550250−25 0.01 IIB − Input Bias Current − nA −50 TA − Free-Air Temperature − °C 0.04 0.1 0.4 100 VCC± = ±15 V IIB Figure 6-12. Input Bias Current vs Free-Air Temperature TL061, TL061A, TL061B, TL062, TL062A, TL062B, TL064, TL064A, TL064B SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023 www.ti.com

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7 Parameter Measurement Information

RL = 2 kΩ CL = 100 pF OUT Figure 7-1. Unity-Gain Amplifier VI 10 kΩ 1 kΩ RL CL = 100 pF OUT Figure 7-2. Gain-of-10 Inverting Amplifier 100 kΩ 1.5 kΩ VCC− TL061 IN− OUT IN+ Figure 7-3. Input Offset-Voltage Null Circuit TL061, TL061A, TL061B, TL062, TL062A, TL062B, TL064, TL064A, TL064B SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023 www.ti.com

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8 Detailed Description

8.1 Overview

8.2 Functional Block Diagram

VIN+ VIN– (Ground) VBIAS2 VBIAS1 Class AB Control Circuitry VO Reference Current

8.3 Feature Description

8.3.1 Common-Mode Rejection Ratio

The common-mode rejection ratio (CMRR) of an amplifier is a measure of how well the device rejects unwanted input signals common to both input leads. It is found by taking the ratio of the change in input offset voltage to the change in the input voltage and converting to decibels. Ideally the CMRR is infinite, but in practice, amplifiers are designed to have it as high as possible. The CMRR of this device is 86 dB.

8.3.2 Slew Rate

The slew rate is the rate at which an operational amplifier can change its output when there is a change on the input. These devices have a 3.5-V/μs slew rate.

8.4 Device Functional Modes

These devices are powered on when the supply is connected. This device can be operated as a single supply operational amplifier or dual supply amplifier depending on the application. www.ti.com TL061, TL061A, TL061B, TL062, TL062A, TL062B, TL064, TL064A, TL064B SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

9 Applications and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The TL06x series of operational amplifiers can be used in countless applications. The few applications in this section show principles used in all applications of these parts.

9.2 Typical Applications

9.2.1 Inverting Amplifier Application

A typical application for an operational amplifier in an inverting amplifier. This amplifier takes a positive voltage on the input, and makes it a negative voltage of the same magnitude. In the same manner, it also makes negative voltages positive. Vsup+ VOUT RF VIN RI Vsup- Figure 9-1. Schematic for Inverting Amplifier Application

9.2.1.1 Design Requirements

The supply voltage must be chosen such that it is larger than the input voltage range and output range. For instance, this application will scale a signal of ±0.5 V to ±1.8 V. Setting the supply at ±12 V is sufficient to accommodate this application.

9.2.1.2 Detailed Design Procedure

Determine the gain required by the inverting amplifier: A V = V OU T VI N (1) A V = 1.8 − 0.5 = − 3.6 (2) Once the desired gain is determined, choose a value for RI or RF. Choose a value in the k Ω range to limit currents in the amplifier circuit to the mA range. This example will choose 10 k Ω for RI which means 36 k Ω will be used for RF. This was determined by Equation 3. A V = − RF RI (3) TL061, TL061A, TL061B, TL062, TL062A, TL062B, TL064, TL064A, TL064B SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023 www.ti.com

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9.2.1.3 Application Curve

-1.5 -0.5 0.5 1.5 0 0.5 1 1.5 2 Volts Time (ms) VIN VOUT Figure 9-2. Input and Output Voltages of the Inverting Amplifier

9.3 System Examples

9.3.1 General Applications

VCC− 100 kΩ Input B 10 kΩ 0.1% 0.1% 10 kΩ VCC− VCC+ TL064 Input A VCC+ TL064 VCC− 100 kΩ 10 kΩ 0.1% 10 kΩ 0.1% TL064 VCC− VCC+ 100 kΩ 100 kΩ Output 1 MΩ Figure 9-3. Instrumentation Amplifier TL061 −15 V 15 V Output 1 kΩ 9.1 kΩ 3.3 kΩ CF = 3.3 µF RF = 100 kΩ 3.3 kΩ F F 1f 2π R C/c61 /c180 /c180 Figure 9-4. 0.5-Hz Square-Wave Oscillator TL061+ C1 C2 C3 VCC− VCC+ OutputInput O R1 R2 2 R3 1.5 MΩ C3C1 C2 110 pF2 1f 1 kHz2π R1 C 1 /c61 /c61 /c180 /c61 /c61 /c61 /c61 /c61 /c61 /c180 /c180 Figure 9-5. High-Q Notch Filter TL064 Output C VCC+ VCC+ Output BTL064 VCC+ Output ATL064 +VCC+ TL064 VCC+ 100 kΩ 100 µF Input 1 µF 1 MΩ 100 kΩ 100 kΩ Figure 9-6. Audio-Distribution Amplifier www.ti.com TL061, TL061A, TL061B, TL062, TL062A, TL062B, TL064, TL064A, TL064B SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

10 kΩ 15 V Output −15 V 5 kΩ 100 pF TL061 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ Figure 9-7. Low-Level Light Detector Preamplifier TL061 0.1 Fµ 10 kΩ 50 Ω 250 kΩ Output 1 MΩ VCC+ 10 kΩ 10 kΩ 0.1 µF Figure 9-8. AC Amplifier

1.2 MΩ 100 kΩ

20 µF 0.1 µF 47 kΩ TL061 2.7 kΩ 270 Ω 0.003 µF 0.001 µF 0.002 µF 1 µF 10 kΩ 100 kΩ 50 kΩ 0.06 µF 50 kΩ 10 kΩ 100 kΩ 1 kΩ 0.06 µF 10 kΩ 0.02 µF 100 kΩ Figure 9-9. Microphone Preamplifier With Tone Control IN− IN+ 100 kΩ TL062 TL062 1 kΩ 1 kΩ 100 kΩ Output Figure 9-10. Instrumentation Amplifier TL061, TL061A, TL061B, TL062, TL062A, TL062B, TL064, TL064A, TL064B SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023 www.ti.com

18 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

220 kΩ 0.00375 µF TL062 10 pF 68 kΩ 0.003 µF 0.03 µF 0.03 µF 10 kΩ 3.3 kΩ 0.003 µF VCC− VCC+ Output Input VCC− VCC+ 10 pF MIN MAX 100 kΩ Treble MIN MAX 100 kΩ Bass 10 kΩ 10 kΩ 0.01 µF 27 kΩ 100 Ω Balance 100 Ω 50 pF 75 µF 47 µF 5 kΩ Gain 47 kΩ 1 µF TA = 25°C VCC± = ±15 V Max Treble Max Bass 200 10 k 4 k2 k1 k40040 100 −10 −15 −20 −25 20 k f − Frequency − Hz Voltage Amplification − dB IC PREAMPLIFIER RESPONSE CHARACTERISTICS Min Treble Min Bass Figure 9-11. IC Preamplifier

9.4 Power Supply Recommendations

Supply voltages larger than 36 V for a single supply, or outside the range of ±18 V for a dual supply can permanently damage the device (see the Absolute Maximum Ratings). Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout section. www.ti.com TL061, TL061A, TL061B, TL062, TL062A, TL062B, TL064, TL064A, TL064B SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

9.5 Layout

9.5.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supply applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to Circuit Board Layout Techniques.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace.
Place the external components as close to the device as possible. Keeping RF and RG close to the inverting input minimizes parasitic capacitance, as shown in Layout Examples.
Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.

9.5.2 Layout Examples

Figure 9-12. Operational Amplifier Schematic for Noninverting Configuration NC VCC+IN1í IN1+ VCCí NC OUT NC RG RIN RF GND VIN VS-GND VS+ GND Run the input traces as far away from the supply lines as possible Only needed for dual-supply operation Place components close to device and to each other to reduce parasitic errors Use low-ESR, ceramic bypass capacitor (or GND for single supply) Ground (GND) plane on another layerVOUT Figure 9-13. Operational Amplifier Board Layout for Noninverting Configuration TL061, TL061A, TL061B, TL062, TL062A, TL062B, TL064, TL064A, TL064B SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023 www.ti.com

20 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

10 Device and Documentation Support

10.1 Documentation Support

10.1.1 Related Documentation

For related documentation, see the following:

Texas Instruments, Circuit Board Layout Techniques chapter extracts

10.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

10.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser based versions of this data sheet, refer to the left hand navigation. www.ti.com TL061, TL061A, TL061B, TL062, TL062A, TL062B, TL064, TL064A, TL064B SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

www.ti.com 15-Jul-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) 81023022A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 81023022A TL062MFKB 8102302PA Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 8102302PA TL062M 81023032A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 81023032A TL064MFKB 8102303CA Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8102303CA TL064MJB 8102303DA Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8102303DA TL064MWB TL061ACD Obsolete Production SOIC (D) | 8 - - Call TI Call TI 0 to 70 061AC TL061ACDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 061AC TL061ACDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 061AC TL061ACP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL061ACP TL061ACP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL061ACP TL061BCP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL061BCP TL061BCP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL061BCP TL061BCPE4 Active Production PDIP (P) | 8 50 | TUBE - Call TI Call TI 0 to 70 TL061CD Obsolete Production SOIC (D) | 8 - - Call TI Call TI 0 to 70 TL061C TL061CDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL061C TL061CDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL061C TL061CP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL061CP TL061CP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL061CP TL061CPSR Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T061 TL061CPSR.A Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T061 TL061ID Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 85 TL061I TL061IDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL061I TL061IDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL061I TL061IDRG4 Active Production SOIC (D) | 8 2500 | LARGE T&R - Call TI Call TI -40 to 85 TL061IP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL061IP Addendum-Page 1

www.ti.com 15-Jul-2026 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TL061IP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL061IP TL061IPE4 Active Production PDIP (P) | 8 50 | TUBE - Call TI Call TI -40 to 85 TL062ACD Obsolete Production SOIC (D) | 8 - - Call TI Call TI 0 to 70 062AC TL062ACDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 062AC TL062ACDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 062AC TL062ACDRG4 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 062AC TL062ACP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL062ACP TL062ACP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL062ACP TL062ACPSR Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T062A TL062ACPSR.A Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T062A TL062BCD Obsolete Production SOIC (D) | 8 - - Call TI Call TI 0 to 70 062BC TL062BCDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 062BC TL062BCDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 062BC TL062BCP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL062BCP TL062BCP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL062BCP TL062CD Obsolete Production SOIC (D) | 8 - - Call TI Call TI 0 to 70 TL062C TL062CDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL062C TL062CDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL062C TL062CDRE4 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL062C TL062CDRG4 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL062C TL062CP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL062CP TL062CP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL062CP TL062CPE4 Active Production PDIP (P) | 8 50 | TUBE - Call TI Call TI 0 to 70 TL062CPS Active Production SO (PS) | 8 80 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T062 TL062CPS.A Active Production SO (PS) | 8 80 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T062 TL062CPSR Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T062 TL062CPSR.A Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T062 TL062CPW Obsolete Production TSSOP (PW) | 8 - - Call TI Call TI 0 to 70 T062 TL062CPWR Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T062 TL062CPWR.A Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T062 TL062CPWRG4 Obsolete Production TSSOP (PW) | 8 - - Call TI Call TI 0 to 70 T062 Addendum-Page 2

www.ti.com 15-Jul-2026 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TL062ID Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 85 TL062I TL062IDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL062I TL062IDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL062I TL062IP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL062IP TL062IP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL062IP TL062IPWR Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 Z062 TL062IPWR.A Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 Z062 TL062IPWRG4 Active Production TSSOP (PW) | 8 2000 | LARGE T&R - Call TI Call TI -40 to 85 TL062MFKB Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 81023022A TL062MFKB TL062MFKB.A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 81023022A TL062MFKB TL062MJG Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 TL062MJG TL062MJG.A Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 TL062MJG TL062MJGB Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 8102302PA TL062M TL062MJGB.A Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 8102302PA TL062M TL064ACD Obsolete Production SOIC (D) | 14 - - Call TI Call TI 0 to 70 TL064AC TL064ACDR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL064AC TL064ACDR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL064AC TL064ACN Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL064ACN TL064ACN.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL064ACN TL064BCD Obsolete Production SOIC (D) | 14 - - Call TI Call TI 0 to 70 TL064BC TL064BCDR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL064BC TL064BCDR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL064BC TL064BCN Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL064BCN TL064BCN.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL064BCN TL064CD Obsolete Production SOIC (D) | 14 - - Call TI Call TI 0 to 70 TL064C TL064CDR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL064C TL064CDR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL064C TL064CN Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL064CN Addendum-Page 3

www.ti.com 15-Jul-2026 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TL064CN.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL064CN TL064CNSR Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL064 TL064CNSR.A Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL064 TL064CPW Obsolete Production TSSOP (PW) | 14 - - Call TI Call TI 0 to 70 T064 TL064CPWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM 0 to 70 T064 TL064CPWR.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T064 TL064CPWRG4 Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 T064 TL064ID Obsolete Production SOIC (D) | 14 - - Call TI Call TI -40 to 85 TL064I TL064IDR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL064I TL064IDR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL064I TL064IDRG4 Obsolete Production SOIC (D) | 14 - - Call TI Call TI -40 to 85 TL064I TL064IN Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL064IN TL064IN.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL064IN TL064INE4 Active Production PDIP (N) | 14 25 | TUBE - Call TI Call TI -40 to 85 TL064INS Active Production SOP (NS) | 14 50 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL064I TL064INS.A Active Production SOP (NS) | 14 50 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL064I TL064INSR Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL064I TL064INSR.A Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL064I TL064IPWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 Z064 TL064IPWR.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 Z064 TL064MFKB Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 81023032A TL064MFKB TL064MFKB.A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 81023032A TL064MFKB TL064MJ Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 TL064MJ TL064MJ.A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 TL064MJ TL064MJB Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8102303CA TL064MJB TL064MJB.A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8102303CA TL064MJB TL064MWB Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8102303DA TL064MWB Addendum-Page 4

www.ti.com 15-Jul-2026 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TL064MWB.A Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8102303DA TL064MWB (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TL062, TL062M, TL064, TL064M :

Catalog : TL062, TL064
Military : TL062M , TL064M Addendum-Page 5

www.ti.com 15-Jul-2026 NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product
Military - QML certified for Military and Defense Applications Addendum-Page 6

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL061ACDR SOIC D 8 2500 353.0 353.0 32.0 TL061CDR SOIC D 8 2500 353.0 353.0 32.0 TL061CPSR SO PS 8 2000 353.0 353.0 32.0 TL061IDR SOIC D 8 2500 353.0 353.0 32.0 TL062ACDR SOIC D 8 2500 353.0 353.0 32.0 TL062ACPSR SO PS 8 2000 353.0 353.0 32.0 TL062BCDR SOIC D 8 2500 353.0 353.0 32.0 TL062CDR SOIC D 8 2500 353.0 353.0 32.0 TL062CPSR SO PS 8 2000 353.0 353.0 32.0 TL062CPWR TSSOP PW 8 2000 353.0 353.0 32.0 TL062IDR SOIC D 8 2500 353.0 353.0 32.0 TL062IPWR TSSOP PW 8 2000 353.0 353.0 32.0 TL064ACDR SOIC D 14 2500 353.0 353.0 32.0 TL064BCDR SOIC D 14 2500 353.0 353.0 32.0 TL064CDR SOIC D 14 2500 353.0 353.0 32.0 TL064CDR SOIC D 14 2500 333.2 345.9 28.6 TL064CDR SOIC D 14 2500 353.0 353.0 32.0 TL064CNSR SOP NS 14 2000 353.0 353.0 32.0 Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL064CPWR TSSOP PW 14 2000 356.0 356.0 35.0 TL064CPWR TSSOP PW 14 2000 353.0 353.0 32.0 TL064CPWR TSSOP PW 14 2000 353.0 353.0 32.0 TL064CPWRG4 TSSOP PW 14 2000 356.0 356.0 35.0 TL064CPWRG4 TSSOP PW 14 2000 356.0 356.0 35.0 TL064IDR SOIC D 14 2500 353.0 353.0 32.0 TL064INSR SOP NS 14 2000 353.0 353.0 32.0 TL064IPWR TSSOP PW 14 2000 353.0 353.0 32.0 TL064IPWR TSSOP PW 14 2000 353.0 353.0 32.0 Pack Materials-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) 81023022A FK LCCC 20 55 506.98 12.06 2030 NA 81023032A FK LCCC 20 55 506.98 12.06 2030 NA 8102303DA W CFP 14 25 506.98 26.16 6220 NA TL061ACP P PDIP 8 50 506 13.97 11230 4.32 TL061ACP.A P PDIP 8 50 506 13.97 11230 4.32 TL061BCP P PDIP 8 50 506 13.97 11230 4.32 TL061BCP.A P PDIP 8 50 506 13.97 11230 4.32 TL061CP P PDIP 8 50 506 13.97 11230 4.32 TL061CP.A P PDIP 8 50 506 13.97 11230 4.32 TL061IP P PDIP 8 50 506 13.97 11230 4.32 TL061IP.A P PDIP 8 50 506 13.97 11230 4.32 TL062ACP P PDIP 8 50 506 13.97 11230 4.32 TL062ACP.A P PDIP 8 50 506 13.97 11230 4.32 TL062BCP P PDIP 8 50 506 13.97 11230 4.32 TL062BCP.A P PDIP 8 50 506 13.97 11230 4.32 TL062CP P PDIP 8 50 506 13.97 11230 4.32 TL062CP.A P PDIP 8 50 506 13.97 11230 4.32 TL062CPS PS SOP 8 80 530 10.5 4000 4.1 TL062CPS.A PS SOP 8 80 530 10.5 4000 4.1 TL062IP P PDIP 8 50 506 13.97 11230 4.32 TL062IP.A P PDIP 8 50 506 13.97 11230 4.32 TL062MFKB FK LCCC 20 55 506.98 12.06 2030 NA TL062MFKB.A FK LCCC 20 55 506.98 12.06 2030 NA TL064ACN N PDIP 14 25 506 13.97 11230 4.32 TL064ACN.A N PDIP 14 25 506 13.97 11230 4.32 TL064BCN N PDIP 14 25 506 13.97 11230 4.32 TL064BCN.A N PDIP 14 25 506 13.97 11230 4.32 TL064CN N PDIP 14 25 506 13.97 11230 4.32 TL064CN.A N PDIP 14 25 506 13.97 11230 4.32 Pack Materials-Page 5

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TL064IN N PDIP 14 25 506 13.97 11230 4.32 TL064IN.A N PDIP 14 25 506 13.97 11230 4.32 TL064INS NS SOP 14 50 530 10.5 4000 4.1 TL064INS.A NS SOP 14 50 530 10.5 4000 4.1 TL064MFKB FK LCCC 20 55 506.98 12.06 2030 NA TL064MFKB.A FK LCCC 20 55 506.98 12.06 2030 NA TL064MWB W CFP 14 25 506.98 26.16 6220 NA TL064MWB.A W CFP 14 25 506.98 26.16 6220 NA Pack Materials-Page 6

www.ti.com PACKAGE OUTLINE 10.16 9.00 7.11 6.22 1.60 0.38 6X 2.54 8X 0.58 0.38 4X 1.65 1.14 0.51 MIN 3.30 MIN

5.08 MAX

7.87 7.37 0.36

0.20 TYP

4X (0.94) CDIP - 5.08 mm max heightJG0008A CERAMIC DUAL IN-LINE PACKAGE 4230036/A 09/2023 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package can be hermetically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification. 5. Falls within MIL STD 1835 GDIP1-T8 SEATING PLANE

0.25 C A B

A B C

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

(7.62) 6X (2.54) 8X ( 1) THRU 7X ( 1.6) (1.6) (R0.05) TYP CDIP - 5.08 mm max heightJG0008A CERAMIC DUAL IN-LINE PACKAGE 4230036/A 09/2023 LAND PATTERN EXAMPLE NON SOLDER MASK DEFINED SCALE: 9X SOLDER MASK OPENING TYP METAL TYP SYMM SYMM 4 5

www.ti.com PACKAGE OUTLINE C TYP6.2 5.8

1.75 MAX

12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14 0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800

www.ti.com EXAMPLE BOARD LAYOUT (5.4)

0.07 MAX

0.07 MIN

14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. LCCC - 2.03 mm max heightFK 20 LEADLESS CERAMIC CHIP CARRIER8.89 x 8.89, 1.27 mm pitch 4229370\\/A\\

www.ti.com PACKAGE OUTLINE C 14X .008-.014 [0.2-0.36]TYP -150 AT GAGE PLANE -.314 .308 -7.97 7.83 [ ] 14X -.026 .014 -1.65 1.15 [ ] .2 MAX TYP [5.08] .13 MIN TYP [3.3] TYP-.060 .015 -1.52 0.38 [ ] 4X .005 MIN [0.13] 12X .100 [2.54] .015 GAGE PLANE [0.38] A -.785 .754 -19.9419.15 [ ] B -.283 .245 -7.19 6.22 [ ] CDIP - 5.08 mm max heightJ0014A CERAMIC DUAL IN LINE PACKAGE 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. 7 8 PIN 1 ID (OPTIONAL) SCALE 0.900 SEATING PLANE .010 [0.25] C A B

www.ti.com EXAMPLE BOARD LAYOUT ALL AROUND [0.05] MAX .002 .002 MAX [0.05] ALL AROUND SOLDER MASK OPENING METAL (.063) [1.6] (R.002 ) TYP [0.05] 14X ( .039) [1] ( .063) [1.6] 12X (.100 ) [2.54] (.300 ) TYP [7.62] CDIP - 5.08 mm max heightJ0014A CERAMIC DUAL IN LINE PACKAGE 4214771/A 05/2017 LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X SEE DETAIL A SEE DETAIL B SYMM SYMM 7 8 DETAIL A SCALE: 15X SOLDER MASK OPENING METAL DETAIL B 13X, SCALE: 15X

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

www.ti.com PACKAGE OUTLINE C 12X 0.65 3.9 14X 0.30 0.17 6.6

6.2 TYP

1.2 MAX

0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MIN

14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 7 8 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 7 8

www.ti.com PACKAGE OUTLINE C TYP6.6 6.2 6X 0.65 8X 0.30 0.19 1.95 0.15 0.05 (0.15) TYP 0 - 8 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 3.1 2.9 B NOTE 4 4.5 4.3 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. 1 8 0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT (5.8) 8X (1.5) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 4 5 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.8) 6X (0.65) 8X (0.45) 8X (1.5) (R ) TYP0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

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Selected Specification

Texas Instruments TL061 overview.

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Overview

TL061 is listed in the Amplifier category. Available datasheets include documents from STMicroelectronics, SYC Electronica, Texas Instruments. DigiCamel provides a local PDF and searchable HTML technical text for online reference.

Summary

LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS

Description

LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS

Source title TL061 Datasheet(PDF) - Texas Instruments

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