TFP401A

TFP401x TI PanelBus Digital Receiver datasheet (Rev. H)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SLDS120,H]
• PDF pages: 35

Technical content

TFP401x TI PanelBus™ Digital Receiver

1 Features

• Supports pixel rates up to 165 MHz (including 1080p and WUXGA at 60 Hz)
• Digital visual interface (DVI) specification compliant 1
• True-color, 24-bit/pixel, 16.7M colors at 1 or 2 pixels per clock
• Laser trimmed internal termination resistors for optimum fixed impedance matching
• Skew tolerant up to one pixel-clock cycle
• 4× oversampling
• Reduced power consumption – 1.8-V core operation with 3.3-V I/Os and supplies 2
• Reduced ground bounce using time-staggered pixel outputs
• Low noise and good power dissipation using TI PowerPAD™ packaging
• Advanced technology using TI 0.18-µm EPIC-5 CMOS process
• TFP401A incorporates HSYNC jitter immunity 3

2 Applications

• High-definition TV
• HD PC monitors
• Digital video
• HD projectors
• DVI/HDMI™ receivers (HDMI video-only)

3 Description

The Texas Instruments TFP401 and TFP401A are TI PanelBus™ flat-panel display products, part of a comprehensive family of end-to-end DVI 1.0 compliant solutions. Targeted primarily at desktop LCD monitors and digital projectors, the TFP401/401A finds applications in any design requiring high-speed digital interface. The TFP401 and TFP401A supports display resolutions up to 1080p and WUXGA in 24-bit true- color pixel format. The TFP401 and TFP401A offers design flexibility to drive one or two pixels per clock, supports TFT or DSTN panels, and provides an option for time-staggered pixel outputs for reduced ground bounce. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TFP401 HTQFP (100) 14.00 mm × 14.00 mm TFP401A (1) For all available packages, see the orderable addendum at the end of the data sheet. Copyright © 2016, Texas Instruments Incorporated TFP401 Diagram 1 The Digital Visual Interface Specification, DVI, is an industry standard developed by the Digital Display Working Group (DDWG) for high-speed digital connection to digital displays. The TPF401 and TFP401A are compliant with the DVI Specification Rev. 1.0. 2 The TFP401/401A has an internal voltage regulator that provides the 1.8-V core power supply from the external 3.3-V supplies. 3 The TFP401A incorporates additional circuitry to create a stable HSYNC from DVI transmitters that introduce undesirable jitter on the transmitted HSYNC signal. TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

13.1 Receiving Notification of Documentation Updates..26

14 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (May 2016) to Revision H (March 2022) Page

• Added sentence to end of first paragraph that recommends soldering package thermal pad to PCB in order to Changes from Revision F (February 2015) to Revision G (May 2016) Page Changes from Revision E (July 2013) to Revision F (February 2015) Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 www.ti.com

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5 Description (continued)

PowerPAD advanced packaging technology results in best-of-class power dissipation, footprint, and ultralow ground inductance. The TFP401 and TFP401A combines PanelBus circuit innovation with TI's advanced 0.18-µm EPIC-5 CMOS process technology, along with TI PowerPAD package technology to achieve a reliable, low-powered, low-noise, high-speed digital interface solution.

6 Pin Configuration and Functions

51525354555657585960616263646566676869707172737475 25242322212019181716151413121110987654321 QO1 QO0 HSYNC DE ODCK OVDD CTL3 CTL2 CTL1 GND DVDD QE23 QE22 QE20 QE19 QE17 QE16 OVDD OGND QE15 QE14 OGND OVDD AGND Rx2+ Rx2− AVDD AGND AVDD Rx1− AGND AGND Rx0+ Rx0− AGND RxC+ RxC− AVDD EXT_RES PGND RSVD OCK_INV QO22 QO21 QO20QO18 QO17 QO16 GND DVDD QO13 QO12 Qo9 QO8 OGND OVDD QO7 QO6 QO5 QO4 QO3 QO2 DFOPDST PIXSGNDDVDDSTAGPDOQE0 QE2 QE3 QE4 QE5 QE6 OVDDOGND QE9 QE11QE12 QE13QE7 QO23 AVDD QO11QO15 QO14 OGND QE18 SCDT QE8QE1 QE10 QE21 VSYNC QO10QO19 Rx1+ PVDD Thermal Pad Figure 6-1. PZP Package, 100-Pin HTQFP (Top View) Table 6-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. AGND 79, 83, 87, 89, 92 GND Analog ground – Ground reference and current return for analog circuitry AVDD 82, 84, 88, 95 VDD Analog VDD – Power supply for analog circuitry. Nominally 3.3 V CTL[3:1] 42, 41, 40 DO General-purpose control signals – Used for user-defined control. CTL1 is not powered down via PDO. DE 46 DO Output data enable – Used to indicate time of active video display versus non-active display or blank time. During blank, only HSYNC, VSYNC, and CTL[3:1] are transmitted. During times of active display, or non-blank, only pixel data, QE[23:0], and QO[23:0] are transmitted. High: Active display time Low: Blank time www.ti.com TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TFP401 TFP401A

Table 6-1. Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. DFO 1 DI Output clock data format – Controls the output clock (ODCK) format for either TFT or DSTN panel support. For TFT support, the ODCK clock runs continuously. For DSTN support, ODCK only clocks when DE is high; otherwise, ODCK is held low when DE is low. High: DSTN support/ODCK held low when DE = low Low: TFT support/ODCK runs continuously. DGND 5, 39, 68 GND Digital ground – Ground reference and current return for digital core DVDD 6, 38, 67 VDD Digital VDD – Power supply for digital core. Nominally 3.3 V EXT_RES 96 AI Internal impedance matching – The TFP401/401A is internally optimized for impedance matching at 50 Ω. An external resistor tied to this pin has no effect on device performance. HSYNC 48 DO Horizontal sync output RSVD 99 DI Reserved. Must be tied high for normal operation OVDD 18, 29, 43, 57, 78 VDD Output driver VDD – Power supply for output drivers. Nominally 3.3 V ODCK 44 DO Output data clock – Pixel clock. All pixel outputs QE[23:0] and QO[23:0] (if in 2-pixel/clock mode), along with DE, HSYNC, VSYNC and CTL[3:1], are synchronized to this clock. OGND 19, 28, 45, 58, 76 GND Output driver ground – Ground reference and current return for digital output drivers OCK_INV 100 DI ODCK polarity – Selects ODCK edge on which pixel data (QE[23:0] and QO[23:0]) and control signals (HSYNC, VSYNC, DE, CTL[3:1]) are latched. Normal mode: High: Latches output data on rising ODCK edge Low: Latches output data on falling ODCK edge PD 2 DI Power down – An active-low signal that controls the TFP401/401A power-down state. During power down, all output buffers are switched to a high-impedance state. All analog circuits are powered down and all inputs are disabled, except for PD. If PD is left unconnected, an internal pullup defaults the TFP401/401A to normal operation. High : Normal operation Low: Power down PDO 9 DI Output drive power down – An active-low signal that controls the power-down state of the output drivers. During output drive power down, the output drivers (except SCDT and CTL1) are driven to a high-impedance state. When PDO is left unconnected, an internal pullup defaults the TFP401/401A to normal operation. High: Normal operation/output drivers on Low: Output drive power down PGND 98 GND PLL GND – Ground reference and current return for internal PLL PIXS 4 DI Pixel select – Selects between one- and two-pixels-per-clock output modes. During the 2- pixel/clock mode, both even pixels, QE[23:0], and odd pixels, QO[23:0], are output in tandem on a given clock cycle. During 1-pixel/clock, even and odd pixels are output sequentially, one at a time, with the even pixel first, on the even pixel bus, QE[23:0]. (The first pixel per line is pixel-0, the even pixel. The second pixel per line is pixel-1, the odd pixel). High: 2-pixel/clock Low: 1-pixel/clock PVDD 97 VDD PLL VDD – Power supply for internal PLL QE[8:15] 20–27 DO Even green-pixel output – Output for even and odd green pixels when in 1-pixel/clock mode. Output for even-only green pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QE8/pin 20 MSB: QE15/pin 27 QE[16:23] 30–37 DO Even red-pixel output – Output for even and odd red pixels when in 1-pixel/clock mode. Output for even-only red pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QE16/pin 30 MSB: QE23/pin 37 QO[0:7] 49–56 DO Odd blue-pixel output – Output for odd-only blue pixel when in 2-pixel/clock mode. Not used, and held low, when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QO0/pin 49 MSB: QO7/pin 56 TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 www.ti.com

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Table 6-1. Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. QO[8:15] 59–66 DO Odd green-pixel output – Output for odd-only green pixel when in 2-pixel/clock mode. Not used, and held low, when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QO8/pin 59 MSB: QO15/pin 66 QO[16:23] 69–75, 77 DO Odd red-pixel output – Output for odd-only red pixel when in 2-pixel/clock mode. Not used, and held low, when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QO16/pin 69 MSB: QO23/pin 77 QE[0:7] 10–17 DO Even blue-pixel output – Output for even and odd blue pixels when in 1-pixel/clock mode. Output for even-only blue pixel when in 2-pixel per clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QE0/pin 10 MSB: QE7/pin 17 RxC+ 93 AI Clock positive receiver input – Positive side of reference clock. TMDS low-voltage signal differential input pair RxC– 94 AI Clock negative receiver input – Negative side of reference clock. TMDS low-voltage signal differential input pair Rx0+ 90 AI Channel-0 positive receiver input – Positive side of channel-0. TMDS low-voltage signal differential input pair. Channel-0 receives blue pixel data in active display and HSYNC, VSYNC control signals in blank. Rx0– 91 AI Channel-0 negative receiver input – Negative side of channel-0. TMDS low-voltage signal differential input pair Rx1+ 85 AI Channel-1 positive receiver input – Positive side of channel-1 TMDS low-voltage signal differential input pair Channel-1 receives green-pixel data in active display and CTL1 control signals in blank. Rx1– 86 AI Channel-1 negative receiver input – Negative side of channel-1 TMDS low-voltage signal differential input pair Rx2+ 80 AI Channel-2 positive receiver input – Positive side of channel-2 TMDS low-voltage signal differential input pair Channel-2 receives red-pixel data in active display and CTL2, CTL3 control signals in blank. Rx2– 81 AI Channel-2 negative receiver input – Negative side of channel-2 TMDS low-voltage signal differential input pair SCDT 8 DO Sync detect - Output to signal when the link is active or inactive. The link is considered to be active when DE is actively switching. The TFP401/401A monitors the state of DE to determine link activity. SCDT can be tied externally to PDO to power down the output drivers when the link is inactive. High: Active link Low: Inactive link ST 3 DI Output drive strength select – Selects output drive strength for high- or low-current drive. (See dc specifications for IOH and IOL vs ST state). High: High drive strength Low: Low drive strength STAG 7 DI Staggered pixel select – An active-low signal used in the 2-pixel/clock pixel mode (PIXS = high). Time-staggers the even and odd pixel outputs to reduce ground bounce. Normal operation outputs the odd and even pixels simultaneously. High: Normal simultaneous even/odd pixel output Low: Time-staggered even/odd pixel output VSYNC 47 DO Vertical sync output Thermal Pad — Thermal pad. Recommend soldering the package thermal pad to thermal pad on PCB. Soldering the thermal pad will help to release stress through the solder, otherwise the stress will be absorbed by the peripheral pins. (1) DI = Digital Input; DO = Digital Output; AI = Analog Input; AO = Analog Output www.ti.com TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TFP401 TFP401A

7 Specifications

7.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT DVDD, AVDD, OVDD, PVDD Supply voltage –0.3 4 V VI Input voltage range, logic/analog signals –0.3 4 V Operating ambient temperature 0 70 °C Package power dissipation/PowerPAD package Soldered(2) 4.3 W Not soldered(3) 2.7 JEDEC latchup (EIA/JESD78) 100 mA Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 7.3 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Specified with PowerPAD bond pad on the backside of the package soldered to a 2-oz. (0.071-mm thick) Cu plate PCB thermal plane. Specified at maximum allowed operating temperature, 70°C. (3) PowerPAD bond pad on the backside of the package is not soldered to a thermal plane. Specified at maximum allowed operating temperature, 70°C.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

VDD (DVDD, AVDD, PVDD, OVDD) Supply voltage 3 3.3 3.6 V tpix (1) Pixel time 6.06 40 ns Rt Single-ended analog-input termination resistance 45 50 55 Ω TA Operating free-air temperature 0 25 70 °C (1) tpix is the pixel time defined as the period of the RxC clock input. The period of the output clock, ODCK is equal to tpix when in 1-pixel/clock mode and 2tpix when in 2-pixel/clock mode.

7.4 Thermal Information

THERMAL METRIC(1) TFP401, TFP401A UNITPZP (HTQFP)

100 PINS

RθJA Junction-to-ambient thermal resistance 26 °C/W RθJC(top) Junction-to-case (top) thermal resistance 12.3 RθJB Junction-to-board thermal resistance 7.3 ψJT Junction-to-top characterization parameter 0.3 ψJB Junction-to-board characterization parameter 7.2 RθJC(bot) Junction-to-case (bottom) thermal resistance 1.6 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 www.ti.com

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7.5 DC Digital I/O Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High-level digital input voltage(1) 2 DVDD V VIL Low-level digital input voltage(1) 0 0.8 V IOH High-level output drive current(2) ST = high, VOH = 2.4 V 5 10 14 mA ST = low, VOH = 2.4 V 3 6 9 IOL Low-level output drive current(2) ST = high, VOL = 0.8 V 10 13 19 mA ST = low, VOL = 0.8 V 5 7 11 IOZ Hi-Z output leakage current PD = low or PDO = low –1 1 μA (1) Digital inputs are labeled DI in I/O column of Terminal Functions table. (2) Digital outputs are labeled DO in I/O column of Terminal Functions table.

7.6 DC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VID Analog input differential voltage(1) 75 1200 mV VIC Analog input common-mode voltage(1) AVDD – 300 AVDD – 37 mV VI(OC) Open-circuit analog input voltage AVDD – 10 AVDD + 10 mV IDD(2PIX) Normal 2-pix/clock power supply current (2) ODCK = 82.5 MHz, 2-pix/clock 370 mA IPD Power-down current (3) PD = low 10 mA IPDO Output drive power-down current(3) PDO = low 35 mA (1) Specified as dc characteristic with no overshoot or undershoot. (2) Alternating 2-pixel black/2-pixel white pattern. ST = high, STAG = high, QE[23:0] and QO[23:0] CL = 10 pF. (3) Analog inputs are open circuit (transmitter is disconnected from TFP401/401A).

7.7 AC Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VID(2) Differential input sensitivity(1) 150 1560 mVp-p tps Analog input intra-pair (+ to –) differential skew(8) 0.4 tbit (2) tccs Analog input inter-pair or channel-to-channel skew (8) 1 tpix (3) tijit Worst-case differential input clock jitter tolerance(8) (4) 50 ps tf1 Fall time of data and control signals(5) (6) ST = low, CL = 5 pF 2.4 ns ST = high, CL = 10 pF 1.9 tr1 Rise time of data and control signals(5) (6) ST = low, CL = 5 pF 2.4 ns ST = high, CL = 10 pF 1.9 tr2 Rise time of ODCK clock(5) ST = low, CL = 5 pF 2.4 ns ST = high, CL = 10 pF 1.9 tf2 Fall time of ODCK clock(5) ST = low, CL = 5 pF 2.4 ns ST = high, CL = 10 pF 1.9 tsu1 Setup time, data and control signal to falling edge of ODCK 1 pixel/clock, PIXS = low, OCK_INV = low 1.8 ns2 pixel/clock, PIXS = high, STAG = high, OCK_INV = low 3.8 2 pixel and STAG, PIXS = high, STAG = low, OCK_INV = low 0.7 www.ti.com TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TFP401 TFP401A

7.7 AC Electrical Characteristics (continued)

over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT th1 Hold time, data and control signal to falling edge of ODCK 1 pixel/clock, PIXS = low, OCK_INV = low 0.6 ns2 pixel and STAG, PIXS = high, STAG = low, OCK_INV = low 2.5 2 pixel/clock, PIXS = high, STAG = high, OCK_INV = low 2.9 tsu2 Setup time, data and control signal to rising edge of ODCK 1 pixel/clock, PIXS = low, OCK_INV = high 2.1 ns2 pixel/clock, PIXS = high, STAG = high, OCK_INV = high 4 2 pixel and STAG, PIXS = high, STAG = low, OCK_INV = high 1.5 th2 Hold time, data and control signal to rising edge of ODCK 1 pixel/clock, PIXS = low, OCK_INV = high 0.5 ns2 pixel and STAG, PIXS = high, STAG = low, OCK_INV = high 2.4 2 pixel/clock, PIXS = high, STAG = high, OCK_INV = high 2.1 fODCK ODCK frequency PIX = low (1-PIX/CLK) 25 165 MHz PIX = high (2-PIX/CLK) 12.5 82.5 ODCK duty-cycle 40% 50% 60% tpd(PDL) Propagation delay time from PD low to Hi-Z outputs 9 ns tpd(PDOL) Propagation delay time from PDO low to Hi-Z outputs 9 ns tt(HSC) Transition time between DE transition to SCDT low(7) 1e6 tpix tt(FSC) Transition time between DE transition to SCDT high(7) 1600 tpix td(st) Delay time, ODCK latching edge to QE[23:0] data output STAG = low, PIXS = high 0.25 tpix tWL(PDL_MIN) Minimum time PD is asserted low 9 ns tDEL Minimum DE low 128 Tpixel (1) Specified as ac parameter to include sensitivity to overshoot, undershoot and reflection. (2) tbit is 1/10 the pixel time, tpix. (3) tpix is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to tpix in 1-pixel/clock mode or 2tpix when in 2-pixel/clock mode. (4) Measured differentially at 50% crossing using ODCK output clock as trigger. (5) Rise and fall times measured as time between 20% and 80% of signal amplitude. (6) Data and control signals are QE[23:0], QO[23:0], DE, HSYNC, VSYNC. and CTL[3:1]. (7) Link active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity. (8) By characterization. TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 www.ti.com

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7.8 Typical Characteristics

Figure 7-1. Imax vs Input Frequency www.ti.com TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TFP401 TFP401A

8 Parameter Measurement Information

QE[23:0], QO[23:0], DE, CTK[3:1], HSYNC, VSYNC 20% 80% 80% 20% tr1 tf1 Figure 8-1. Rise and Fall Times of Data and Control Signals 80% 20% 80% 20% tr2 tf2 ODCK Figure 8-2. Rise and Fall Times of ODCK 1/fODCK ODCK Figure 8-3. ODCK Frequency QE[23:0], QO[23:0] DE, CTL[3:1], HSYNC, VSYNC VOH VOL VOH VOL VOH VOL VOH VOL t(su1) t(h1) t(h2) t(su2) VOH VOH VOL VOL ODCK OCK_INV Figure 8-4. Data Setup and Hold Times to Rising and Falling Edges of ODCK 50% VOH td(st) ODCK QE[23:0] Figure 8-5. ODCK High to QE[23:0] Staggered Data Output tps 50% Rx+ Rx– Figure 8-6. Analog Input Intra-Pair Differential Skew ODCK, DE, CTL[3:1], HSYNC, VSYNC, SCDT PD tpd(PDL) VIL Figure 8-7. Delay From PD Low to Hi-Z Outputs ODCK, DE, CTL[3:2], HSYNC, VSYNC PDO tpd(PDOL) VIL Figure 8-8. Delay From PDO Low to Hi-Z Outputs DFO, ST, PIXS, STAG, OCK_INV PD VIH tp(PDH-V) Figure 8-9. Delay From PD Low to High Before Inputs Are Active twL(PDL_MIN) PD VIL Figure 8-10. Minimum Time PD Low TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 www.ti.com

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9 Detailed Description

9.1 Overview

The TFP401/401A is a digital visual interface (DVI)-compliant TMDS digital receiver that is used in digital flat panel display systems to receive and decode TMDS-encoded RGB pixel data streams. In a digital display system a host, usually a PC or workstation, contains a TMDS-compatible transmitter that receives 24-bit pixel data along with appropriate control signals and encodes them into a high-speed low-voltage differential serial bit stream fit for transmission over a twisted-pair cable to a display device. The display device, usually a flat-panel monitor, requires a TMDS-compatible receiver like the TI TFP401/401A to decode the serial bit stream back to the same 24-bit pixel data and control signals that originated at the host. This decoded data can then be applied directly to the flat-panel drive circuitry to produce an image on the display. Because the host and display can be separated by distances up to 5 meters or more, serial transmission of the pixel data is preferred. To support modern display resolutions up to UXGA, a high-bandwidth receiver with good jitter and skew tolerance is required.

9.2 Functional Block Diagram

+ Latch Channel 2 + Latch Channel 1 + Latch Channel 0 + PLL Data Recovery and Synchronization TMDS Decoder CH2(0-9) CH1(0-9) CH0(0-9) Panel Interface RED(0-7) CTL3 CTL2 GRN(0-7) CTL1 BLU(0-7) VSYNC HSYNC QE(0-23) QO(0-23) ODCK DE SCDT CTL3 CTL2 CTL1 VSYNC HSYNC 1.8 V Regulator 3.3 V Internal 50-W Termination 3.3 V 3.3 V Rx2+ Rx2- Rx1+ Rx1- Rx0+ Rx0- RxC+ RxC- Copyright © 2016, Texas Instruments Incorporated

9.3 Feature Description

9.3.1 TMDS Pixel Data and Control Signal Encoding

TMDS stands for transition-minimized differential signaling. Only one of two possible TMDS characters for a given pixel is transmitted at a given time. The transmitter keeps a running count of the number of ones and zeros previously sent, and transmits the character that minimizes the number of transitions to approximate a dc balance of the transmission line. Three TMDS channels are used to receive RGB pixel data during active display time, DE = high. The same three channels also receive control signals, HSYNC, VSYNC, and user-defined control signals CTL[3:1]. These control signals are received during inactive display or blanking-time. Blanking-time is when DE = low. Table 9-1 maps the received input data to the appropriate TMDS input channel in a DVI-compliant system. TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 www.ti.com

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Table 9-1. TMDS Pixel Data and Control Signal Encoding RECEIVED PIXEL DATA ACTIVE DISPLAY DE = HIGH INPUT CHANNEL OUTPUT PINS (VALID FOR DE = HIGH) Red[7:0] Channel-2 (Rx2 ±) QE[23:16] QO[23:16] Green[7:0] Channel-1 (Rx1 ±) QE[15:8] QO[15:8] Blue[7:0] Channel-0 (Rx0 ±) QE[7:0] QO[7:0] RECEIVED CONTROL DATA BLANKING DE = LOW INPUT CHANNEL OUTPUT PINS (VALID FOR DE = LOW) CTL[3:2] Channel-2 (Rx2 ±) CTL[3:2] CTL[1: 0] (1) Channel-1 (Rx1 ±) CTL1 HSYNC, VSYNC Channel-0 (Rx0 ±) HSYNC, VSYNC (1) Some TMDS transmitters transmit a CTL0 signal. The TFP401/401A decodes and transfers CTL[3:1] and ignores CTL0 characters. CTL0 is not available as a TFP401/401A output. The TFP401/401A discriminates between valid pixel TMDS characters and control TMDS characters to determine the state of active display versus blanking (for example, the state of DE).

9.3.2 TFP401/401A Clocking and Data Synchronization

The TFP401/401A receives a clock reference from the DVI transmitter that has a period equal to the pixel time, tpix. The frequency of this clock is also referred to as the pixel rate. Because the TMDS encoded data on Rx[2:0] contains 10 bits per 8-bit pixel, it follows that the Rx[2:0] serial bit rate is 10 times the pixel rate. For example, the required pixel rate to support a UXGA resolution with 60-Hz refresh rate is 165 MHz. The TMDS serial bit rate is 10× the pixel rate, or 1.65 Gb/s. Due to the transmission of this high-speed digital bit stream, on three separate channels (or twisted-pair wires) of long distances (3–5 meters), phase synchronization between the data steams and the input reference clock is not assured. In addition, skew between the three data channels is common. The TFP401/401A uses a 4× oversampling scheme of the input data streams to achieve reliable synchronization with up to 1-t pix channel-to-channel skew tolerance. Accumulated jitter on the clock and data lines due to reflections and external noise sources is also typical of high-speed serial data transmission; hence, the TFP401/401A design for high jitter tolerance. The input clock to the TFP401/401A is conditioned by a phase-locked loop (PLL) to remove high-frequency jitter from the clock. The PLL provides four 10× clock outputs of different phase to locate and sync the TMDS data streams (4× oversampling). During active display, the pixel data is encoded to be transition-minimized, whereas in blank, the control data is encoded to be transition-maximized. A DVI-compliant transmitter is required to transmit in blank for a minimum period of time, 128 t pix, to ensure sufficient time for data synchronization when the receiver sees a transition-maximized code. Synchronization during blank, when the data is transition- maximized, ensures reliable data-bit boundary detection. Phase synchronization to the data streams is unique for each of the three input channels and is maintained as long as the link remains active.

9.3.3 TFP401/401A TMDS Input Levels and Input Impedance Matching

The TMDS inputs to the TFP401/401A receiver have a fixed single-ended termination to AV DD. The TFP401/401A is internally optimized using a laser trim process to precisely fix the impedance at 50 Ω. The device functions normally with or without a resistor on the EXT_RES pin, so it remains drop-in compatible with current sockets. The fixed impedance eliminates the need for an external resistor while providing optimum impedance matching to standard 50-Ω DVI cables. Figure 9-1 shows a conceptual schematic of a DVI transmitter and TFP401/401A receiver connection. A transmitter drives the twisted-pair cable via a current source, usually achieved with an open-drain type output driver. The internal resistor, which is matched to the cable impedance at the TFP401/401A input, provides a pullup to AV DD. Naturally, when the transmitter is disconnected and the TFP401/401A DVI inputs are left unconnected, the TFP401/401A receiver inputs pull up to AV DD. The single-ended differential signal and full- differential signal is shown in Figure 9-2. The TFP401/401A is designed to respond to differential signal swings ranging from 150 mV to 1.56 V with common-mode voltages ranging from (AVDD – 300 mV) to (AVDD – 37 mV). www.ti.com TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TFP401 TFP401A

Figure 9-1. TMDS Differential Input and Transmitter Connection AVCC AVCC – 1/2 VIDIFF 1/2 VIDIFF a) Single-Ended Input Signal +1/2 VIDIFF –1/2 VIDIFF VIDIFF b) Differential Input Signal Figure 9-2. TMDS Inputs

9.3.4 TFP401A Incorporates HSYNC Jitter Immunity

Several DVI transmitters available in the market introduce jitter on the transmitted HSYNC and VSYNC signals during the TMDS encryption process. The HSYNC signal can shift by one pixel position (one clock) from nominal in either direction, resulting in up to two cycles of HSYNC shift. This jitter carries through to the DVI receiver, and if the position of HSYNC shifts continuously, the receiver can lose track of the input timing, causing pixel noise to occur on the display. For this reason, a DVI-compliant receiver with HSYNC jitter immunity should be used in all displays that could be connected to host PCs with transmitters that have this HSYNC jitter problem. The TFP401A integrates HSYNC regeneration circuitry that provides a seamless interface to these noncompliant transmitters. The position of the data enable (DE) signal is always fixed in relation to data, irrespective of the location of HSYNC. The TFP401A receiver uses the DE and clock signals to recreate stable vertical and horizontal sync signals. The circuit filters the HSYNC output of the receiver, and HSYNC is shifted to the nearest eighth bit boundary, producing a stable output with respect to data, as shown in Figure 9-3 . This ensures accurate data synchronization at the input of the display timing controller. This HSYNC regeneration circuit is transparent to the monitor and need not be removed even if the transmitted HSYNC is stable. For example, the PanelBus line of DVI 1.0 compliant transmitters, such as the TFP6422 and TFP420, do not have the HSYNC jitter problem. The TFP401A operates correctly with either compliant or noncompliant transmitters. In contrast, the TFP401 is ideal for customers who have control over the transmit portion of the design, such as bundled system manufacturers and for internal monitor use (the DVI connection between monitor and panel modules). TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 www.ti.com

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HSYNC Shift by ± 1 Clock ODCK HSYNC IN DE HSYNC OUT Figure 9-3. HSYNC Regeneration Timing Diagram

9.4 Device Functional Modes

9.4.1 TFP401/401A Modes of Operation

The TFP401/401A provides system design flexibility and value by providing the system designer with configurable options or modes of operation to support varying system architectures. Table 9-2 outlines the various panel modes that can be supported, along with appropriate external control pin settings. Table 9-2. TFP401/401A Modes of Operation PANEL PIXEL RATE ODCK LATCH EDGE ODCK DFO PIXS OCK_INV TFT or 16-bit DSTN 1 pix/clock Falling Free run 0 0 0 TFT or 16-bit DSTN 1 pix/clock Rising Free run 0 0 1 TFT 2 pix/clock Falling Free run 0 1 0 TFT 2 pix/clock Rising Free run 0 1 1 24-bit DSTN 1 pix/clock Falling Gated low 1 0 0 NONE 1 pix/clock Rising Gated low 1 0 1 24-bit DSTN 2 pix/clock Falling Gated low 1 1 0 24-bit DSTN 2 pix/clock Rising Gated low 1 1 1

9.4.2 TFP401/401A Output Driver Configurations

The TFP401/401A provides flexibility by offering various output driver features that can be used to optimize power consumption, ground bounce, and power-supply noise. The following sections outline the output driver features and their effects.

9.4.2.1 Output Driver Power Down

(PDO = low); pulling PDO low places all the output drivers, except CTL1 and SCDT, into a high-impedance state. The SCDT output, which indicates link-disabled or link-inactive, can be tied directly to the PDO input to disable the output drivers when the link is inactive or when the cable is disconnected. An internal pullup on the PDO pin defaults the TFP401/401A to the normal nonpower-down output drive mode if left unconnected.

9.4.2.2 Drive Strength

(ST = high for high drive strength, ST = low for low drive strength). The TFP401/401A allows for selectable output drive strength on the data, control, and ODCK outputs. See the DC Electrical Characteristics table for the values of IOH and IOL current drives for a given ST state. The high output drive strength offers approximately two times the drive as the low-output drive strength. www.ti.com TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TFP401 TFP401A

9.4.2.3 Time-Staggered Pixel Output

This option works only in conjunction with the 2-pixel/clock mode (PIXS = high). Setting STAG = low time- staggers the even- and odd-pixel outputs so as to reduce the amount of instantaneous current surge from the power supply. Depending on the PCB layout and design, this can help reduce the amount of system ground bounce and power-supply noise. The time stagger is such that in 2-pixel/clock mode, the even pixel is delayed from the latching edge of ODCK by 0.25 t cip. (tcip is the period of ODCK. The ODCK period is 2 t pix when in 2-pixel/clock mode). Depending on system constraints of output load, pixel rate, panel input architecture, and board cost, the TFP401/401A drive-strength and staggered-pixel options allow flexibility to reduce system power-supply noise, ground bounce, and EMI.

9.4.2.4 Power Management

The TFP401/401A offers several system power-management features. The output driver power down (PDO = low) is an intermediate mode which offers several uses. During this mode, all output drivers except SCDT and CTL1 are driven to a high-impedance state while the rest of the device circuitry remains active. The TFP401/401A power down (PD = low) is a complete power down in that it powers down the digital core, the analog circuitry, and output drivers. All output drivers are placed into a Hi-Z state. All inputs are disabled except for the PD input. The TFP401/401A does not respond to any digital or analog inputs until PD is pulled high. Both PDO and PD have internal pullups, so if left unconnected they default the TFP401/401A to normal operating modes.

9.4.2.5 Sync Detect

The TFP401/401A offers an output, SCDT, to indicate link activity. The TFP401/401A monitors activity on DE to determine if the link is active. When 1 million (1e6) pixel clock periods pass without a transition on DE, the TFP401/401A considers the link inactive, and SCDT is driven low. While SCDT is low, if two DE transitions are detected within 1600 pixel clock periods, the link is considered active, and SCDT is pulled high. SCDT can be used to signal a system power management circuit to initiate a system power down when the link is considered inactive. The SCDT can also be tied directly to the TFP401/401A PDO input to power down the output drivers when the link is inactive. It is not recommended to use SCDT to drive the PD input, because once in complete power-down, the analog inputs are ignored and the SCDT state does not change. An external system power-management circuit to drive PD is preferred. TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 www.ti.com

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10 Applications and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

10.1 Application Information

The TFP401 is a DVI (Digital Visual Interface) compliant digital receiver that is used in digital flat panel display systems to receive and decode TMDS encoded RGB pixel data streams. A digital display system a host, usually a PC or workstation, contains a DVI compliant transmitter that receives 24-bit pixel data along with appropriate control signals and encodes them into a high-speed low voltage differential serial bit stream fit for transmission over a twisted-pair cable to a display device. The display device, usually a flat-panel monitor, will require a DVI compliant receiver like the TI TFP401 to decode the serial bit stream back to the same 24-bit pixel data and control signals that originated at the host. This decoded data can then be applied directly to the flat panel drive circuitry to produce an image on the display. Since the host and display can be separated by distances up to 5 meters or more, serial transmission of the pixel data is preferred. The TFP401 will support resolutions up to UXGA.

10.2 Typical Application

Figure 10-1. Typical Application

10.2.1 Design Requirements

For this design example, use the parameters listed in Table 10-1 as the input parameters. Table 10-1. Design Parameters PARAMETER VALUE Power supply 3.3 V-DC at 1 A Input clock Single-ended Input clock frequency range 25 MHz – 165 MHz Output format 24 bits/pixel Input clock latching Rising edge I2C EEPROM support No De-skew No www.ti.com TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TFP401 TFP401A

10.2.2 Detailed Design Procedure

10.2.2.1 Data and Control Signals

The trace length of data and control signals out of the receiver should be kept as close to equal as possible. Trace separation should be ≈5X Height. As a general rule, traces also should be less than 2.8 inches if possible (longer traces can be acceptable). Delay = 85 × SQRT ER (1) where

• ER = 4.35
• Relative permittivity of 50% resin FR-4 at 1 GHz
• Delay = 177 pS/inch Length of rising edge = TR (picoseconds) ÷ Delay (2) where
• TR = 3 nS
• = 3000 ps ÷ 177 ps per inch
• = 16.9 inches Length of rising edge ÷ 6 = Maximum length of trace for lumped circuit (3) where
• 16.9 ÷ 6 = 2.8 inches Figure 10-2. Data and Control Signals Design TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 www.ti.com

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10.2.2.2 Configuration Options

The TFP401 can be configured in several modes depending on the required output format, for example 1-byte/ clock, 2-bytes/clock, falling/rising clock edge. You can leave place holders for future configuration changes. Figure 10-3. Configuration Options Design

10.2.2.3 Power Supplies Decoupling

Digital, analog, and PLL supplies must be decoupled from each other to avoid electrical noise on the PLL and the core. Figure 10-4. Power Supplies Decoupling Design www.ti.com TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TFP401 TFP401A

10.2.3 Application Curve

Sometimes the panel does not support the same format as the graphics processor unit (GPU). In these cases the user must decide how to connect the unused bits. Figure 10-5 and Figure 10-6 plots show the mismatches between the 18-bit GPU and a 24-bit LCD where “x” and “y” represent the 2 LSB of the panel. Figure 10-5. 16-bit GPU to 24-bit LCD Figure 10-6. 18-bit GPU to 24-bit LCD

11 Power Supply Recommendations

Use solid ground planes and tie ground planes together with as many vias as is practical. This will provide a desirable return path for current. Each supply should be on separate split power planes, where each power plane should be as large an area as possible. Connect PanelBus receiver power and ground pins and all bypass caps to appropriate power or ground plane with via. Vias should be as fat and short as practical, the goal is to minimize the inductance.

• DVDD: Place one 0.01 µF capacitor as close as possible between each DVDD device pin (Pins 6, 38, and 67) and ground. A 22 µF tantalum capacitor should be placed between the supply and 0.01 µF capacitors. A ferrite bead should be used between the source and the 22 µF capacitor.
• OVDD: Place one 0.01 µF capacitor as close as possible between each OVDD device pin (Pins 18, 29, 43, 57, and 78) and ground. A 22 µF tantalum capacitor should be placed between the supply and 0.01 µF capacitors. A ferrite bead should be used between the source and the 22 µF capacitor.
• AVDD: Place one 0.01 µF capacitor as close as possible between each AVDD device pin (Pins 82, 84, 88, and 95) and ground. A 22 µF tantalum capacitor should be placed between the supply and 0.01 µF capacitors. A ferrite bead should be used between the source and the 22 µF capacitor.
• PVCC: Place three 0.01 µF capacitors in parallel as close as possible between the PVDD device pin (Pin 97) and ground. A 22 µF tantalum capacitor should be placed between the supply and 0.01 µF capacitors. A ferrite bead should be used between the source and the 22 µF capacitor. TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 www.ti.com

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12 Layout

12.1 Layout Guidelines

12.1.1 Layer Stack

The pinout of Texas Instruments' High Speed Interface (HSI) devices features differential signal pairs and the remaining signals comprise the supply rails, V CC and ground, and lower speed signals such as control pins. As an example, consider a device X which is a repeater/re-driver, so both its inputs and outputs are high-speed differential signals. These guidelines can be applied to other high-speed devices such as drivers, receivers, multiplexers, and so forth. A minimum of four layers is required to accomplish a low EMI PCB design. Layer stacking should be in the following order (top-to-bottom): high-speed differential signal layer, ground plane, power plane and control signal layer. Figure 12-1. Layer Stack

12.1.2 Routing High-Speed Differential Signal Traces (RxC–, RxC+, Rx0–, Rx0+, Rx1–, Rx1+, Rx2–, Rx2+)

Trace impedance should be controlled for optimal performance. Each differential pair should be equal in length and symmetrical and should have equal impedance to ground with a trace separation of 2X to 4X Height. A differential trace separation of 4X Height yields about 6% cross-talk (6% effect on impedance). It is recommended that differential trace routing should be side by side, though it is not important that the differential traces be tightly coupled together because tight coupling is not achievable on PCB traces. Typical ratios on PCBs are only 20-50%, and 99.9% is the value of a well-balanced twisted pair cable. Each differential trace should be as short as possible (<2" preferably) with no 90" angles. These high-speed transmission traces should be on Layer 1 (top layer). RxC–, RxC+, Rx0–, Rx0+, Rx1–, Rx1+, Rx2–, Rx2+ signals all route directly from the DVI connector pins to the device, no external components are needed.

12.1.3 DVI Connector

Clear-out holes for connector pins should leave space between pins to allow continuous ground through the pin field. Allow enough spacing in ground plane around signal pins vias however, keep enough copper between vias to allow for ground current to flow between the vias. Avoid creating a large ground plane slot around the entire connector, minimizing the via capacitance is the goal. www.ti.com TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TFP401 TFP401A

12.2 Layout Example

DVI connector trace matching: Figure 12-2. DVI Connector Routing TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 www.ti.com

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Keep data lines as far as possible from each other. Figure 12-3. Data Lines Routing www.ti.com TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TFP401 TFP401A

Connect the thermal pad to ground. Figure 12-4. Ground Routing

12.3 TI PowerPAD 100-TQFP Package

The TFP401/401A is packaged in TI's thermally enhanced PowerPAD 100-TQFP packaging. The PowerPAD package is a 14-mm × 14-mm × 1-mm TQFP outline with 0.5-mm lead pitch. The PowerPAD package has a specially designed die mount pad that offers improved thermal capability over typical TQFP packages of the same outline. The TI 100-TQFP PowerPAD package offers a back-side solder plane that connects directly to the die mount pad for enhanced thermal conduction. Soldering the back side of the TFP401/401A to the application board is not required thermally, because the device power dissipation is well within the package capability when not soldered. However, to minimize stress on peripheral pins, it is highly recommended to solder the thermal pad to PCB. Soldering the back side of the device to the PCB ground plane is recommended for electrical considerations. Because the die pad is electrically connected to the chip substrate and hence to chip ground, connection of the PowerPAD's back side to a PCB ground plane helps to improve EMI, ground bounce, and power-supply noise performance. To minimize stress on peripheral pins, however, it is highly recommended to solder the thermal pad to PCB. TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 www.ti.com

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Table 12-1 outlines the thermal properties of the TI 100-TQFP PowerPAD package. The 100-TQFP non- PowerPAD package is included only for reference. Table 12-1. TI 100-TQFP (14 mm × 14 mm × 1 mm) / 0.5-mm Lead Pitch PARAMETER WITHOUT PowerPAD™ Package PowerPAD™ Package, NOT CONNECTED TO PCB THERMAL PLANE PowerPAD™ Package, CONNECTED TO PCB THERMAL PLANE(1) Theta-JA(1) (2) 45°C/W 27.3°C/W 17.3°C/W Theta-JC(1) (2) 3.11°C/W 0.12°C/W 0.12°C/W Maximum power dissipation(1) (2) (3) 1.6 W 2.7 W 4.3 W (1) Specified with 2-oz. (0.071 mm thick) Cu PCB plating (2) Airflow is at 0 LFM (0 m/s) (no airflow) (3) Measured at ambient temperature, TA = 70°C www.ti.com TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TFP401 TFP401A

13 Device and Documentation Support

13.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

13.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

13.3 Trademarks

PanelBus™ and PowerPAD™ are trademarks of Texas Instruments. HDMI™ is a trademark of HDMI Licensing Administrator, Inc. TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

13.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

13.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TFP401, TFP401A SLDS120H – MARCH 2000 – REVISED MARCH 2022 www.ti.com

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www.ti.com 9-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TFP401APZP Active Production HTQFP (PZP) | 100 90 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR 0 to 70 TFP401APZP TFP401APZP.A Active Production HTQFP (PZP) | 100 90 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR 0 to 70 TFP401APZP TFP401APZPG4 Active Production HTQFP (PZP) | 100 90 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR 0 to 70 TFP401APZP TFP401APZPR Active Production HTQFP (PZP) | 100 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR 0 to 70 TFP401APZP TFP401APZPR.A Active Production HTQFP (PZP) | 100 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR 0 to 70 TFP401APZP TFP401PZP Active Production HTQFP (PZP) | 100 90 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR 0 to 70 TFP401PZP TFP401PZP.A Active Production HTQFP (PZP) | 100 90 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR 0 to 70 TFP401PZP TFP401PZPG4 Active Production HTQFP (PZP) | 100 90 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR 0 to 70 TFP401PZP TFP401PZPG4.A Active Production HTQFP (PZP) | 100 90 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR 0 to 70 TFP401PZP (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Addendum-Page 1

www.ti.com 9-Nov-2025 Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TFP401A :

• Automotive : TFP401A-Q1
• Enhanced Product : TFP401A-EP NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TFP401APZPR HTQFP PZP 100 1000 350.0 350.0 43.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. TQFP - 1.2 mm max height TM PowerPAD PZP 100 PLASTIC QUAD FLATPACK14 x 14 mm Pkg Body, 0.5 mm pitch 16 x 16 mm Pkg Area 4224739/B

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