TBB1002 HITACHI
Document overview
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Technical content
Features
- Small SMD package CMPAK-6 built in twin BBFET; To reduce using parts cost & PC board space.
- Suitable for World Standard Tuner RF amplifier.
- Very useful for total tuner cost reduction.
- Withstanding to ESD; Build in ESD absorbing diode. Withstand up to 200 V at C = 200 pF, Rs = 0 conditions.
- Provide mini mold packages; CMPAK-6 Outline CMPAK-6 1. Gate-1(1) 2. Source 3. Drain(1) 4. Drain(2) 5. Gate-2 6. Gate-1(2) Notes: 1. Marking is “BM”. 2. TBB1002 is individual type number of HITACHI TWIN BBFET.
Absolute Maximum Ratings (Ta = 25°C) Item Symbol Ratings Unit Drain to source voltage V DS 6V Gate1 to source voltage V G1S +6 V Gate2 to source voltage V G2S +6 V Drain current I D 30 mA Channel power dissipation Pch *3 250 mW Channel temperature Tch 150 °C Storage temperature Tstg –55 to +150 °C Notes: 3. Value on the glass epoxy board (49mm · 38mm · 1mm). Electrical Characteristics (Ta = 25°C) The below specification are applicable for UHF unit (FET1) Item Symbol Min Typ Max Unit Test Conditions Drain to source breakdown voltage V(BR)DSS 6 ——V I D = 200mA, VG1S = VG2S = 0 Gate1 to source breakdown voltage V(BR)G1SS + 6 ——V I G1 = +10mA, VG2S = VDS = 0 Gate2 to source breakdown voltage V(BR)G2SS + 6 ——V I G2 = +10mA, VG1S = VDS = 0 Gate1 to source cutoff current IG1SS — — +100 nA V G1S = +5V, VG2S = VDS = 0 Gate2 to source cutoff current IG2SS — — +100 nA V G2S = +5V, VG1S = VDS = 0 Gate1 to source cutoff voltage VG1S(off) 0.5 0.75 1.0 V V DS = 5V, VG2S = 4V, ID = 100mA Gate2 to source cutoff voltage VG2S(off) 0.5 0.75 1.0 V V DS = 5V, VG1S = 5V, ID = 100mA Drain current I D(op) 13 17 21 mA V DS = 5V, VG1 = 5V VG2S = 4V, RG = 100kW Forward transfer admittance |yfs| 2 12 63 1m S V DS = 5V, VG1 = 5V, VG2S =4V R G = 100kW , f = 1kHz Input capacitance c iss 1.4 1.8 2.2 pF V DS = 5V, VG1 = 5V Output capacitance c oss 1.0 1.4 1.8 pF V G2S =4V, RG = 100kW Reverse transfer capacitance crss — 0.02 0.04 pF f = 1MHz Power gain PG 16 21 — dB V DS = VG1 = 5V, VG2S = 4V R G = 100kW , f = 900MHz Zi=S11*, Zo=S22*(:PG) Noise figure NF — 1.7 2.5 dB Zi=S11opt (:NF)
Electrical Characteristics (Ta = 25°C) The below specification are applicable for VHF unit (FET2) Item Symbol Min Typ Max Unit Test Conditions Drain to source breakdown voltage V(BR)DSS 6 ——V I D = 200mA, VG1S = VG2S = 0 Gate1 to source breakdown voltage V(BR)G1SS + 6 ——V I G1 = +10mA, VG2S = VDS = 0 Gate2 to source breakdown voltage V(BR)G2SS + 6 ——V I G2 = +10mA, VG1S = VDS = 0 Gate1 to source cutoff current IG1SS — — +100 nA V G1S = +5V, VG2S = VDS = 0 Gate2 to source cutoff current IG2SS — — +100 nA V G2S = +5V, VG1S = VDS = 0 Gate1 to source cutoff voltage VG1S(off) 0.5 0.75 1.0 V V DS = 5V, VG2S = 4V, ID = 100mA Gate2 to source cutoff voltage VG2S(off) 0.5 0.75 1.0 V V DS = 5V, VG1S = 5V, ID = 100mA Drain current I D(op) 14 18 22 mA V DS = 5V, VG1 = 5V, VG2S = 4V, R G = 82kW Forward transfer admittance |yfs| 2 02 53 0m S V DS = 5V, VG1 = 5V, VG2S =4V, R G = 82kW , f = 1kHz Input capacitance c iss 2.2 2.6 3.0 pF V DS = 5V, VG1 = 5V Output capacitance c oss 1.2 1.6 2.0 pF V G2S =4V, RG = 82kW Reverse transfer capacitance crss — 0.03 0.05 pF f = 1MHz Power gain PG 22 27 — dB V DS = VG1 = 5V, VG2S = 4V Noise figure NF — 1.2 1.7 dB R G = 82kW , f = 200MHz
- DC Biasing Circuit for Operating Characteristic Items (ID(op), |yfs|, Ciss, Coss, Crss, NF, PG) Measurment of FET1 Gate 1 Source Gate 2 R G Drain A ID VG2 VG1 VD OpenOpen Measurment of FET2 Gate 1 Source Gate 2 Drain VG2 R G VG1 A ID VD OpenOpen
- Equivalent Circuit BBFET-(1) BBFET-(2) No.1 No.2 No.3 No.6 No.5 No.4 Gate-1(1) Source Drain(1) Gate-1(2) Gate-2 Drain(2)
- 200 MHz Power Gain, Noise Figure Test Circuit V G2 Input(50Ω ) 1000p 36p 1000p V = V D G1 R G TWINBBFET RFC Output(50Ω )L2 1000p 10p max 1000p 1000p 47k 1SV70 1000p 1000p 1000p 47k 47k 82k V TV T Unit : Resistance (Ω ) Capacitance (F) 1SV70 L1 : φ1mm Enameled Copper Wire,Inside dia 10mm, 2Turns L2 : φ1mm Enameled Copper Wire,Inside dia 10mm, 2Turns RFC : φ1mm Enameled Copper Wire,Inside dia 5mm, 2Turns
V = 4 V V = V G2S G1 DS 0 12345 0 12345 V = 5 V R = 120 kΩ DS G V = 5 VDS Channel Power Dissipation Pch* (mW) Ambient Temperature Ta (°C) Maximum Channel Power Dissipation Curve Drain Current I (mA)D Typical Output Characteristics (FET1) Drain to Source Voltage V (V)DS Drain Current vs. Gate1 Voltage (FET1) Gate1 Voltage V (V)G1 Drain Current I (mA)D R = 68 kG Ω 82 k Ω 100 k Ω 2 V V = 1 VG2S 4 V 3 V * Value on the glass epoxy board (49mm × 38mm × 1mm) 120 k Ω 150 k Ω 180 k Ω Gate1 Voltage V (V)G1 Forward Transfer Admittance vs. Gate1 Voltage (FET1) fsForward Transfer Admittance |y | (mS) V = 4 VG2S 150 k Ω R = 68 kG Ω100 k Ω
Gate2 to Source Voltage V (V)G2S Input Capacitance Ciss (pF) Input Capacitance vs. Gate2 to Source Voltage (FET1) 0 12345 V = 4 V V = V G2S G1 DS Drain Current I (mA)D Typical Output Characteristics (FET2) Drain to Source Voltage V (V)DS R = 56 kG Ω 68 k Ω 100 k Ω 120 k Ω 150 k Ω 82 k Ω 0 12345 V = 5 V R = 82 kΩ DS G Drain Current vs. Gate1 Voltage (FET2) Gate1 Voltage V (V)G1 Drain Current I (mA)D 2 V V = 1 VG2S 4 V 3 V 10 20 50 100 200 500 1000 V = 5 V V = 5 V V = 4 V DS G2S Drain Current vs. Gate Resistance (FET1) Drain Current I (mA)D Gate Resistance R (kΩ )G V = 5 V V = 5 V R = 100 kΩ f = 1 MHz DS G
V = 5 VDS Gate1 Voltage V (V)G1 Forward Transfer Admittance vs. Gate1 Voltage (FET2) fsForward Transfer Admittance |y | (mS) V = 4 VG2S 120 k Ω R = 56 kG Ω 82 k Ω 0 1 2 34 Gate2 to Source Voltage V (V) G2S Input Capacitance Ciss (pF) Input Capacitance vs. Gate2 to Source Voltage (FET2) 10 20 50 100 200 500 1000 V = 5 V V = 5 V V = 4 V DS G2S Drain Current vs. Gate Resistance (FET2) Drain Current I (mA)D Gate Resistance R (kΩ )G 10 20 50 100 200 500 1000 V = 5 V V = 5 V V = 4 V f = 200 MHz DS G2S Power Gain vs. Gate Resistance (FET2) Gate Resistance R (kΩ )G Power Gain PG (dB) V = 5 V V = 5 V R = 82 kΩ f = 1 MHz DS G
V = 5 V V = 5 V V = 4 V f = 200 MHz DS G2S Noise Figure vs. Gate Resistance (FET2) Noise Figure NF (dB) Gate Resistance R (kΩ )G 3 2 10 DS G V = V = 5 V R = 82 kΩ Gain Reduction GR (dB) Gain Reduction vs. Gate2 to Source Voltage (FET2) Gate2 to Source Voltage V (V)G2S
2.1 – 0.3 6-0.2 0.9 – 0.1 (0.2) 2.0 – 0.2 (0.65) (0.65) 1.3 – 0.2 (0.425)(0.425) Hitachi Code JEDEC EIAJ Mass (reference value) CMPAK-6 Conforms 0.006 g 0.15 0 to 0.1 + 0.1 – 0.05 + 0.1 – 0.05 1.25 – 0.1 As of January, 2001 Unit: mm
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