TBB1002

TBB1002_06 RENESAS

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 10

Technical content

Features

• Small SMD package CMPAK-6 built in twin BBFET; To reduce using parts cost & PC board space.
• Suitable for World Standard Tuner RF amplifier.
• Very useful for total tuner cost reduction.
• Withstanding to ESD; Built in ESD absorbing diode. Withstand up to 200 V at C = 200 pF, Rs = 0 conditions.
• Provide mini mold packages; CMPAK-6 Outline (Package name: CMPAK-6) 1. Gate-1(1) 2. Source 3. Drain(1) 4. Drain(2) 5. Gate-2 6. Gate-1(2) Notes: 1. Marking is “BM”. 2. TBB1002 is individual type number of RENESAS TWIN BBFET.

Rev.9.00 Aug 22, 2006 page 2 of 9 Absolute Maximum Ratings (Ta = 25°C) Item Symbol Ratings Unit Drain to source voltage V DS 6 V Gate1 to source voltage V G1S +6 V Gate2 to source voltage V G2S +6 V Drain current I D 30 mA Channel power dissipation Pch *3 250 mW Channel temperature Tch 150 °C Storage temperature Tstg –55 to +150 °C Notes: 3. Value on the glass epoxy board (49mm × 38mm × 1mm).

Electrical Characteristics

(Ta = 25°C) The below specification are applicable for UHF unit (FET1) Item Symbol Min Typ Max Unit Test conditions Drain to source breakdown voltage V (BR)DSS 6 — — V I D = 200 µA, VG1S = VG2S = 0 Gate1 to source breakdown voltage V (BR)G1SS +6 — — V I G1 = +10 µA, VG2S = VDS = 0 Gate2 to source breakdown voltage V (BR)G2SS +6 — — V I G2 = +10 µA, VG1S = VDS = 0 Gate1 to source cutoff current I G1SS — — +100 nA V G1S = +5 V, VG2S = VDS = 0 Gate2 to source cutoff current I G2SS — — +100 nA V G2S = +5 V, VG1S = VDS = 0 Gate1 to source cutoff voltage V G1S(off) 0.5 0.75 1.0 V VDS = 5 V, VG2S = 4 V ID = 100 µA Gate2 to source cutoff voltage V G2S(off) 0.5 0.75 1.0 V VDS = 5 V, VG1S = 5 V ID = 100 µA Drain current I D(op) 13 17 21 mA VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 100 kΩ Forward transfer admittance |y fs| 21 26 31 mS VDS = 5 V, VG1 = 5 V, VG2S = 4 V RG = 100 kΩ , f = 1 kHz Input capacitance Ci ss 1.4 1.8 2.2 pF Output capacitance Co ss 1.0 1.4 1.8 pF Reverse transfer capacitance Crss — 0.02 0.04 pF VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 100 kΩ f = 1 MHz Power gain PG 16 21 — dB Noise figure NF — 1.7 2.5 dB VDS = VG1 = 5 V, VG2S = 4 V RG = 100 kΩ , f = 900 MHz Zi =S11*, Zo=S22*(:PG) Zi =S11opt (:NF)

Rev.9.00 Aug 22, 2006 page 3 of 9 Electrical Characteristics (cont.) (Ta = 25°C) The below specification are applicable for VHF unit (FET2) Item Symbol Min Typ Max Unit Test conditions Drain to source breakdown voltage V (BR)DSS 6 — — V I D = 200 µA, VG1S = VG2S = 0 Gate1 to source breakdown voltage V (BR)G1SS +6 — — V I G1 = +10 µA, VG2S = VDS = 0 Gate2 to source breakdown voltage V (BR)G2SS +6 — — V I G2 = +10 µA, VG1S = VDS = 0 Gate1 to source cutoff current I G1SS — — +100 nA V G1S = +5 V, VG2S = VDS = 0 Gate2 to source cutoff current I G2SS — — +100 nA V G2S = +5 V, VG1S = VDS = 0 Gate1 to source cutoff voltage V G1S(off) 0.5 0.75 1.0 V VDS = 5 V, VG2S = 4 V ID = 100 µA Gate2 to source cutoff voltage V G2S(off) 0.5 0.75 1.0 V VDS = 5 V, VG1S = 5 V ID = 100 µA Drain current I D(op) 14 18 22 mA VDS = 5V, VG1 = 5 V, VG2S = 4 V RG = 82 kΩ Forward transfer admittance |y fs| 20 25 30 mS VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 82 kΩ f = 1 kHz Input capacitance Ci ss 2.2 2.6 3.0 pF Output capacitance Co ss 1.2 1.6 2.0 pF Reverse transfer capacitance Crss — 0.03 0.05 pF VDS = 5 V, VG1 = 5 V VG2S =4 V, RG = 82 kΩ f = 1 MHz Power gain PG 22 27 — dB Noise figure NF — 1.2 1.7 dB VDS = VG1 = 5 V, VG2S = 4 V RG = 82 kΩ , f = 200 MHz

Rev.9.00 Aug 22, 2006 page 4 of 9 Test Circuits

• DC Biasing Circuit for Operating Characteristic Items (ID(op), |yfs|, Ciss, Coss, Crss, NF, PG) Measurment of FET1 Gate 1 Source Gate 2 RG Drain A ID VG2 VG1 VD OpenOpen Measurment of FET2 Gate 1 Source Gate 2 Drain VG2 RG VG1 A ID VD OpenOpen

Rev.9.00 Aug 22, 2006 page 5 of 9

• Equivalent Circuit BBFET-(1) BBFET-(2) No.1 No.2 No.3 No.6 No.5 No.4 Gate-1(1) Source Drain(1) Gate-1(2) Gate-2 Drain(2)
• 200 MHz Power Gain, Noise Figure Test Circuit V G2 Input(50Ω) 1000p 36p 1000p V = V D G1 R G TWINBBFET RFC Output(50Ω)L2 1000p 10p max 1000p 1000p 47k 1SV70 1000p 1000p 1000p 47k 47k 82k V TV T Unit : Resistance (Ω) Capacitance (F) 1SV70 L1 : φ1mm Enameled Copper Wire,Inside dia 10mm, 2Turns L2 : φ1mm Enameled Copper Wire,Inside dia 10mm, 2Turns RFC : φ1mm Enameled Copper Wire,Inside dia 5mm, 2Turns

Rev.9.00 Aug 22, 2006 page 6 of 9 Forward Transfer Admittance |yfs| (mS) 400 300 200 100 0 50 100 150 200 0 1234 VG2S = 4 V VG1 = VDS 0 1234 0 12345 VDS = 5 V RG = 120 kΩ VG2S = 5 V Channel Power Dissipation Pch* (mW) Ambient Temperature Ta (°C) Maximum Channel Power Dissipation Curve Drain Current ID (mA) Typical Output Characteristics (FET1) Drain to Source Voltage VDS (V) Drain Current vs. Gate1 Voltage (FET1) Gate1 Voltage VG1 (V) Drain Current ID (mA) RG = 68 kΩ 82 k Ω 100 k Ω 2 V VG2S = 1 V 4 V 3 V * Value on the glass epoxy board (49mm × 38mm × 1mm) 120 k Ω 150 k Ω 180 k Ω Gate1 Voltage VG1 (V) Forward Transfer Admittance vs. Gate1 Voltage (FET1) VDS = 4 V 150 k Ω RG = 68 kΩ100 k Ω 0 1 2 3 4 Gate2 to Source Voltage VG2S (V) Input Capacitance Ciss (pF) Input Capacitance vs. Gate2 to Source Voltage (FET1) 10 20 50 100 200 500 1000 VDS = 5 V VG1 = 5 V VG2S = 4 V Drain Current vs. Gate Resistance (FET1) Drain Current ID (mA) Gate Resistance RG (kΩ) VDS = 5 V VG1 = 5 V RG = 100 kΩ f = 1 MHz

Rev.9.00 Aug 22, 2006 page 7 of 9 0 12345 VG2S = 4 V VG1 = VDS Drain Current ID (mA) Typical Output Characteristics (FET2) Drain to Source Voltage VDS (V) RG 56 k Ω 68 k Ω 100 k Ω 120 k Ω 150 k Ω 82 k Ω 0 12345 VDS = 5 V RG = 82 kΩ Drain Current vs. Gate1 Voltage (FET2) Gate1 Voltage VG1 (V) Drain Current ID (mA) 2 V VG2S = 1 V 4 V 3 V Forward Transfer Admittance |yfs| (mS) 0 12345 VDS = 5 V Gate1 Voltage VG1 (V) Forward Transfer Admittance vs. Gate1 Voltage (FET2) VG2S = 4 V 120 k Ω RG = 56 kΩ 82 k Ω 0 1 2 3 4 Gate2 to Source Voltage VG2S (V) Input Capacitance Ciss (pF) Input Capacitance vs. Gate2 to Source Voltage (FET2) 10 20 50 100 200 500 1000 VDS = 5 V VG1 = 5 V VG2S = 4 V Drain Current vs. Gate Resistance (FET2) Drain Current ID (mA) Gate Resistance RG (kΩ) 10 20 50 100 200 500 1000 VDS = 5 V VG1 = 5 V VG2S = 4 V f = 200 MHz Power Gain vs. Gate Resistance (FET2) Gate Resistance RG (kΩ) Power Gain PG (dB) VDS = 5 V VG1 = 5 V RG = 82 kΩ f = 1 MHz

Rev.9.00 Aug 22, 2006 page 8 of 9 10 20 50 100 200 500 1000 VDS = 5 V VG1 = 5 V VG2S = 4 V f = 200 MHz Noise Figure vs. Gate Resistance (FET2) Noise Figure NF (dB) Gate Resistance RG (kΩ) 3 2 1 VDS = VG1 = 5 V RG = 82 kΩ Gain Reduction GR (dB) Gain Reduction vs. Gate2 to Source Voltage (FET2) Gate2 to Source Voltage VG2S (V)

Rev.9.00 Aug 22, 2006 page 9 of 9 Package Dimensions Sy e A EH E L Q c D b AA Pattern of terminal position areas e LP S AA2 A b c D E e HE L LP x y Q 0.8 0.8 0.15 0.1 1.8 1.15 2.0 0.3 0.2 0.22 0.25 0.9 0.13 0.11 2.0 1.25 0.65 2.1 1.5 0.25 1.1 0.1 1.0 0.3 0.2 0.15 2.2 1.35 2.2 0.7 L1 0.1 0.5 0.6 0.05 0.05 0.35 0.9 Dimension in MillimetersReference Symbol Min Nom Max ASMx SC-88 0.006g MASS[Typ.] CMPAK-6 / CMPAK-6VPTSP0006JA-A RENESAS CodeJEITA Package Code Previous Code b A-A Section c Package Name CMPAK-6

Ordering Information

Part Name Quantity Shipping Container TBB1002BMTL-E 3000 φ 178 mm Reel, 8 mm Emboss Taping Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product.

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