SPT7851 ETC1

Document overview

  • Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 8

Technical content

Signal Processing Technologies, Inc.

4755 Forge Road, Colorado Springs, Colorado 80907, USA

Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com SPT7851 10-BIT, 20 MSPS, 79 mW A/D CONVERTER

APPLICATIONS

  • CCD Imaging Cameras and Sensors
  • Medical Imaging
  • RF Communications
  • Document and Film Scanners
  • Electro-Optics
  • Transient Signal Analysis
  • Handheld Equipment GENERAL DESCRIPTION The SPT7851 10-bit, 20 MSPS analog-to-digital converter has a pipelined converter architecture built in a CMOS pro- cess. It delivers high performance with a typical power dissi- pation of only 79 mW. With low distortion and high dynamic range, this device offers the performance needed for imag- ing, multimedia, telecommunications and instrumentation applications. The SPT7851 is available in a 44-lead Thin Quad Flat Pack (TQFP) package in the industrial temperature range (–40 °C to +85 °C).

FEATURES

  • 10-Bit, 20 MSPS Analog-to-Digital Converter
  • Monolithic CMOS
  • Internal Track-and-Hold
  • Low Input Capacitance: 1.4 pF
  • Low Power Dissipation: 79 mW
  • 2.8 – 3.6 V Power Supply Range
  • TTL-Compatible Outputs
  • –40 °C to +85 °C Operation Stage Stage Stage Stage Clock Driver Digital Delays, Error Correction and Output VIN+ VIN– VREF+ VREF– CLK Digital Output (D0 – D9) DAC ADC G=2 D<1…0> Pipeline Stage BLOCK DIAGRAM

TA = TMIN–TMAX , VDD1 = VDD2 = VDD3 = 3.3 V, VREF– = 1.0 V, VREF+ = 2.0 V, Common Mode Voltage = 1.65 V, ƒCLK = 20 MSPS, Bias 1 = 90 µA, Bias 2 = 9.5 µA, Differential Input, Duty Cycle = 50%, unless otherwise specified. TEST TEST SPT7851 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS DC Accuracy Resolution Bits Differential Linearity V ±0.6 LSB Integral Linearity V ±0.75 LSB No Missing Codes VI Guaranteed Analog Input Input Voltage Range (Differential) IV ±0.6 ±1.0 ±1.7 V Common Mode Input Voltage IV 1.2 1.65 1.9 V Input Capacitance V 1.4 pF Input Bandwidth (Large Signal) V 120 MHz Offset (Mid-scale) VIN+ = VIN– = VCM V ±1.0 % FSR Gain Error V 0.3 % FSR Reference Voltages Reference Input Voltage Range IV 0.6 1.0 1.7 V (VREF+ – VREF–) Negative Reference Voltage (VREF–) IV 0.9 1.0 1.3 V Positive Reference Voltage (VREF+) IV 1.9 2.0 2.9 V Common Mode Output Voltage (VCM) IO = –1 µA VI 1.3 1.65 1.8 V VREF+ Current V µA VREF– Current V –25 µA Switching Performance Maximum Conversion Rate VI MHz Pipeline Delay IV 7.5 Clocks (See Timing Diagram) Aperture Delay Time (TAP) V ns Aperture Jitter Time V ps-rms ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C Supply Voltages Input Voltages Temperature Note: Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications.

TA = TMIN–TMAX , VDD1 = VDD2 = VDD3 = 3.3 V, VREF– = 1.0 V, VREF+ = 2.0 V, Common Mode Voltage = 1.65 V, ƒCLK = 20 MSPS, Bias 1 = 90 µA, Bias 2 = 9.5 µA, Differential Input, Duty Cycle = 50%, unless otherwise specified. TEST TEST SPT7851 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS Dynamic Performance Effective Number of Bits ƒIN = 5.0 MHz VI 9.0 9.3 Bits ƒIN = 10.0 MHz V 9.0 Bits Signal-To-Noise Ratio ƒIN = 5.0 MHz VI dB ƒIN = 10.0 MHz V dB Total Harmonic Distortion ƒIN=5.0 MHz VI –68 –61 dB ƒIN=10.0 MHz V –60 dB Signal-To-Noise and Distortion ƒIN = 5 MHz VI dB ƒIN = 10 MHz V dB Spurious Free Dynamic Range ƒIN = 5.0 MHz VI dB ƒIN = 10.0 MHz V dB Differential Phase V 0.2 Degrees Differential Gain V 0.5 Digital Inputs Logic 1 Voltage VI 80% VDD Logic 0 Voltage VI 20% VDD Maximum Input Current Low VIN = GND VI µA Maximum Input Current High VIN = VDD VI µA Input Capacitance V 1.8 pF Digital Outputs Logic 1 Voltage IO = –2 mA VI 85% VDD 95% VDD V Logic 0 Voltage IO = +2 mA VI 0.1 0.4 V CLK to Output Delay Time (tD) IV ns Power Supply Requirements Supply Voltages VDD1, VDD2, VDD3 IV 2.8 3.3 3.6 V Supply Current IDD VI mA Power Dissipation VI 100 mW Power Supply Rejection Ratio (PSRR) V dB TEST LEVEL I II III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified con- dition.

TYPICAL PERFORMANCE CHARACTERISTICS THD SNR SINAD THD, SNR, SINAD (dB) 100 101 102 THD, SNR, SINAD vs Input Frequency Input Frequency (MHz) Temperature (°C) THD, SNR, SINAD vs Temperature THD SNR SINAD THD, SNR, SINAD (dB) –40 –25 Power Dissipation (mW) 100 125 150 10 0 101 102 Power Dissipation vs Sample Rate Sample Rate (MSPS) Note: Bias1 and Bias2 optimized for each sample rate. 0.60 0.65 0.70 0.75 0.80 0.85 0.90 IBias 2 (µA) VBias 2 (V) IBias 2 VBias 2 0.6975 0.7535 0.796 0.8295 0.8595 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 120 150 180 IBias1 (µA) VBias1 (V) Bias 1 VBias 1 2.19 2.53 2.79 120 150 3.22 Bias 1 Voltage vs Bias 1 Current Bias 2 Voltage vs Bias 2 Current SNR THD SINAD SNR THD SINAD 10 0 101 102 THD, SNR, SINAD vs Sample Rate Sample Rate (MSPS) Note: Bias1 and Bias2 currents optimized for each sample rate. THD, SNR, SINAD (dB)

N N-1 tD N-2 N-1 N Sampling Points tAP AIN CLK DOUT Figure 2 – Typical Interface Circuit Figure 1 – Timing Diagram GENERAL DESCRIPTION The SPT7851 is an ultra-low power, 10-bit, 20 MSPS ADC. It has a pipelined architecture and incorporates digital error correction of all 10 bits. This error correction ensures good linearity performance for input frequencies up to Nyquist. The inputs are fully differential, making the device insensi- tive to system-level noise. This device can also be used in a single-ended mode. (See analog input section.) With the power dissipation roughly proportional to the sampling rate, this device is ideal for very low power applications in the range of 1 to 20 MSPS. TYPICAL INTERFACE CIRCUIT The SPT7851 requires few external components to achieve the stated operation and performance. Figure 2 shows the typical interface requirements when using the SPT7851 in normal circuit operation. The following sections provide a description of the functions and outline critical performance criteria to consider for achieving the optimal device perfor- mance. GND .01 µF 4.7 µF Ref- In (+1.15 V) Ref+ In (+2.15 V) .01 µF 10 µF 0.1 µF +3.3 V CLK In (3 V Logic) Interfacing

3 V Logic

+3.3 V DGND FB AGND SPT7851 .01 µF (+1.65 V) Minicircuit T1-6T RF In 68 pF N/C N/C N/C GND Bias1 Bias2 VCM GND VIN+ VIN- GND VDD3 GND CLK N/C VDD3 VDD2 VDD2 VDD1 VDD1 VDD1 VRef- VRef+ .01 µF 4.7 µF +3.3 V Digital 9.5 µA 90 µA DNC DNC (LSB) (MSB) Note: 1. All VDD1, VDD2 and VDD3 should be tied together. 2. FB = Ferrite Bead; must be placed as close to U1 as possible.

The SPT7851 accepts a low voltage CMOS logic level at the CLK input. The duty cycle of the clock should be kept as close to 50% as possible. Because consecutive stages in the ADC are clocked in opposite phase to each other, a non- 50% duty cycle reduces the settling time available for every other stage and thus could potentially cause a degradation of dynamic performance. For optimal performance at high input frequencies, the clock should have low jitter and fast edges. The rise/fall times should be kept shorter than 2 ns. Overshoot and undershoot should be avoided. Clock jitter causes the noise floor to rise proportional to the input frequency. Because jitter can be caused by crosstalk on the PC board, it is recommended that the clock trace be kept as short as possible and stan- dard transmission line practices be followed. DIGITAL OUTPUTS The digital output data appears in an offset binary code at 3.3 V CMOS logic levels. A negative full scale input results in an all zeros output code (000…0). A positive full scale PACKAGE OUTLINE 44L TQFP INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A

0.472 Typ

12.00 Typ

B

0.394 Typ

10.00 Typ

C D E

0.031 Typ

0.80 Typ

F 0.012 0.018 0.300 0.45 G 0.053 0.057 1.35 1.45 H 0.002 0.006 0.05 0.15 I 0.018 0.030 0.450 0.750 J

0.039 Typ

1.00 Typ

K 0-7° 0-7° input results in an all 1’s code (111…1). The output data is available 7.5 clock cycles after the data is sampled. The in- put signal is sampled on the high to low transition of the input clock. Output data should be latched on the low to high clock transition as shown in figure 1, the Timing Diagram. The output data is invalid for the first 20 clock cycles after the device is powered up. EVALUATION BOARD The EB7851 Evaluation Board is available to aid designers in demonstrating the full performance capability of the SPT7851. The board includes an on-board clock driver, ad- justable voltage references, adjustable bias current circuits, single-to-differential input buffers with adjustable levels, a single-to-differential transformer (1:1), digital output buffers and 3.3/5 V adjustable logic outputs. An application note (AN7851) is also available which describes the operation of the evaluation board and provides an example of the recom- mended power and ground layout and signal routing. Con- tact the factory for price and availability. Index A B C D Pin 1 E F G H I J K

www.digicamel.com Copyright © Each Manufacturing Company. All Datasheets cannot be modified without permission. This datasheet has been download from : www.digicamel.com 100% Free DataSheet Search Site. Free Download. No Register. Fast Search System. www.digicamel.com