SMJ27C512

TMS27C512 TI

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TMS27C512 65536 BY 8-BIT UV ERASABLE TMS27PC512 65536 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068Organization...6 5 5 3 6 b y 8 Bits /C0068Single 5-V Power Supply /C0068Pin Compatible With Existing 512K MOS ROMs, PROMs, and EPROMs /C0068All Inputs/Outputs Fully TTL Compatible /C0068Max Access/Min Cycle Time VCC ± 10% ’27C/PC512-10 100 ns ’27C/PC512-12 120 ns ’27C/PC512-15 150 ns ’27C/PC512-20 200 ns ’27C/PC512-25 250 ns /C0068Power Saving CMOS Technology /C0068Very High-Speed SNAP! Pulse Programming /C00683-State Output Buffers /C0068400-mV Minimum DC Noise Immunity With Standard TTL Loads /C0068Latchup Immunity of 250 mA on All Input and Output Lines /C0068Low Power Dissipation ( VCC = 5.25 V ) – Active . . . 158 mW Worst Case – Standby... 1.4 mW Worst Case (CMOS Input Levels) /C0068Temperature Range Options /C0068512K EPROM Available With MIL-STD-883C Class B High Reliability Processing (SMJ27C512)

description

The TMS27C512 series are 65536 by 8-bit (524288-bit), ultraviolet (UV) light erasable, electrically programmable read-only memories (EPROMs). The TMS27PC512 series are 65536 by 8-bit (524288-bit), one-time programmable (OTP) electrically programmable read-only memories (PROMs). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 321 3 2 3 1 43 0 15 16 17 18 19 20 PIN NOMENCLATURE A0–A15 Address Inputs E Chip Enable/Power Down DQ0–DQ7 Inputs (programming)/Outputs G /VPP 13-V Programming Power Supply GND Ground NC No Internal Connection NU Make No External Connection VCC 5-V Power Supply J PACKAGE (TOP VIEW) A15 A12 DQ0 DQ1 DQ2 GND V CC A14 A13 A11 G /VPP A10 E DQ7 DQ6 DQ5 DQ4 DQ3 A8 A11 NC G /VPP A10 E DQ7 DQ6 NC DQ0 DQ1 DQ2 NU DQ3 DQ4 A12 A15 NU V A14 A13 FM PACKAGE (TOP VIEW) DQ5 CC GND PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  1997, Texas Instruments Incorporated

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TMS27PC512 are pin compatible with 28-pin 512K MOS ROMs, PROMs, and EPROMs. plastic leaded chip carrier package using 1,25-mm (50-mil) lead spacing (FM suffix). FML suffix) and – 40°C to 85°C (JE and FME suffix). See Table 1. All package styles conform to JEDEC standards. Table 1. Temperature Range Suffixes PP of 13 V and a VCC of 6.5 V for a nominal programming time of seven seconds. programmed singly, in blocks, or at random.

TTL level except for VPP during programming (13 V for SNAP! Pulse) and 12 V on A9 for signature mode. Table 2. Operation Modes pins. Output data is accessed at pins DQ0 through DQ7. Latchup immunity on the TMS27C512 and TMS27PC512 is a minimum of 250 mA on all inputs and outputs. without compromising performance or packing density. necessary to assure that all bits are in the logic high state. Logic lows are programmed into the desired locations.

1. A typical 12-mW/cm2, filterless UV lamp erases the device in

window should be covered with an opaque label.

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are programmed into the desired locations. Logic lows programmed into a PROM cannot be erased. time varies as a function of the programmer used. pulses per byte are provided before a failure is recognized. (eight bits) on pins DQ0 to DQ7. Once addresses and data are stable, E is pulsed. CC = 5 V, G/VPP = VIL, and E = VIL. Programming can be inhibited by maintaining a high level input on the E pin. Programmed bits can be verified when G/VPP and E = VIL. A0 high selects the device code 85, as shown in Table 3. Table 3. Signature Mode

Figure 1. SNAP! Pulse Programming Flow Chart

TMS27C512 65536 BY 8-BIT UV ERASABLE TMS27PC512 65536 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

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logic symbols† [PWR DWN] EN A A A A A A A A A10 A11 A12 A13 A14 A15 E G /VPP EPROM 65 536 × 8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 A 0 65 535 A 0 65 535 A A A A A A A A [PWR DWN] EN A10 A11 A12 A13 A14 A15 E G /VPP OTP PROM 65 536 × 8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 † These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the J package. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND.

TMS27C512 65536 BY 8-BIT UV ERASABLE TMS27PC512 65536 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage Read mode (see Note 2) 4.5 5 5.5 VVCC Supply voltage SNAP! Pulse programming algorithm 6.25 6.5 6.75 V G /VPP Supply voltage SNAP! Pulse programming algorithm 12.75 13 13.25 V VIH High level dc input voltage TTL 2 VCC +1 VVIH High-level dc input voltage CMOS VCC – 0.2 VCC +1 V VIL Low level dc input voltage TTL – 0.5 0.8 VVIL Low-level dc input voltage CMOS – 0.5 0.2 V TA Operating free-air temperature TMS27C512-_ _JL TMS27PC512-_ _FML 0 70 °C TA Operating free-air temperature TMS27C512-_ _JE TMS27PC512-_ _FME –4 0 85 °C NOTE 2: V CC must be applied before or at the same time as G/VPP and removed after or at the same time as G/VPP. The device must not be inserted into or removed from the board when VPP or VCC is applied. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VOH High level dc output voltage IOH = – 2.5 mA 3.5 VVOH High-level dc output voltage IOH = – 20 µA VCC – 0.1 V VOL Low level dc output voltage IOL = 2.1 mA 0.4 VVOL Low-level dc output voltage IOL = 20 µA 0.1 V II Input current (leakage) VI = 0 V to 5.5 V ±1 µA IO Output current (leakage) VO = 0 V to VCC ±1 µA IPP G /VPP supply current (during program pulse)G /VPP = 13 V 35 50 mA ICC1 VCC supply current (standby) µAICC1 VCC supply current (standby) µA ICC2 VCC supply current (active) VCC = 5.5 V, E = VIL, tcycle = minimum cycle time, outputs open 15 30 mA † Typical values are at TA = 25°C and nominal voltages. capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz† PARAMETER TEST CONDITIONS MIN TYP ‡ MAX UNIT C I Input capacitance VI = 0 V, f = 1 MHz 6 10 pF C O Output capacitance VO = 0 V, f = 1 MHz 10 14 pF C G/VPP G /VPP input capacitance G /VPP = 0 V, f = 1 MHz 20 25 pF † Capacitance measurements are made on a sample basis only. ‡ Typical values are at TA = 25°C and nominal voltages.

TMS27C512 65536 BY 8-BIT UV ERASABLE TMS27PC512 65536 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

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switching characteristics over recommended ranges of operating conditions PARAMETER TEST CONDITIONS (SEE NOTES 3 AND 4) ’27C512-10 ’27PC512-10 ’27C512-12 ’27PC512-12 UNIT(SEE NOTES 3 AND 4) MIN MAX MIN MAX ta(A) Access time from address 100 120 ns ta(E) Access time from chip enable C L = 100 pF, 100 120 ns ten(G) Output enable time from G/VPP C L = 100 F,

1 Series 74 TTL Load, 55 55 ns

tdis Output disable time from G/VPP or E, whichever occurs first† Input tr ≤ 20 ns, Input tf≤ 20 ns 0 45 0 45 ns tv(A) Output data valid time after change of address, E, or G/VPP, whichever occurs first† Input tf ≤ 20 ns 0 0 ns PARAMETER TEST CONDITIONS (SEE NOTES 3 AND 4) ’27C512-15 ’27PC512-15 UNIT(SEE NOTES 3 AND 4) MIN MAX ta(A) Access time from address 150 ns ta(E) Access time from chip enable C L = 100 pF, 150 ns ten(G) Output enable time from G/VPP C L = 100 F,

1 Series 74 TTL Load, 75 ns

tdis Output disable time from G/VPP or E, whichever occurs first† Input tr ≤ 20 ns, Input tf≤ 20 ns 0 60 ns tv(A) Output data valid time after change of address, E, or G/VPP, whichever occurs first† Input tf ≤ 20 ns 0 ns PARAMETER TEST CONDITIONS (SEE NOTES 3 AND 4) ’27C512-20 ’27PC512-20 ’27C512-25 ’27PC512-25 UNIT(SEE NOTES 3 AND 4) MIN MAX MIN MAX ta(A) Access time from address 200 250 ns ta(E) Access time from chip enable C L = 100 pF, 200 250 ns ten(G) Output enable time from G/VPP C L = 100 F,

1 Series 74 TTL Load, 75 100 ns

tdis Output disable time from G/VPP or E, whichever occurs first† Input tr ≤ 20 ns, Input tf≤ 20 ns 0 60 0 60 ns tv(A) Output data valid time after change of address, E, or G/VPP, whichever occurs first† Input tf ≤ 20 ns 0 0 ns † Value calculated from 0.5 V delta to measured output level. This parameter is only sampled. NOTES: 3. For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and 0.8 V for logic low (see Figure 2). 4. Common test conditions apply for tdis except during programming. switching characteristics for programming: VCC = 6.50 V and G/VPP = 13 V (SNAP! Pulse), TA = 25°C (see Note 3) PARAMETER MIN MAX UNIT tdis(G) Disable time, output from G/VPP 0 130 ns NOTE 3: For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and 0.8 V for logic low.

NOTES: A. C L includes probe and fixture capacitance. Figure 2. AC Testing Output Load Circuit

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Figure 3. Read-Cycle Timing † tdis(G) is a characteristic of the device but must be accommodated by the programmer. ‡ 13-V G/VPP and 6.5-V VCC for SNAP! Pulse programming. Figure 4. Program-Cycle Timing (SNAP! Pulse Programming)

TMS27C512 65536 BY 8-BIT UV ERASABLE TMS27PC512 65536 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 FM (R-PQCC-J32) PLASTIC J-LEADED CHIP CARRIER 4040201-4/B 03/95 0.020 (0,51) 0.015 (0,38) Seating Plane 0.140 (3,56) 0.132 (3,35) 0.123 (3,12) 0.129 (3,28) 0.043 (1,09) 0.049 (1,24) 0.008 (0,20) NOM 0.595 (15,11) 0.553 (14,05) 0.585 (14,86) TYP 0.030 (0,76) 0.547 (13,89) 301 0.495 (12,57) 0.453 (11,51) 0.485 (12,32) 0.447 (11,35) 0.050 (1,27) 0.004 (0,10) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-016

TMS27C512 65536 BY 8-BIT UV ERASABLE TMS27PC512 65536 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

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J (R-CDIP-T) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE 4040084/B 04/95 B C 0.018 (0,46) MIN 0.125 (3,18) MIN 0.022 (0,56) 0.008 (0,20) Seating Plane A WIDE A PINS DIM MAX MIN NARR MIN MAX B C MAX MIN NARR WIDE NARR WIDE WIDE NARR

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0.045 (1,14) 0.065 (1,65) 0.090 (2,29) 0.060 (1,53) Lens Protrusion 0.010 (0,25) MAX 0.175 (4,45) 0.140 (3,56) 0.100 (2,54) 0°–10° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.

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