SM5170

SM5170AV NPC

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Technical content

NIPPON PRECISION CIRCUITS—1 NIPPON PRECISION CIRCUITS INC. PLL Synthesizer IC OVERVIEW The SM5170A V is a PLL synthesizer IC developed for application in pagers. It incorporates indepen- dently-controlled reference frequency and FIN input frequency dividers, and operates from a low-voltage supply to realize low power dissipation. It features a charge pump that operates at 3 V , making possible a wide range of VCO designs.

FEATURES

n Supply voltages DD1 = 0.95 to 1.2 V (prescaler, counters) DD2 = 2.0 to 3.3 V (charge pump) n FIN input frequency FIN = 300 MHz (V DD1 = 0.95 V) FIN = 330 MHz (V DD1 = 1.0 V) n Reference frequency XIN = 25 MHz (V DD1 = 0.95 V) n 20 to 262140 reference frequency divider ratio range (with 1/4 prescaler built-in) n 1056 to 131071 FIN input frequency divider ratio range n 10 to 60 C operating temperature range n 16-pin VSOP PINOUT (Top view)

ORDERING INFORMATION

NIPPON PRECISION CIRCUITS—2 PACKAGE DIMENSIONS Unit: mm 16-pin VSOP BLOCK DIAGRAM 4.4 0.2 6.4 0.2 5.1 0.2 1.15 0.1 0.10 0.05 0.15 + 0.10- 0.05 01 0 0.5 0.2 0.275typ 0.65 0.22- 0.05 + 0.10 0.12 M 0.10 XOUT XIN CLK DATA LE OPR 1/4 Prescaler DO 16Bit R-Counter 16Bit R-Latch Latch Selector 22Bit Shift Register 17Bit N-Latch 5Bit Swallow Counter 12Bit Main CounterFIN Dual Modulus Prescaler Level Shifter Phase Detector Charge Pump Lock Detector LD Boost Signal Generator DB VDD1 AREA(1V) VDD2 AREA(3V) VDD1 AREA(1V)

NIPPON PRECISION CIRCUITS—3 PIN DESCRIPTION SPECIFICATIONS Absolute Maximum Ratings V SS = 0 V Recommended Operating Conditions V SS = 0 V Number Name I/O Supply Description 1 XIN I 1 V Reference frequency divider crystal oscillator connection pins. Alter natively, an external clock input can be connected to XIN. The clock is output on XOUT . F eedback resistor b uilt-in for A C-coupled inputs.2 XOUT O 1 V

3 VDD2 – 3 V Phase compar ator, charge pump and booster signal 3 V supply

4 DB O 3 V Booster signal output for faster loc king

5D OO3 V Phase compar ator output pin. Built-in charge pump and tristate output means that this output can be connected to a lo w-pass fi lter. The output polar ity is preset for connection to a passive fi lter.

6 VSS – – Ground pin

7 FIN I 1 V FIN input frequency divider input pin. F eedback resistor b uilt-in for A C-coupled inputs.

8 VDD1 – 1 V Ref erence frequency and FIN input frequency prescaler and counter 1 V supply

9 NC – – No connection

10 LD O 1 V Unlock signal output pin. (Unlocked when LOW). The function of LD can be tur ned OFF using the LD input control bit (LD should be tied LOW when not used).

11 CLK I 3 V Control data clock input pin

12 DATA I 3 V Control data input pin

13 LE I 3 V Control data latch enable signal input pin

14 OPR I 3 V Power-save control pin. Start when HIGH, standby mode when LOW.

15 NC – – No connection

16 TEST I 1 V T est pin. Pull-down resistor b uilt-in. Leave open or connect to ground for nor mal oper ation. Parameter Symbol Condition Rating Unit Supply voltage V DD1 VDD1 0.3 to 2.0 V V DD2 VDD2 0.3 to 4.6 V Input voltage r ange V IN1 FIN, XIN, TEST V SS 0.3 to V DD1 + 0.3 V V IN2 OPR, CLK, DATA, LE V SS 0.3 to V DD2 + 0.3 V Stor age temper ature r ange T stg 40 to 125 C Pow er dissipation P D 150 m W Parameter Symbol Condition Rating Unit Supply voltage V DD1 VDD1 0.95 to 1.2 V V DD2 VDD2 2.0 to 3.3 V Oper ating temper ature r ange T opr 10 to 60 C

NIPPON PRECISION CIRCUITS—4

Electrical Characteristics

V SS = 0 V , V DD1 = 0.95 to 1.2 V , V DD2 = 2.0 to 3.3 V , T a 10 to 60 C DATA, CLK, and LE timing Parameter Symbol Condition Rating Unit min typ max VDD1 oper ating current consumption I DD1 Note 1. 1. V DD1 = 1.0 to 1.05V , V DD2 = 2.7 to 3.3 V, f FIN = 310 MHz (300 mVp-p sine wav e), f XIN = 14.4 MHz (300 mVp-p sine wave), 25 kHz compar ator fre- quency, OPR = HIGH, no output load, typ condition : V DD1 = 1.0 V – 1.1 1.9 mA VDD2 oper ating current consumption I DD2 Note 2. 2. V DD1 = 0.95 to 1.2 V, V DD2 = 2.7 to 3.3 V, f FIN = 310 MHz (300 mVp-p sine wav e), f XIN = 14.4 MHz (300 mVp-p sine wave), 25 kHz compar ator fre- quency, OPR = HIGH, no output load, typ condition : V DD2 = 3.0 V – 0.003 – VDD1 standby current I st1 Note 3. 3. V DD1 = 1.0 V, V DD2 = 3.0 V, OPR = LOW, no input/output load (i.e. CLK = DATA = LE = 0 V) – 0.7 – µA VDD2 standby current I st2 Note 4. 4. V DD1 = 0 V, V DD2 = 2.7 to 3.3 V, OPR = LOW, no input/output load (i.e. CLK = DATA = LE = 0 V), typ condition : V DD2 = 3.0 V – 0.01 10.0 FIN maximum oper ating input frequency f max1 300 mVp-p sine wave V DD1 = 0.95 to 1.2 V 300 – – MHz V DD1 = 1.0 to 1.2 V 330 – – XIN maximum oper ating input frequency f max2 300 mVp-p sine wave (e xternal input) 25 – – MHz FIN minimum oper ating input frequency f min1 300 mVp-p sine wave – – 40 MHz XIN minimum oper ating input frequency f min2 300 mVp-p sine wave (e xternal input) – – 9 MHz FIN input amplitude V FIN1 f FIN = 300 MHz, AC coupling 0.3 – – Vp-p V FIN2 f FIN = 330 MHz, V DD1 = 1.0 to 1.2 V, AC coupling 0.3 – – XIN input amplitude V XIN f XIN = 25 MHz, AC coupling (e xternal input) 0.3 – – Vp-p OPR, CLK, DATA, LE LOW -level input voltage V IL – – 0.3 V OPR, CLK, DATA, LE HIGH-level input voltage V IH V DD2 0.3 ––V FIN LOW -level input current I IL1 V IL = 0 V –– 6 0 µ A XIN LOW -level input current I IL2 –– 1 0 µ A FIN HIGH-level input current I IH1 V IH = V DD1 –– 6 0 µ A XIN HIGH-level input current I IH2 –– 1 0 µ A DB LOW -level output v oltage V DOL Note 5. 5. DB output is derived from the V DD2 supply. DB-pin condition select bit = (00001) , V DD2 = 2.7 to 3.3 V, no load 0.5 V DB HIGH-level output v oltage V DOH Note 6. 6. DB output is derived from the V DD2 supply. DB-pin condition select bit = (11111) , V DD2 = 2.7 to 3.3 V, no load V DD2 0.5 V DO LOW -level output current I DOL Note 7. 7. DO output is derived from the V DD2 supply. V DD2 = 2.7 to 3.3 V, V OL = 0.4 V 1.0 – – m A DO HIGH-level output current I DOH Note 8. 8. DO output is derived from the V DD2 supply. V DD2 = 2.7 to 3.3 V, V OH = V DD2 0.4 V 1.0 – – m A D O, DB tristate output high-impedance leakage current I OZL V OL = 0 V – – 100 nA I OZH V OH = V DD2 – – 100 nA DAT A fi CLK setup time t SU1 See the timing diagrams. 2–– µ s CLK fi LE setup time t SU2 2–– µ s Hold time t H 2–– µ s VIH tSU1 tSU2 VIH VIH VIH tHDATA CLK LE

being written to the shift register. The last two data bits determine the status of the shift register data latch. Figure 1. Frequency divider data format Figure 2. Latch select data format

00 S w allow counter and main counter frequency

01 Reference frequency counter divider r atio

ence frequency divider ratio is set by bits 1 to 16. The lock detect signal output is set by bit 20. The output on LD is set by bit 20.

1. Bits 21 and 22 are factory test bits and should also

Figure 5. Reference counter data and LD output setting format

1 Normal unlock signal output (nor mal oper ation)

0 Unlock signal output OFF , LOW -level output

NIPPON PRECISION CIRCUITS—9 INPUT/OUTPUT EQUIVALENT CIRCUITS XIN, XOUT DO LD FIN DB OPR, CLK, DATA, LE TEST From Internal Circuits XIN XOUT To Internal Counter From Internal Circuits DO Lagging Phase Correction Signal Leading Phase Correction Signal From Internal Circuits LD From Internal Circuits FIN To Internal Counter From Internal Circuits From Internal Circuits DB From Internal Circuits From Internal Circuits From Internal Circuits To Internal Circuits CLK DATA LE OPR To Internal Circuits TEST

NIPPON PRECISION CIRCUITS—10 NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility fo r the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infr ingement. Applications for any devices shown in this data sheet are for illustr ation only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing o r modification. The products described in this data sheet are not intended to use for the apparatus which infl uence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinaft er, including compliance with export controls on the distribution or dissemination of the products. Customers shall not e xport, directly or indirectly, any products without first obtaining required licenses and approv als from appropriate gover nment agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, J apan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9808CE 1999.8 NIPPON PRECISION CIRCUITS INC.