SM5165

SM5165AV NPC

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Technical content

NIPPON PRECISION CIRCUITS—1 NIPPON PRECISION CIRCUITS INC. PLL Synthesizer IC OVERVIEW The SM5165A V is a PLL synthesizer IC developed for application in pagers and fabricated using NPC’s Molybdenum-gate CMOS process. It incorporates independently-controlled reference frequency and operating frequency dividers, and operates from a low-voltage supply to realize low power dissipation.

FEATURES

n Up to 90 MHz operating frequency DD1 = V DD2 = 0.95 V) n Up to 100 MHz operating frequency DD1 = V DD2 = 1.00 V) n Supply voltages DD1 = V DD2 = 0.95 to 1.5 V (prescaler, counters) DD3 = 2.0 to 3.3 V (charge pump) n 40 to 16376 reference frequency divider ratio range (with 1/8 prescaler built-in) n 1056 to 262143 operating frequency divider ratio range n Power-save function for reduced power dissipation n 10 to 60 C operating temperature range n 16-pin VSOP n Molybdenum-gate CMOS process

APPLICATIONS

n Pagers ORDERING INFOMATION Device Package SM5165AV 16pin VSOP PINOUT (TOP VIEW) PACKAGE DIMENSIONS Unit: mm 16-pin VSOP VDD1 FIN VSS RO TEST DO DB XIN XOUT LE CLK DATA OPR VDD2 NC VDD3 16pin VSOP 5165AV 4.4 0.2 6.4 0.2 5.1 0.2 0.65 1.15 0.1 0.10 0.05 0.22+ 0.10- 0.05 0.15 + 0.10- 0.05 01 0 0.5 0.2

NIPPON PRECISION CIRCUITS—2 BLOCK DIAGRAM PIN DESCRIPTION Protection diodes are connected to VDD3. Logic level : V DD2 to V DD3 Number Name I/O Description

1 VDD1 – Ref erence frequency and comparator frequency prescaler and counter 1 V supply

2 FIN I Operating frequency divider input pin. Feedback resistor built-in for AC-coupled inputs.

3 VSS1 – Ground pin

4R O O Test output. LOW-level output for (1, 0) test bit patter. Leave open for normal operation. 5 TEST I Test pin. Pull-down resistor built-in. Leave open or connect to ground for normal operation. 6D O O Phase detector output pin. Built-in charge pump and tristate output means that this output can be connected to a low-pass filter. The output polarity is preset for connection to a passive filter.

7 DB O Booster signal output for faster locking

8 NC – No connection

9 VDD3 – Phase compar ator, charge pump and booster signal 3 V supply

10 VDD2 – Shift register and latch 1 V supply. Should be kept at the same potential as VDD1. 11 OPR I Power-save control pin. Operation when HIGH, standby mode when LOW.

12 DATA I Control data input pin

13 CLK I Control data clock input pin

14 LE I Control data latch enable signal input pin

15 XOUT O Ref erence frequency divider crystal oscillator connection pins. Alternatively, an external clock input can be connected to XIN. The clock is also output on XOUT. Feedback resistor built-in for AC-coupled inputs.16 XIN I

11 BIT

18 BIT

18 BIT LATCH

11 BIT LATCH

22 BIT

S. G. LATCH SELECTER FIN WINDOW GENERATOR OPR LEVEL SHIFTER LEVEL SHIFTER LEVEL SHIFTER VDD1 AREA VDD2 AREA VDD3 AREA VDD2 VDD3

NIPPON PRECISION CIRCUITS—3 SPECIFICATIONS Absolute Maximum Ratings V SS = 0 V Recommended Operating Conditions V SS = 0 V

Electrical Characteristics

V SS = 0 V , V DD1 = V DD2 = 0.95 to 1.5 V , V DD3 = 2.0 to 3.3 V , T a 10 to 60 C Parameter Symbol Condition Rating Unit Supply voltage V DD1,2 0.3 to 2.0 V V DD3 0.3 to 7.0 V Input voltage range V IN1 FIN, XIN, TEST V SS 0.3 to V DD1,2 + 0.3 V V IN2 OPR, CLK, DATA, LE V SS 0.3 to V DD3 + 0.3 V Storage temperature range T stg 40 to 125 C Power dissipation P D 150 mW Soldering temperature T sld 255 C Soldering time t sld 10 s Parameter Symbol Condition Rating Unit Supply voltage V DD1,2 0.95 to 1.5 V V DD3 2.0 to 3.3 V Storage temperature range T stg 10 to 60 C Parameter Symbol Condition Rating Unit min typ max VDD1, VDD2 oper ating current consumption I DD1 Note 1. – 0.70 1.10 mA Note 2. – 0.75 1.20 VDD3 oper ating current consumption I DD2 –1 0–µ A VDD2 standby current I DD3 Note 3. – 0.1 – µA VDD3 standby current I DD4 – 0.01 10.0 µA FIN maximum oper ating input frequency f max1 300 mVp-p sine wave V DD1,2 = 0.95 to

1.50 V 90 – –

V DD1,2 = 1.00 to

1.50 V 100 – –

XIN maximum oper ating input frequency f max2 300 mVp-p sine wave. Note 4. 16 – – MHz FIN minimum oper ating input frequency f min1 300 mVp-p sine wave – – 40 MHz XIN minimum oper ating input frequency f min2 300 mVp-p sine wave. Note 4. – – 9 MHz FIN input amplitude V FIN V DD1,2 = 0.95 to 1.50 V, f FIN = 90 MHz, AC coupling 0.3 – – Vp-p V DD1,2 = 1.00 to 1.50 V, f FIN = 100 MHz, AC coupling 0.3 – – XIN input amplitude V XIN f XIN = 16 MHz, AC coupling 0.3 – – Vp-p OPR, CLK, DATA, LE LOW-level input voltage V IL – – 0.2V DD2 V

NIPPON PRECISION CIRCUITS—4 OPR, CLK, DATA, LE HIGH-level input voltage V IH 0.8V DD2 DD3 V FIN LOW-level input current I IL1 V IL = 0 V –– 6 0 µ A XIN LOW-level input current I IL2 –– 1 0 µ A FIN HIGH-level input current I IH1 V IH = V DD1 –– 6 0 µ A XIN HIGH-level input current I IH2 –– 1 0 µ A DO, DB LOW-level output current I OL Note 5. 1.0 – – mA DO, DB HIGH-level output current I OH Note 6. 1.0 – – mA Tristate output high-impedance leakage current I OZL V OL = 0 V – – 100 nA I OZH V OH = V DD3 – – 100 nA DATA fi CLK setup time t SU1 Note 7. 2–– µ s CLK fi LE setup time t SU2 2–– µ s Hold time t H 2–– µ s 1. V DD1 = V DD2 = 0.95 to 1.05 V, V DD3 = 2.7 to 3.3 V, f FIN = 90 MHz (300 mVp-p sine wav e), f XIN = 14.4 MHz (300 mVp-p sine wave), OPR = HIGH, no output load 2. V DD1 = V DD2 = 1.00 to 1.05 V, V DD3 = 2.7 to 3.3 V, f FIN = 100 MHz (300 mVp-p sine wave), f XIN = 14.4 MHz (300 mVp-p sine wave), OPR = HIGH, no output load 3. V DD1 = 0 V, V DD2 = 0.95 to 1.05 V, V DD3 = 2.7 to 3.3 V, OPR = LOW, no input/output load (i.e. CLK = DATA = LE = 0 V) 4. Externally-input sine wave 5. DO and DB outputs are derived from the V DD3 supply. V DD3 = 2.7 to 3.3 V, V OL = 0.4 V 6. DO and DB outputs are derived from the V DD3 supply. V DD3 = 2.7 to 3.3 V, V OH = V DD3 0.4 V 7. Setup and hold times. Parameter Symbol Condition Rating Unit min typ max VIH tSU1 tSU2 VIH VIH VIH tHDATA CLK LE

NIPPON PRECISION CIRCUITS—5 FUNCTIONAL DESCRIPTION Operating Frequency Divider (N-counter) Structure The operating frequency divider generates a compar- ator frequency signal (FV), which is input to the phase comparator, by dividing the VCO signal input on pin FIN. The operating frequency divider is comprised by dual modulus prescalers, a 5-bit swallow counter and a 13-bit main counter. The settings for the dual modulus prescaler (P and P + 1), swallow counter (S) and main counter (M) are related to the comparator frequency divider ratio by: The counter value ranges are P = 32, P + 1 = 33, S = 0 to 31, and M = 32 to 8191. Therefore, the compara- tor frequency divider ratio range N is 1056 to 262143. Reference Frequency Divider (R-counter) Structure The reference frequency divider generates a compar- ator frequency signal (FR), which is input to the phase comparator, by dividing the reference oscilla- tor frequency input either from an external signal on XIN or from a crystal oscillator connected between XIN and XOUT. The reference frequency divider is comprised by a fixed divide-by-8 prescaler and an 11-bit reference counter. NP 1 +() SP MS –()+·= PM S+= The settings for the prescaler (A = 8) and reference counter (R) are related to the reference frequency divider ratio by: The counter value ranges are A = 8 and B = 5 to 2047. Therefore, the reference frequency divider ratio range is R = 40 to 16376. Input Data The input data should be specified keeping in mind both the V DD2 and V DD3 supplies. The data is input using CLK, DATA and LE pins into the shift register and latch which operate from the V DD2 supply. How- ever, the input voltages can be specified using either the V DD2 or V DD3 supply levels. The control data input uses a 3-line 23-bit serial interface comprising the clock (CLK), data input (DATA) and latch enable (LE). The data is input with the MSB first. The last (23rd) bit is used as the latch select control bit. Data is written to the shift register on the rising edge of the clock signal. Accordingly, the data should change state on the falling edge of the clock signal. Data is transferred from the shift register to the latch when the latch enable (LE) sig- nal goes HIGH. Accordingly, the latch enable signal should be held LOW while data is being written to the shift register. The clock and data input signals are both ignored when the latch enable signal goes HIGH. RA B8 B== Input data format 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 MSB CLK DATA LE 18 19 20 21 22 23 LSB CONTROL 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 MSB CLK DATA LE 18 19 20 21 22 23 LSB CONTROL

NIPPON PRECISION CIRCUITS—6 Latch select The last (23rd) data bit determines the shift register data latch. Swallow counter, main counter frequency divider data and DO output Bits 19 and 20 have no meaning. These bits should be set to 0. Bits 20 and 21 control the state of the DO output pin. The DO output polarity can be set by master-slice for either a passive or active filter. Input data example If the VCO output is (fVCO ) trebled, the output frequency (fLO ) is 251.3 MHz, and the channel bandwidth (fCH : comparator frequency (fR ) · 3) is 25 kHz, then the comparator frequency divider ratio N is given by: Therefore, the swallow counter count is 4 (00100)2 and the main counter count is 314 (0000100111010)2. Bit 23 Latch

0 Reference frequency counter divider ratio data latch

1 Swallow counter and main counter frequency divider

ratio and DO output latch select Bit 21 Bit 22 DO output High impedance Normal operation Main counter (13-bit : 32 to 8191) No meaning 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 MSB DATA 18 19 20 21 22 23 LSB 22222222222222221 2 1 1 1 0 9876543210432 2210 Swallow counter (5-bit : 0 to 31) Latch select bit. Setting "1" DO output select bits N fLO fCH fVCO 3· 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 MSB 18 19 20 21 22 23 LSB 22222222222222221 2 1 1 1 0 9876543210432 2210 00001001110100010 000111Input Data Main counter (13-bit : 32 to 8191) No meaningSwallow counter (5-bit : 0 to 31) Latch select bit. Setting "1" DO output select bits

NIPPON PRECISION CIRCUITS—7 Reference counter frequency divider setting Bits 1 to 7 and bits 21 and 22 have no meaning. These bits should be set to 0. Bits 8 and 9 are used for testing at the manufacturers and should be set to 1 and 0, respectively, for normal operation. Input data example If the VCO output is (fVCO ) trebled, the crystal oscillator frequency is 12.8 MHz and the channel bandwidth (fCH : comparator frequency (fR ) · 3) is 25 kHz, then the reference frequency divider ratio R is given by: Therefore, the reference counter count is 192 (00011000000)2. Boost-up Signal No meaning 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 MSB DATA 18 19 20 21 22 23 LSB 222222222221 0 9876543210 Reference counter (11-bit : 5 to 8191) Latch select bit. Set "0" Test bits No meaning NR Xtal fCH 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 MSB 18 19 20 21 22 23 LSB 222222222221 0 9876543210 00000001000011000 000000Input Data No meaningReference counter (11-bit : 5 to 8191) Latch select bit. Set "0" Test bits No meaning When the PLL starts up with some phase tolerance, a level signal is output on pin DB. When the PLL phase error comes within the tolerance before in lock, output DB goes high impedance. When the PLL starts up, the signal on DB charges the low-pass filter capacitor in anticipation of high- speed locking. After the boost-up signal is output and the PLL phase error comes within tolerance, the boost-up circuit stops and operation continues when the 3 supplies (V DD1 , VDD2 ) are applied and OPR goes HIGH once only. After the boost-up circuit stops, new data is written and the boost-up signal is not output even if the VCO is not in lock. FR FV Phase detector error correction signal WINDOWN DB ∗∗ ∗ ∗ (High impedance) (High impedance) (HIGH level output) : 32fFIN∗()

NIPPON PRECISION CIRCUITS—8 Operating principles When the PLL is operating with a phase error within fixed tolerance, an internal WINDOWN signal is generated. This signal is in sync with the N counter output signal (FV) and is 62 cycles of the FIN input period in length centered about the falling edge of FV . If the phase detector error correction signal occurs before the WINDOWN LOW-level pulse, the HIGH- level output from DB continues. However, if the error correction signal occurs wholly within the WINDOWN LOW-level pulsewidth, DB goes high impedance and the boost-up circuit operation stops. The above description applies when the error correc- tion signal is revising up. When the error correction signal is revising down, DB goes LOW. Standby Mode The SM5165A V enters standby mode when OPR goes LOW. In this mode, the following pin states and functions occur. Note that even in standby mode, some current flows into VDD1 (FIN and XIN prescaler current). It is recommended that VDD1 be grounded in standby mode to reduce current consumption if necessary. Note also that the above pin states and functions are only valid if V DD2 and VDD3 are maintained within normal operating conditions. If VDD2 and/or VDD3 Function State Outputs DO and DB Floating (high impedance) Phase detector Reset Input FIN F eedback resistor is cutoff (internal HIGH level) Input XIN F eedback resistor is cutoff (internal HIGH level) N counter Reset R counter Reset Latch data Stored are not within normal operating conditions, the latch data is not retained. Phase Comparator Timing Diagram Passive Low-pass Filter FV and FR are the internal comparator frequency divider output signal and reference frequency divider output signal, respectively. FR FV DO LD DO C VCO

NIPPON PRECISION CIRCUITS—9 Input/Output Equivalent Circuits XIN, XOUT DO (for passive filter) DB RO FIN OPR, CLK, DATA, LE TEST VDD1 XIN To Internal Counter Transistor Resistor VDD1 Intenal Circuit From Internal Circuit VDD1 From Internal Circuit XOUT VDD2 DO Lagging Phase Correction Signal Leading Phase Correction Signal VDD2 DB From Internal Circui From Internal Circui VDD2 RO (FV, FR) (for TEST mode) From Internal Circuit VDD1 To Internal Counter FIN1 Diffused Resistor VDD1 From Internal Circuit VDD2 OPR CLK DATA LE To Intenal Circuit VDD1 To Intenal Circuit TEST VDD1 Transistor Resistor

NIPPON PRECISION CIRCUITS—10 NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon P recision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failu re or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinaft er, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, dir ectly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9609BE 1997.08 NIPPON PRECISION CIRCUITS INC.