SLG7NT4850VTR

SLG7NT4850 DIALOG

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 10

Technical content

Features

• Low Power Consumption
• Pb-Free / RoHS Compliant
• Halogen-Free
• STQFN-20 Package Output Summary
• 8 Outputs — Open Drain NMOS 1X Pin Configuration 11 8 9 10 20 19 18 STQFN-20 TOP VIEW VDD SLG7NT4850 GND WAKE PWRBTN# AC_PRESENT_SOC AC_OK_CHGR SKL_APL_N SLP_S0ix_N PCH_PWROK IMVP_VR_ON VNN_COMP DDR_VR_PWRGD VCCSTG SLP_S3_N VCCST VTT_CTRL PWRBTN_EC 5VR_PWRGD VCCST_PWRGD VNN_PGD Silego SLG7NT4850 is a low power and small form device. The SoC is hou sed in a 2mm x 3mm STQFN package which is optimal for using with small devices.

SLG7NT4850_DS_r102 SLG7NT4850 Pin Configuration Pin # Pin Name Type Pin Description

1 VDD PWR Supply Voltage

2 WAKE Digital Input Digital Input without Schmitt trigger

3 PWRBTN# Digital Input Digital Input with Schmitt trigger

4 AC_PRESENT_SOC Digital Output Open Drain NMOS 1X

5 AC_OK_CHGR Digital Input Digital Input without Schmitt trigger

6 SKL_APL_N Analog Input/Output Analog Input/Output

7 SLP_S0ix_N Digital Input Low Voltage Digital Input

8 PCH_PWROK Digital Output Open Drain NMOS 1X

9 IMVP_VR_ON Digital Output Open Drain NMOS 1X

10 VNN_COMP Analog Input/Output Analog Input/Output

11 GND GND Ground

12 DDR_VR_PWRGD Digital Input Low Voltage Digital Input

13 VCCSTG Analog Input/Output Analog Input/Output

14 SLP_S3_N Digital Input Low Voltage Digital Input

15 VCCST Analog Input/Output Analog Input/Output

16 VCCST_PWRGD Digital Output Open Drain NMOS 1X

17 VNN_PGD Digital Output Open Drain NMOS 1X

18 VTT_CTRL Digital Output Open Drain NMOS 1X

19 PWRBTN_EC Digital Output Open Drain NMOS 1X

20 5VR_PWRGD Digital Output Open Drain NMOS 1X

Ordering Information

SLG7NT4850V V=STQFN-20 SLG7NT4850VTR VTR=STQFN-20 – Tape and Reel (3k units)

SLG7NT4850_DS_r102 SLG7NT4850 Absolute Maximum Conditions Parameter Min. Max. Unit VHIGH to GND -0.3 7 V Voltage at input pins -0.3 7 V Current at input pin -1.0 1.0 mA Storage temperature range -65 150 °C Junction temperature -- 150 °C ESD Protection (Human Body Model) 2000 -- V ESD Protection (Charged Device Model) 1300 -- V Moisture Sensitivity Level 1

Electrical Characteristics

(@ 25°C, unless otherwise stated) Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 1.659 3.3 5.665 V TA Operating Temperature -40 25 85 °C IQ Quiescent Current Static inputs and outputs @VDD=5.665V -- 80 -- µA VO Maximal Voltage Applied to any PIN in High-Impedance State -- -- VDD V IO Maximal Average or DC Current (note 1) Per Each Chip Side (PIN2-PIN10, PIN12-PIN20) -- -- 90 mA VIH HIGH-Level Input Voltage Logic Input, at VDD=1.8V 1.10 -- VDD V Logic Input with Schmitt Trigger, at VDD=1.8V 1.27 -- VDD Low-Level Logic Input, at VDD=1.8V 0.98 -- VDD Logic Input, at VDD=3.3V 1.78 -- VDD Logic Input with Schmitt Trigger, at VDD=3.3V 2.13 -- VDD Low-Level Logic Input, at VDD=3.3V 1.13 -- VDD Logic Input, at VDD=5.0V 2.64 -- VDD Logic Input with Schmitt Trigger, at VDD=5.0V 3.16 -- VDD Low-Level Logic Input, at VDD=5.0V 1.23 -- VDD VIL LOW-Level Input Voltage Logic Input, at VDD=1.8V -- -- 0.69 V Logic Input with Schmitt Trigger, at VDD=1.8V -- -- 0.44 Low-Level Logic Input, at VDD=1.8V -- -- 0.52 Logic Input, at VDD=3.3V -- -- 1.21 Logic Input with Schmitt Trigger, at VDD=3.3V -- -- 0.95 Low-Level Logic Input, at VDD=3.3V -- -- 0.69 Logic Input, at VDD=5.0V -- -- 1.84

SLG7NT4850_DS_r102 SLG7NT4850 Logic Input with Schmitt Trigger, at VDD=5.0V -- -- 1.51 Low-Level Logic Input, at VDD=5.0V -- -- 0.78 IIH HIGH-Level Input Current Logic Input PINs; VIN = VDD -1.0 -- 1.0 µA IIL LOW-Level Input Current Logic Input PINs; VIN = 0V -1.0 -- 1.0 µA VOL LOW-Level Output Voltage Open Drain, IOL = 100uA, 1X Driver, at VDD=1.8 V -- 0.005 0.020 V Open Drain, IOL = 3mA, 1X Driver, at VDD=3.3 V -- 0.080 0.147 Open Drain, IOL = 5mA, 1X Driver, at VDD=5.0 V -- 0.102 0.180 IOL LOW-Level Output Current Open Drain, VOL =0.15V, 1X Driver, at VDD=1.8 V 1.375 2.534 -- mA Open Drain, VOL =0.4V, 1X Driver, at VDD=3.3 V 7.313 12.37 -- Open Drain, VOL =0.4V, 1X Driver, at VDD=5.0 V 10.82 17.38 -- VACMP0 Analog Comparator Threshold Voltage ACMP0 threshold including input offset, reference voltage variation and hysteresis. 1034 -- 1342 mV VACMP1 Analog Comparator Threshold Voltage ACMP1 threshold including input offset, reference voltage variation and hysteresis. 522 -- 682 mV VACMP2 Analog Comparator Threshold Voltage ACMP2 threshold including input offset, reference voltage variation and hysteresis. 735 -- 848 mV VACMP3 Analog Comparator Threshold Voltage ACMP3 threshold including input offset, reference voltage variation and hysteresis. 735 -- 848 mV VHYST Analog Comparator Hysteresis Voltage (note 1) ACMP 2, 3 -- 25 -- mV ACMP 1 -- 50 -- TDLY5 Delay5 Time At temperature 25°C 252.88 300 334.25 µs At temperature -40°C +85°C (note 1) 229.09 300 395.73 TSU Start up Time From VDD rising past 1.35V -- 0.3 -- ms 1. Guaranteed by Design.

SLG7NT4850_DS_r102 SLG7NT4850 Timing Diagram 1. Case 1: PIN#6(SKL_APL_N) - LOW

SLG7NT4850_DS_r102 SLG7NT4850 2. Case 2: PIN#6(SKL_APL_N) - HIGH

SLG7NT4850_DS_r102 SLG7NT4850 Package Top Marking Datasheet Revision Programming Code Number Locked Status Part Code Revision Date 1.02 003 U 4850V AA 03/11/2016 The IC security bit is locked/set for code security for production unless otherwise specified. Revision number is not changed for bit locking.

SLG7NT4850_DS_r102 SLG7NT4850 Package Drawing and Dimensions

20 Lead STQFN Package

JEDEC MO-220, Variation WECE IC Net Weight: 0.015 g

SLG7NT4850_DS_r102 SLG7NT4850 Tape and Reel Specification Package Type # of Pins Nominal Package Size (mm) Max Units Reel & Hub Size (mm) Trailer A Leader B Pocket (mm) per reel per box Pockets Length (mm) Pockets Length (mm) Width Pitch STQFN 20L 2x3mm 0.4P Green 20 2x3x0.55 3000 3000 178/60 100 400 100 400 8 4 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Length (mm) Pocket BTM Width (mm) Pocket Depth (mm) Index Hole Pitch (mm) Pocket Pitch (mm) Index Hole Diameter (mm) Index Hole to Tape Edge (mm) Index Hole to Pocket Center (mm) Tape Width (mm) A0 B0 K0 P0 P1 D0 E F W STQFN 20L 2x3mm 0.4P Green Refer to EIA-481 Specifications Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 3.3 mm3 (nominal). More information can be found at www.jedec.org.

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