SLG7NT4445

SLG7NT4445 DIALOG

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 12

Technical content

Features

• Low Power Consumption
• Dynamic Voltage Supply Range
• RoHS Compliant / Halogen-Free
• Pb-Free TDFN-12 Package
• MSL1 Pin Configuration TDFN-12 TOP VIEW Thermal Pad connected to GND Output Summary
• 1 Output — Push Pull 1X
• 4 Outputs — Open Drain NMOS 1X VDD PWR_BTN_L BATT_ENABLE AC_PRESENT KSO_SW KSI_SW GND KSI KSO_INV EC_ENTERING_RW EC_IN_RW EC_RST_L SLG7NT4445 Silego GreenPAK 2 SLG7NT4445 is a low power and small form device. The SoC is housed in a 2.5mm x 2.5mm TDFN package which is optimal for using with small devices.

Reset IC with Latch and MUX SLG7NT4445 SLG7NT4445_DS_r102 Page 2 Block Diagram

Reset IC with Latch and MUX SLG7NT4445 SLG7NT4445_DS_r102 Page 3 Pin Configuration Pin # Pin Name Type Pin Description

1 VDD PWR Supply Voltage

2 PWR_BTN_L Digital Input Digital Input with Schmitt trigger

3 BATT_ENABLE Digital Output Open Drain NMOS 1X

4 AC_PRESENT Digital Input Low Voltage Digital Input

5 KSO_SW Digital Output Open Drain NMOS 1X

6 KSI_SW Digital Input Digital Input with Schmitt trigger

7 GND GND Ground

8 KSI Digital Output Open Drain NMOS 1X

9 KSO_INV Digital Input Digital Input with Schmitt trigger

10 EC_ENTERING_RW Digital Input Digital Input with Schmitt trigger

11 EC_IN_RW Digital Output Open Drain NMOS 1X

12 EC_RST_L Bi-directional Digital Input withSchmitt trigger / Push

Bottom Pad Exposed Bottom Pad GND Ground

Ordering Information

SLG7NT4445V V = TDFN-12 SLG7NT4445VTR VTR = TDFN-12 - Tape and Reel (3k units)

Reset IC with Latch and MUX SLG7NT4445 SLG7NT4445_DS_r102 Page 4 Absolute Maximum Conditions Parameter Min. Max. Unit VHIGH to GND -0.3 7 V Voltage at input pins -0.3 7 V Current at input pin -1.0 1.0 mA Storage temperature range -65 150 °C Junction temperature -- 150 °C

Electrical Characteristics

(@ 25°C, unless otherwise stated) Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 1.71 -- 5.5 V TA Operating Temperature -40 25 85 °C IQ Quiescent Current Static i nputs and outputs -- 1 -- µA IA Active Current Static inputs and outputs -- 15 -- µA VO Maximal Voltage Applied to any PIN in High-Impedance State -- -- VDD V IO Maximal Average or DC Current (note 1) Per Each Chip Side -- -- 24 mA VIH HIGH-Level Low Voltage Input Voltage Logic Input with Schmitt Trigger, at VDD=1.8V 1.35 -- VDD V Low-Level Logic Input, at VDD=1.8V 1.1 -- VDD Logic Input with Schmitt Trigger, at VDD=3.3V 2.3 -- VDD Low-Level Logic Input, at VDD=3.3V 1.5 -- VDD Logic Input with Schmitt Trigger, at VDD=5.0V 3.2 -- VDD Low-Level Logic Input, at VDD=5.0V 1.7 -- VDD VIL LOW-Level Low Voltage Input Voltage Logic Input with Schmitt Trigger, at VDD=1.8V -- -- 0.45 V Low-Level Logic Input, at VDD=1.8V -- -- 0.50 Logic Input with Schmitt Trigger, at VDD=3.3V -- -- 0.92 Low-Level Logic Input, at VDD=3.3V -- -- 0.66 Logic Input with Schmitt Trigger, at VDD=5.0V -- -- 1.3

Reset IC with Latch and MUX SLG7NT4445 SLG7NT4445_DS_r102 Page 5 Low-Level Logic Input, at VDD=5.0V -- -- 0.77 IIH HIGH-Level Input Cu rrent Logic Input Pins;V IN = VDD -1.0 -- 1.0 μA IIL LOW-Level Input Current Logic Input Pins; V IN = 0V -1.0 -- 1.0 μA VOH HIGH-Level Output Voltage (note 1) Push Pull, IOH = 100uA, 1X Driver, at VDD=1.8 V 1.66 -- -- V Push Pull, IOH = 700uA, 1X Driver, at VDD=1.8 V 1.21 -- -- Push Pull, IOH = 3mA, 1X Driver, at VDD=3.3 V 2.1 -- -- Push Pull, IOH = 5mA, 1X Driver, at VDD=5.0 V 3.6 -- -- Push Pull, IOH = 8mA, 1X Driver, at VDD=5.0 V 2.9 -- -- VOL LOW-Level Output Voltage (note 1) Push Pull, IOL = 100uA, 1X Driver, at VDD=1.8 V -- -- 0.040 V Push Pull, IOL = 700uA, 1X Driver, at VDD=1.8 V -- -- 0.415 Open Drain, IOL = 5mA, 1X Driver, at VDD=1.8 V -- -- 0.340 Push Pull, IOL = 3mA, 1X Driver, at VDD=3.3 V -- -- 0.81 Open Drain, IOL = 20mA, 1X Driver, at VDD=3.3 V -- -- 0.605 Push Pull, IOL = 5mA, 1X Driver, at VDD=5.0 V -- -- 0.85 Push Pull, IOL = 8mA, 1X Driver, at VDD=5.0 V -- -- 1.2 Open Drain, IOL = 20mA, 1X Driver, at VDD=5.0 V -- -- 0.36 IOL LOW-Level Output Current (note 1) Push Pull, V OL =0.15V, 1X Driver, at VDD=1.8 V 0.34 -- -- mA Open Drain, VOL =0.15V, 1X Driver, at VDD=1.8 V 2.72 -- -- Push Pull, VOL =0.4V, 1X Driver, at VDD=3.3 V 1.836 -- -- Open Drain, VOL =0.4V, 1X Driver, at VDD=3.3 V 14.688 -- -- Push Pull, VOL =0.4V, 1X Driver, at VDD=5.0 V 2.745 -- --

Reset IC with Latch and MUX SLG7NT4445 SLG7NT4445_DS_r102 Page 6 Open Drain, VOL =0.4V, 1X Driver, at VDD=5.0 V 21.96 -- -- RPULL_UP Internal Pull Up Resistance Pull up on PINs 6, 12 35 50 65 k Ω RPULL_DOWN Internal Pull Down Resistance Pull down on PIN10 35 50 65 kΩ Pull down on PIN9 210 300 390 TDLY0 Delay0 Time At temperature 25°C 4.13 5 5.88 ms TDLY1 Delay1 Time At temperature 25°C 8.27 10 11.7 ms TDLY2 Delay2 Time At temperature 25°C 5 -- 7.042 s TDLY3 Delay3 Time At temperature 25°C 60 -- 127 µs TSU Start up Time After VDD reache s 1.6V level -- 7 -- ms 1. Guaranteed by Design.

Reset IC with Latch and MUX SLG7NT4445 SLG7NT4445_DS_r102 Page 7

Description

This device is a reset IC with one shot function, internal Latching system, level shifter and multiplexor. The reset (active LOW) occurs when both PWR_ BTN_L (PIN2) and KSI_SW (PIN6) ar e LOW. PWR_BTN_L (PIN2) has 5ms deglitch delay on its line. Also reset logics contains one more 100µs deglitch delay is used. The signal from this delay goes to 10ms one-shot system that creates 10ms LOW pulse on reset event. If PWR_BTN_L and KSI_SW are LOW, and AC_PRESENT (PIN4) transitions from HUGH to LOW, these three conditions will latch the BATT_ENABLE (PIN3) LOW for 5 seconds minimum. During this EC_RST_L will be asserted and EC_IN_RW will go LOW as well. EC_RST_L is configured to be bidirectional, so it will operate as digital input with Schmitt trigger or as Low Level Digital Output. Also SLG7NT4445 includes latching system. Its inputs are EC_RST_L and EC_ENTERING_RW. EC_IN_RW is an output configured as open drain. This system is initialized with logic HIGH on its output. It is latched LOW when EC_RST_L goes LOW until EC_ENTERING_RW goes HIGH. Multiplexing system in this device follow the logic: KSI = !(PWR_BTN_L) | KSI_SW If the AC_PRESENT / BATTERY_ENABLE functionality is not needed, BA TTERY_ENABLE can be left floating but AC_PRESENT should be tied low. All pins are in a high impedance state until the chip has powered up.

Reset IC with Latch and MUX SLG7NT4445 SLG7NT4445_DS_r102 Page 8 Timing Diagram

e num G7NT4445_ ackage To Datashee Revision 1.02 e IC securit mber is not _DS_r102 op Markin et n Prog Code ty bit is lock t changed f ng ramming e Number 002 ked/set for for bit lockin Locked Status L code secur ng. R d Par rity for prod Reset IC rt Code 445V duction unle C with L Revisio AB ess otherwis Latch a SLG7 on se specified nd MUX 7NT444 Page 9 Date 6/30/2015 d. Revision X n

G7NT4445_ ackage D _DS_r102 rawing an nd Dimen JE nsions

12 Lead

R d TDFN Pac 252, Variat Reset IC ckage tion 2525E C with L E Latch a SLG7 nd MUX 7NT444 Page 10 X

Reset IC with Latch and MUX SLG7NT4445 SLG7NT4445_DS_r102 Page 11 Tape and Reel Specification Package Type # of Pins Nominal Package Size (mm) Max Units Reel & Hub Size (mm) Trailer A Leader B Pocket (mm) per reel per box Pockets Length (mm) Pockets Length (mm) Width Pitch TDFN 12L 2.5x2.5mm 0.4P Green 12 2.5x2.5x0.75 3000 3000 178/60 42 168 42 168 8 4 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Length (mm) Pocket BTM Width (mm) Pocket Depth (mm) Index Hole Pitch (mm) Pocket Pitch (mm) Index Hole Diameter (mm) Index Hole to Tape Edge (mm) Index Hole to Pocket Center (mm) Tape Width (mm) A0 B0 K0 P0 P1 D0 E F W TDFN 12L 2.5x2.5mm 0.4P Green Refer to EIA-481 Specifications Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 4.6875 mm3 (nominal). More information can be found at www.jedec.org.

Reset IC with Latch and MUX SLG7NT4445 SLG7NT4445_DS_r102 Page 12 Silego Website & Support Silego Technology Website Silego Technology provides online support via our website at http://www.silego.com/.This website is used as a means to make files and information easily available to customers. For more information regarding Silego Green products, please visit: http://greenpak.silego.com/ http://greenpak2.silego.com/ http://greenfet.silego.com/ http://greenfet2.silego.com/ http://greenclk.silego.com/ Products are also available for purchase directly from Silego at the Silego Online Store at http://store.silego.com/. Silego Technical Support Datasheets and errata, application notes and example designs, user guides, and hardware support documents and the latest software releases are available at the Silego website or can be requested directly at info@silego.com. For specific GreenPAK design or applications questions and support please send email requests to GreenPAK@silego.com Users of Silego products can receive assistance through several channels: Contact Your Local Sales Representative Customers can contact their local sales representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. More information regarding your local representative is available at the Silego website or send a request to info@silego.com Contact Silego Directly Silego can be contacted directly via e-mail at info@silego.com or user submission form, located at the following URL: http://support.silego.com/ Other Information The latest Silego Technology press releases, listing of seminars and events, listings of worldwide Silego Technology offices and representatives are all available at http://www.silego.com/ THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. SILEGO TECHNOLOGY DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. SILEGO TECHNOLOGY RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTICE.