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  • Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 11

Technical content

Features

  • Low Power Consumption
  • Pb-Free / RoHS Compliant
  • Halogen-Free
  • STQFN-12 Package
  • MSL “1” Output Summary
  • 3 Outputs — Push Pull 1X
  • 1 Output — Push Pull 2X Pin Configuration 4 5 6 12 11 STQFN-12 TOP VIEW VDD VPP (2.5V) SLP_S3#/DDR_VTT_CNTL VPP_EN VTT_EN VDDQ(1.2V) GND VDDQ_BLEED VDDQ_EN SLP_S4# +V3P3A NC Silego SLG7N T4375 is a low power and small form device. The SoC is housed in a 1.6 x 1.6 mm STQFN package which is optimal for using with small devices.

SLG7NT4375_DS_r101 Page 2 Block Diagram

SLG7NT4375_DS_r101 Page 3 Pin Configuration Pin # Pin Name Type Pin Description

1 VDD PWR Supply Voltage

2 VPP (2.5V) Digital Input Low Voltage Digital input

3 SLP_S3#/DDR_VTT_CNTL Analog

Input/Output Analog Input/Output

4 VPP_EN Digital Output Push Pull 1X

5 VTT_EN Digital Output Push Pull 1X

6 VDDQ(1.2V) Analog Input/Output Analog Input/Output

7 GND GND Ground

8 VDDQ_BLEED Digital Output Push Pull 1X

9 VDDQ_EN Digital Output Push Pull 2X

10 SLP_S4# Digital Input Digital Input without Schmitt trigger

11 +V3P3A Digital Input Digital Input without Schmitt trigger

12 NC -- Keep Floating or Connect to GND

Ordering Information

SLG7NT4375V V=STQFN-12 SLG7NT4375VTR STQFN-12 – Tape and Reel (3k units)

SLG7NT4375_DS_r101 Page 4 Absolute Maximum Conditions Parameter Min. Max. Unit VHIGH to GND -0.3 7 V Voltage at input pins -0.3 7 V Current at input pin -1.0 1.0 mA Storage temperature range -65 150 °C Junction temperature -- 150 °C

Electrical Characteristics

(@ 25°C, unless otherwise stated) Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 3 3.3 3.6 V TA Operating Temperature -40 25 85 °C IQ Quiescent Current Static inputs and outputs -- 70 -- µA VO Maximal Voltage Applied to any PIN in High-Impedance State -- -- VDD V IO Maximal Average or DC Current Per Each Chip Side -- -- 90 mA VIH HIGH-Level Input Voltage Logic Input, at VDD=3.3V 1.4 -- VDD V Low-Level Logic Input, at VDD=3.3V 0.91 -- VDD VIL LOW-Level Input Voltage Logic Input, at VDD=3.3V -- -- 1.65 V Low-Level Logic Input, at VDD=3.3V -- -- 0.95 IIH HIGH-Level Input Current Logic Input PINs; VIN = VDD -1.0 -- 1.0 µA IIL LOW-Level Input Current Logic Input PINs; VIN = 0V -1.0 -- 1.0 µA VOH HIGH-Level Output Voltage Push Pull, IOH = 3mA, 1X Driver, at VDD=3.3 V 2.73 3.13 -- V Push Pull, IOH = 3mA, 2X Driver, at VDD=3.3 V 2.87 3.22 -- VOL LOW-Level Output Voltage Push Pull, IOL = 3mA, 1X Driver, at VDD=3.3 V -- 0.15 0.28 V Push Pull, IOL = 3mA, 2X Driver, at VDD=3.3 V -- 0.07 0.13 IOH HIGH-Level Output Current Push Pull & PMOS OD, VOH = 2.4 V, 1X Driver, at VDD=3.3 V 6.01 12.07 -- mA Push Pull & PMOS OD, VOH = 2.4 V, 2X Driver, at VDD=3.3 V 12.01 24.13 -- IOL LOW-Level Output Current Push Pull, VOL =0.4V, 1X Driver, at VDD=3.3 V 4.06 6.92 -- mA Push Pull, VOL =0.4V, 2X Driver, at VDD=3.3 V 8.13 13.84 -- VACMP0 Analog Comparator Threshold Voltage ACMP0 threshold including input offset, reference voltage variation and hysteresis. 620 -- 677 mV VACMP1 Analog Comparator Threshold Voltage ACMP1 threshold including input offset, reference voltage variation and hysteresis. 186 -- 214 mV TSU Start up Time From VDD rising past 1.6V -- 1 -- ms

SLG7NT4375_DS_r101 Page 5 Functionality Waveforms Channel 1 (yellow/top line) – PIN#3 (SLP_S3#/DDR_VTT_CNTL) Channel 2 (light blue/2nd line) – PIN#6 (VDDQ(1.2V)) D0 – PIN#2 (VPP (2.5V)) D1 – PIN#11 (+V3P3A) D2 – PIN#10 (SLP_S4#) D3 – PIN#9 (VDDQ_EN) D4 – PIN#8 (VDDQ_BLEED) D5 – PIN#5 (VTT_EN) D6 – PIN#4 (VPP_EN) 1. Device general operation

SLG7NT4375_DS_r101 Page 6 D0 – PIN#10 (SLP_S4#) D1 – PIN#11 (+V3P3A) D2 – PIN#4 (VPP_EN) Channel 1 (yellow/top line) – PIN#3 (SLP_S3#/DDR_VTT_CNTL) D3 – PIN#9 (VDDQ_EN) Channel 2 (light blue/2nd line) – PIN#6 (VDDQ(1.2V)) D4 – PIN#8 (VDDQ_BLEED) 2. Enable PIN: SLP_S4# D0 – PIN#11 (+V3P3A) Channel 1 (yellow/top line) – PIN#3 (SLP_S3#/DDR_VTT_CNTL) D1 – PIN#5 (VTT_EN) 3. VTT_EN operation

SLG7NT4375_DS_r101 Page 7 Package Top Marking Datasheet Revision Programming Code Number Locked Status Part Code Revision Date 1.01 004 L YV B 02/23/2015 The IC security bit is locked/set for code security for production unless otherwise specified. Revision number is not changed for bit locking.

SLG7NT4375_DS_r101 Page 8 Package Drawing and Dimensions

12 Lead STQFN Package

SLG7NT4375_DS_r101 Page 9 Tape and Reel Specification Package Type # of Pins Nominal Package Size (mm) Max Units Reel & Hub Size (mm) Trailer A Leader B Pocket (mm) per reel per box Pockets Length (mm) Pockets Length (mm) Width Pitch STQFN 12L FCA 0.4P Green 12 1.6x1.6x0.55 3000 3000 178/60 100 400 100 400 8 4 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Length (mm) Pocket BTM Width (mm) Pocket Depth (mm) Index Hole Pitch (mm) Pocket Pitch (mm) Index Hole Diameter (mm) Index Hole to Tape Edge (mm) Index Hole to Pocket Center (mm) Tape Width (mm) A0 B0 K0 P0 P1 D0 E F W STQFN 12L FCA 0.4P Green Refer to EIA-481 Specifications Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 1.408 mm3 (nominal). More information can be found at www.jedec.org.

SLG7NT4375_DS_r101 Page 10 Datasheet Revision History Date Version Change 03/27/2014 0.10 New designSLG46120 03/28/2014 0.11 Corrected device functionality 04/02/2014 0.12 Change PIN5 name VTT to VTT_EN, correctedElectrical Characteristics 04/24/2014 0.13 Removed LATCH from VPP_EN, ACMP1 Vref changed to 200mV 04/28/2014 0.14 Added one more Functionality Waveform 05/05/2014 0.15 Added additional Functionality Waveforms 05/23/2014 0.16 Version update 07/25/2014 0.17 Updated Device Revision Table 08/25/2014 0.18 Added MSL “1” Renamed Package to FCA package 09/03/2014 0.19 Changed PIN11 name, updated functionality waveforms 09/05/2014 0.20 Removed one functionality waveform 09/25/2014 0.21 Updated Device Revision Table 10/02/2014 0.22 Changed Lock status 10/03/2014 0.23 Updated VIH, VIL logic levels 10/03/2014 0.24 Updated Device Revision Table 11/06/2014 1.00 Production Release 02/23/2015 1.01 Corrected VDDQ_EN output type

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